source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 402f4df

4.104.114.84.95
Last change on this file since 402f4df was 402f4df, checked in by Eric Norum <WENorum@…>, on Apr 10, 2005 at 9:10:32 PM

Set up IRQ1* handling properly.

  • Property mode set to 100644
File size: 17.5 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29#include <errno.h>
30 
31/*
32 *  The original table from the application and our copy of it with
33 *  some changes.
34 */
35extern rtems_configuration_table Configuration;
36rtems_configuration_table  BSP_Configuration;
37rtems_cpu_table Cpu_table;
38char *rtems_progname;
39
40/*
41 * Location of 'VME' access
42 */
43#define VME_ONE_BASE    0x30000000
44#define VME_TWO_BASE    0x31000000
45
46/*
47 * CPU-space access
48 * The NOP after writing the CACR is there to address the following issue as
49 * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
50 *
51 * 6 Possible Cache Corruption after Setting  CACR[CINV]
52 * 6.1 Description
53 * The cache on the MCF5282 was enhanced to function as a unified data and
54 * instruction cache, an instruction cache, or an operand cache.  The cache
55 * function and organization is controlled by the cache control register (CACR).
56 * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
57 * If the cache is configured as a unified cache and the CINV bit is set, the
58 * scope of the cache clear is controlled by two other bits in the CACR,
59 * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
60 * cache only).  These bits allow the entire cache, just the instruction
61 * portion of the cache, or just the data portion of the cache to be cleared.
62 * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
63 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
64 * then cache corruption may  occur.
65 *
66 * 6.2 Workaround
67 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
68 * should be followed immediately by a NOP instruction.  This avoids the cache
69 * corruption problem.
70 * DATECODES AFFECTED: All
71 */
72#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr ; nop" : : "d" (_cacr))
73#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
74#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
75
76/*
77 * Read/write copy of common cache
78 *   Split I/D cache
79 *   Allow CPUSHL to invalidate a cache line
80 *   Enable buffered writes
81 *   No burst transfers on non-cacheable accesses
82 *   Default cache mode is *disabled* (cache only ACRx areas)
83 */
84static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
85                              MCF5XXX_CACR_DBWE |
86                              MCF5XXX_CACR_DCM;
87/*
88 * Cannot be frozen
89 */
90void _CPU_cache_freeze_data(void) {}
91void _CPU_cache_unfreeze_data(void) {}
92void _CPU_cache_freeze_instruction(void) {}
93void _CPU_cache_unfreeze_instruction(void) {}
94
95/*
96 * Write-through data cache -- flushes are unnecessary
97 */
98void _CPU_cache_flush_1_data_line(const void *d_addr) {}
99void _CPU_cache_flush_entire_data(void) {}
100
101void _CPU_cache_enable_instruction(void)
102{
103    rtems_interrupt_level level;
104
105    rtems_interrupt_disable(level);
106    cacr_mode &= ~MCF5XXX_CACR_DIDI;
107    m68k_set_cacr(cacr_mode);
108    rtems_interrupt_enable(level);
109}
110
111void _CPU_cache_disable_instruction(void)
112{
113    rtems_interrupt_level level;
114
115    rtems_interrupt_disable(level);
116    cacr_mode |= MCF5XXX_CACR_DIDI;
117    m68k_set_cacr(cacr_mode);
118    rtems_interrupt_enable(level);
119}
120
121void _CPU_cache_invalidate_entire_instruction(void)
122{
123    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
124}
125
126void _CPU_cache_invalidate_1_instruction_line(const void *addr)
127{
128    /*
129     * Top half of cache is I-space
130     */
131    addr = (void *)((int)addr | 0x400);
132    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
133}
134
135void _CPU_cache_enable_data(void)
136{
137    rtems_interrupt_level level;
138
139    rtems_interrupt_disable(level);
140    cacr_mode &= ~MCF5XXX_CACR_DISD;
141    m68k_set_cacr(cacr_mode);
142    rtems_interrupt_enable(level);
143}
144
145void _CPU_cache_disable_data(void)
146{
147    rtems_interrupt_level level;
148
149    rtems_interrupt_disable(level);
150    rtems_interrupt_disable(level);
151    cacr_mode |= MCF5XXX_CACR_DISD;
152    m68k_set_cacr(cacr_mode);
153    rtems_interrupt_enable(level);
154}
155
156void _CPU_cache_invalidate_entire_data(void)
157{
158    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
159}
160
161void _CPU_cache_invalidate_1_data_line(const void *addr)
162{
163    /*
164     * Bottom half of cache is D-space
165     */
166    addr = (void *)((int)addr & ~0x400);
167    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
168}
169
170/*
171 *  Use the shared implementations of the following routines
172 */
173void bsp_postdriver_hook(void);
174void bsp_libc_init( void *, uint32_t, int );
175void bsp_pretasking_hook(void);         /* m68k version */
176
177/*
178 *  bsp_start
179 *
180 *  This routine does the bulk of the system initialisation.
181 */
182void bsp_start( void )
183{
184  extern char _WorkspaceBase[];
185  extern char _RamBase[], _RamSize[];
186  extern unsigned long  _M68k_Ramsize;
187
188  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
189
190  /*
191   *  Allocate the memory for the RTEMS Work Space.  This can come from
192   *  a variety of places: hard coded address, malloc'ed from outside
193   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
194   *  typically done by stock BSPs) by subtracting the required amount
195   *  of work space from the last physical address on the CPU board.
196   */
197
198  /*
199   *  Need to "allocate" the memory for the RTEMS Workspace and
200   *  tell the RTEMS configuration where it is.  This memory is
201   *  not malloc'ed.  It is just "pulled from the air".
202   */
203
204  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
205
206  /*
207   *  initialize the CPU table for this BSP
208   */
209  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
210  Cpu_table.postdriver_hook = bsp_postdriver_hook;
211  Cpu_table.do_zero_of_workspace = TRUE;
212  Cpu_table.interrupt_stack_size = 4096;
213
214  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
215
216    /*
217     * Invalidate the cache and disable it
218     */
219    m68k_set_acr0(0);
220    m68k_set_acr1(0);
221    m68k_set_cacr(MCF5XXX_CACR_CINV);
222
223    /*
224     * Cache SDRAM
225     */
226    m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
227                  MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
228                  MCF5XXX_ACR_EN                         |
229                  MCF5XXX_ACR_BWE                        |
230                  MCF5XXX_ACR_SM_IGNORE);
231
232    /*
233     * Enable the cache
234     */
235    m68k_set_cacr(cacr_mode);
236
237    /*
238     * Set up CS* space (fake 'VME')
239     *   Two A24/D16 spaces, supervisor data acces
240     */
241    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
242    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
243                       MCF5282_CS_CSMR_CI |
244                       MCF5282_CS_CSMR_SC |
245                       MCF5282_CS_CSMR_UC |
246                       MCF5282_CS_CSMR_UD |
247                       MCF5282_CS_CSMR_V;
248    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
249    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
250    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
251                       MCF5282_CS_CSMR_CI |
252                       MCF5282_CS_CSMR_SC |
253                       MCF5282_CS_CSMR_UC |
254                       MCF5282_CS_CSMR_UD |
255                       MCF5282_CS_CSMR_V;
256    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
257}
258
259uint32_t bsp_get_CPU_clock_speed(void)
260{
261    extern char _CPUClockSpeed[];
262    return( (uint32_t)_CPUClockSpeed);
263}
264
265/*
266 * Interrupt controller allocation
267 */
268rtems_status_code
269bsp_allocate_interrupt(int level, int priority)
270{
271    static char used[7];
272    rtems_interrupt_level l;
273    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
274
275    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
276        return RTEMS_INVALID_NUMBER;
277    rtems_interrupt_disable(l);
278    if ((used[level-1] & (1 << priority)) == 0) {
279        used[level-1] |= (1 << priority);
280        ret = RTEMS_SUCCESSFUL;
281    }
282    rtems_interrupt_enable(l);
283    return ret;
284}
285
286/*
287 * Arcturus bootloader system calls
288 */
289#define syscall_return(type, ret)                      \
290do {                                                   \
291   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
292      errno = -(ret);                                  \
293      ret = -1;                                        \
294   }                                                   \
295   return (type)(ret);                                 \
296} while (0)
297#define syscall_1(type,name,d1type,d1)                      \
298type bsp_##name(d1type d1)                                  \
299{                                                           \
300   long ret;                                                \
301   register long __d1 __asm__ ("%d1") = (long)d1;           \
302   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
303                         "trap #2\n\t"                      \
304                         "move.l %%d0,%0"                   \
305                         : "=g" (ret)                       \
306                         : "i" (SysCode_##name), "d" (__d1) \
307                         : "d0" );                          \
308   syscall_return(type,ret);                                \
309}
310#define syscall_2(type,name,d1type,d1,d2type,d2)            \
311type bsp_##name(d1type d1, d2type d2)                       \
312{                                                           \
313   long ret;                                                \
314   register long __d1 __asm__ ("%d1") = (long)d1;           \
315   register long __d2 __asm__ ("%d2") = (long)d2;           \
316   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
317                         "trap #2\n\t"                      \
318                         "move.l %%d0,%0"                   \
319                         : "=g" (ret)                       \
320                         : "i" (SysCode_##name), "d" (__d1),\
321                                                 "d" (__d2) \
322                         : "d0" );                          \
323   syscall_return(type,ret);                                \
324}
325#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
326type bsp_##name(d1type d1, d2type d2, d3type d3)            \
327{                                                           \
328   long ret;                                                \
329   register long __d1 __asm__ ("%d1") = (long)d1;           \
330   register long __d2 __asm__ ("%d2") = (long)d2;           \
331   register long __d3 __asm__ ("%d3") = (long)d3;           \
332   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
333                         "trap #2\n\t"                      \
334                         "move.l %%d0,%0"                   \
335                         : "=g" (ret)                       \
336                         : "i" (SysCode_##name), "d" (__d1),\
337                                                 "d" (__d2),\
338                                                 "d" (__d3) \
339                         : "d0" );                          \
340   syscall_return(type,ret);                                \
341}
342#define SysCode_reset              0 /* reset */
343#define SysCode_program            5 /* program flash memory */
344#define SysCode_gethwaddr         12 /* get hardware address */
345#define SysCode_getbenv           14 /* get bootloader environment variable */
346#define SysCode_setbenv           15 /* get bootloader environment variable */
347#define SysCode_flash_erase_range 19 /* erase a section of flash */
348#define SysCode_flash_write_range 20 /* write a section of flash */
349syscall_1(unsigned const char *, gethwaddr, int, a)
350syscall_1(const char *, getbenv, const char *, a)
351syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
352syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
353syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
354
355/*
356 * 'Extended BSP' routines
357 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
358 */
359
360rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
361int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
362int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
363
364/*
365 * 'VME' interrupt support
366 * Interrupt vectors 192-255 are set aside for use by external logic which
367 * drives IRQ1*.  The actual interrupt source is read from the external
368 * logic at FPGA_IRQ_INFO.  The most-significant bit of the least-significant
369 * byte read from this location is set as long as the external logic has
370 * interrupts to be serviced.  The least-significant six bits indicate the
371 * interrupt source within the external logic and are used to select the
372 * specified interupt handler.
373 */
374#define NVECTOR 256
375#define FPGA_VECTOR (64+1)  /* IRQ1* pin connected to external FPGA */
376#define FPGA_EPPAR  MCF5282_EPORT_EPPAR_EPPA1_LEVEL
377#define FPGA_EPDDR  MCF5282_EPORT_EPDDR_EPDD1
378#define FPGA_EPIER  MCF5282_EPORT_EPIER_EPIE1
379#define FPGA_EPPDR  MCF5282_EPORT_EPPDR_EPPD1
380#define FPGA_IRQ_INFO    *((vuint16 *)(0x31000000 + 0xfffffe))
381
382static struct handlerTab {
383    BSP_VME_ISR_t func;
384    void         *arg;
385} handlerTab[NVECTOR];
386
387BSP_VME_ISR_t
388BSP_getVME_isr(unsigned long vector, void **pusrArg)
389{
390    if (vector >= NVECTOR)
391        return (BSP_VME_ISR_t)NULL;
392    if (pusrArg)
393        *pusrArg = handlerTab[vector].arg;
394    return handlerTab[vector].func;
395}
396
397static rtems_isr
398trampoline (rtems_vector_number v)
399{
400    /*
401     * Handle FPGA interrupts until all have been consumed
402     */
403    if (v == FPGA_VECTOR) {
404        while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
405            v = 192 + (v & 0x3f);
406            if (handlerTab[v].func) 
407                (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
408            else
409                rtems_fatal_error_occurred(v);
410        }
411    }
412    else if (handlerTab[v].func) 
413        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
414}
415
416int
417BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
418{
419    rtems_isr_entry old_handler;
420    rtems_interrupt_level level;
421
422    /*
423     * Register the handler information
424     */
425    if (vector >= NVECTOR)
426        return -1;
427    handlerTab[vector].func = handler;
428    handlerTab[vector].arg = usrArg;
429
430    /*
431     * If this is an external FPGA ('VME') vector set up the real IRQ.
432     */
433    if ((vector >= 192) && (vector <= 255)) {
434        int i;
435        static volatile int setupDone;
436        rtems_interrupt_disable(level);
437        if (setupDone) {
438            rtems_interrupt_enable(level);
439            return 0;
440        }
441        MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
442        MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
443        MCF5282_EPORT_EPIER |=  FPGA_EPIER;
444        MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
445                                MCF5282_INTC_IMRL_MASKALL);
446        setupDone = 1;
447        i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
448        rtems_interrupt_enable(level);
449        return i;
450    }
451
452    /*
453     * Make the connection between the interrupt and the local handler
454     */
455    rtems_interrupt_catch(trampoline, vector, &old_handler);
456
457    /*
458     * Find an unused level/priority if this is an on-chip (INTC0)
459     * source and this is the first time the source is being used.
460     * Interrupt sources 1 through 7 are fixed level/priority
461     */
462    if ((vector >= 65) && (vector <= 127)) {
463        int l, p;
464        int source = vector - 64;
465        static unsigned char installed[8];
466
467        rtems_interrupt_disable(level);
468        if (installed[source/8] & (1 << (source % 8))) {
469            rtems_interrupt_enable(level);
470            return 0;
471        }
472        installed[source/8] |= (1 << (source % 8));
473        rtems_interrupt_enable(level);
474        for (l = 1 ; l < 7 ; l++) {
475            for (p = 0 ; p < 8 ; p++) {
476                if ((source < 8)
477                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
478                    if (source >= 8)
479                        *(&MCF5282_INTC0_ICR1 + (source - 1)) = 
480                                                       MCF5282_INTC_ICR_IL(l) |
481                                                       MCF5282_INTC_ICR_IP(p);
482                    rtems_interrupt_disable(level);
483                    if (source >= 32)
484                        MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
485                    else
486                        MCF5282_INTC0_IMRL &= ~((1 << source) |
487                                                MCF5282_INTC_IMRL_MASKALL);
488                    rtems_interrupt_enable(level);
489                    return 0;
490                }
491            }
492        }
493        return -1;
494    }
495    return 0;
496}
497
498int
499BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
500{
501    if (vector >= NVECTOR)
502        return -1;
503    if ((handlerTab[vector].func != handler)
504     || (handlerTab[vector].arg != usrArg))
505        return -1;
506    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
507    return 0;
508}
509
510int
511BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
512{
513    unsigned long offset;
514
515    switch (am) {
516    default:    return -1;
517    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
518    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
519    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
520    }
521    *plocaladdr = vmeaddr + offset;
522    return 0;
523}
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