source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 3f0cfc56

4.104.114.84.95
Last change on this file since 3f0cfc56 was 3f0cfc56, checked in by Joel Sherrill <joel.sherrill@…>, on 03/11/07 at 15:24:18

2007-03-11 Joel Sherrill <joel@…>

  • startup/bspstart.c: Remove assignments of Cpu_table.do_zero_of_workspace to TRUE since TRUE is the default value in boot_card.c
  • Property mode set to 100644
File size: 22.5 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author: W. Eric Norum <norume@aps.anl.gov>
10 *
11 *  COPYRIGHT (c) 2005.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.OARcorp.com/rtems/license.html.
17 *
18 *  $Id$
19 */
20
21#include <bsp.h>
22#include <rtems/libio.h>
23#include <rtems/error.h>
24#include <rtems/libcsupport.h>
25#include <stdio.h>
26#include <string.h>
27#include <errno.h>
28 
29/*
30 *  The original table from the application and our copy of it with
31 *  some changes.
32 */
33extern rtems_configuration_table Configuration;
34rtems_configuration_table  BSP_Configuration;
35rtems_cpu_table Cpu_table;
36char *rtems_progname;
37
38/*
39 * Location of 'VME' access
40 */
41#define VME_ONE_BASE    0x30000000
42#define VME_TWO_BASE    0x31000000
43
44/*
45 * CPU-space access
46 * The NOP after writing the CACR is there to address the following issue as
47 * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
48 *
49 * 6 Possible Cache Corruption after Setting  CACR[CINV]
50 * 6.1 Description
51 * The cache on the MCF5282 was enhanced to function as a unified data and
52 * instruction cache, an instruction cache, or an operand cache.  The cache
53 * function and organization is controlled by the cache control register (CACR).
54 * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
55 * If the cache is configured as a unified cache and the CINV bit is set, the
56 * scope of the cache clear is controlled by two other bits in the CACR,
57 * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
58 * cache only).  These bits allow the entire cache, just the instruction
59 * portion of the cache, or just the data portion of the cache to be cleared.
60 * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
61 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
62 * then cache corruption may  occur.
63 *
64 * 6.2 Workaround
65 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
66 * should be followed immediately by a NOP instruction.  This avoids the cache
67 * corruption problem.
68 * DATECODES AFFECTED: All
69 */
70#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
71#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
72#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
73#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
74
75/*
76 * Read/write copy of cache registers
77 *   Split instruction/data or instruction-only
78 *   Allow CPUSHL to invalidate a cache line
79 *   Enable buffered writes
80 *   No burst transfers on non-cacheable accesses
81 *   Default cache mode is *disabled* (cache only ACRx areas)
82 */
83uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
84#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
85                             MCF5XXX_CACR_DISD |
86#endif
87                             MCF5XXX_CACR_DBWE |
88                             MCF5XXX_CACR_DCM;
89uint32_t mcf5282_acr0_mode = 0;
90uint32_t mcf5282_acr1_mode = 0;
91/*
92 * Cannot be frozen
93 */
94void _CPU_cache_freeze_data(void) {}
95void _CPU_cache_unfreeze_data(void) {}
96void _CPU_cache_freeze_instruction(void) {}
97void _CPU_cache_unfreeze_instruction(void) {}
98
99/*
100 * Write-through data cache -- flushes are unnecessary
101 */
102void _CPU_cache_flush_1_data_line(const void *d_addr) {}
103void _CPU_cache_flush_entire_data(void) {}
104
105void _CPU_cache_enable_instruction(void)
106{
107    rtems_interrupt_level level;
108
109    rtems_interrupt_disable(level);
110    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
111    m68k_set_cacr(mcf5282_cacr_mode);
112    rtems_interrupt_enable(level);
113}
114
115void _CPU_cache_disable_instruction(void)
116{
117    rtems_interrupt_level level;
118
119    rtems_interrupt_disable(level);
120    mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI;
121    m68k_set_cacr(mcf5282_cacr_mode);
122    rtems_interrupt_enable(level);
123}
124
125void _CPU_cache_invalidate_entire_instruction(void)
126{
127    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
128}
129
130void _CPU_cache_invalidate_1_instruction_line(const void *addr)
131{
132    /*
133     * Top half of cache is I-space
134     */
135    addr = (void *)((int)addr | 0x400);
136    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
137}
138
139void _CPU_cache_enable_data(void)
140{
141#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
142    rtems_interrupt_level level;
143
144    rtems_interrupt_disable(level);
145    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
146    m68k_set_cacr(mcf5282_cacr_mode);
147    rtems_interrupt_enable(level);
148#endif
149}
150
151void _CPU_cache_disable_data(void)
152{
153#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
154    rtems_interrupt_level level;
155
156    rtems_interrupt_disable(level);
157    rtems_interrupt_disable(level);
158    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
159    m68k_set_cacr(mcf5282_cacr_mode);
160    rtems_interrupt_enable(level);
161#endif
162}
163
164void _CPU_cache_invalidate_entire_data(void)
165{
166#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
167    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
168#endif
169}
170
171void _CPU_cache_invalidate_1_data_line(const void *addr)
172{
173#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
174    /*
175     * Bottom half of cache is D-space
176     */
177    addr = (void *)((int)addr & ~0x400);
178    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
179#endif
180}
181
182/*
183 *  Use the shared implementations of the following routines
184 */
185void bsp_postdriver_hook(void);
186void bsp_libc_init( void *, uint32_t, int );
187void bsp_pretasking_hook(void);         /* m68k version */
188
189/*
190 * The Arcturus boot ROM prints exception information improperly
191 * so use this default exception handler instead.  This one also
192 * prints a call backtrace
193 */
194static void handler(int pc)
195{
196    int level;
197    static volatile int reent;
198    extern char _RamSize[];
199
200    rtems_interrupt_disable(level);
201    if (reent++) bsp_reset(0);
202    {
203    int *p = &pc;
204    int info = p[-1];
205    int pc = p[0];
206    int format = (info >> 28) & 0xF;
207    int faultStatus = ((info >> 24) & 0xC) | ((info >> 16) & 0x3);
208    int vector = (info >> 18) & 0xFF;
209    int statusRegister = info & 0xFFFF;
210    int *fp;
211
212    printk("\n\nPC:%x  SR:%x  VEC:%x  FORMAT:%x  STATUS:%x\n", pc,
213                                                               statusRegister,
214                                                               vector,
215                                                               format,
216                                                               faultStatus);
217    fp = &p[-2];
218    for(;;) {
219        int *nfp = (int *)*fp;
220        if ((nfp <= fp)
221         || ((char *)nfp >= _RamSize)
222         || ((char *)(nfp[1]) >= _RamSize))
223            break;
224        printk("FP:%x -> %x    PC:%x\n", fp, nfp, nfp[1]);
225        fp = nfp;
226    }
227    }
228    rtems_task_suspend(0);
229    rtems_panic("done");
230}
231
232/*
233 *  bsp_start
234 *
235 *  This routine does the bulk of the system initialisation.
236 */
237void bsp_start( void )
238{
239  int i;
240  extern char _WorkspaceBase[];
241  extern char _RamBase[], _RamSize[];
242  extern unsigned long  _M68k_Ramsize;
243
244  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
245
246  /*
247   *  Allocate the memory for the RTEMS Work Space.  This can come from
248   *  a variety of places: hard coded address, malloc'ed from outside
249   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
250   *  typically done by stock BSPs) by subtracting the required amount
251   *  of work space from the last physical address on the CPU board.
252   */
253
254    /*
255     * Set up default exception handler
256     */
257    for (i = 2 ; i < 256 ; i++)
258        if (i != (32+2)) /* Catch all but bootrom system calls */
259            *((void (**)(int))(i * 4)) = handler;
260
261  /*
262   *  Need to "allocate" the memory for the RTEMS Workspace and
263   *  tell the RTEMS configuration where it is.  This memory is
264   *  not malloc'ed.  It is just "pulled from the air".
265   */
266
267  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
268
269  /*
270   *  initialize the CPU table for this BSP
271   */
272  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
273  Cpu_table.postdriver_hook = bsp_postdriver_hook;
274  Cpu_table.interrupt_stack_size = 4096;
275  {
276    extern void _BSP_Thread_Idle_body(void);
277    Cpu_table.idle_task = _BSP_Thread_Idle_body;
278  }
279  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
280
281    /*
282     * Invalidate the cache and disable it
283     */
284    m68k_set_acr0(mcf5282_acr0_mode);
285    m68k_set_acr1(mcf5282_acr1_mode);
286    m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
287
288    /*
289     * Cache SDRAM
290     */
291    mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
292                        MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
293                        MCF5XXX_ACR_EN                         |
294                        MCF5XXX_ACR_BWE                        |
295                        MCF5XXX_ACR_SM_IGNORE;
296    m68k_set_acr0(mcf5282_acr0_mode);
297
298    /*
299     * Enable the cache
300     */
301    m68k_set_cacr(mcf5282_cacr_mode);
302
303    /*
304     * Set up CS* space (fake 'VME')
305     *   Two A24/D16 spaces, supervisor data acces
306     */
307    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
308    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
309                       MCF5282_CS_CSMR_CI |
310                       MCF5282_CS_CSMR_SC |
311                       MCF5282_CS_CSMR_UC |
312                       MCF5282_CS_CSMR_UD |
313                       MCF5282_CS_CSMR_V;
314    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
315    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
316    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
317                       MCF5282_CS_CSMR_CI |
318                       MCF5282_CS_CSMR_SC |
319                       MCF5282_CS_CSMR_UC |
320                       MCF5282_CS_CSMR_UD |
321                       MCF5282_CS_CSMR_V;
322    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
323    MCF5282_GPIO_PJPAR |= 0x06;
324}
325
326uint32_t bsp_get_CPU_clock_speed(void)
327{
328    extern char _CPUClockSpeed[];
329    return( (uint32_t)_CPUClockSpeed);
330}
331
332/*
333 * Interrupt controller allocation
334 */
335rtems_status_code
336bsp_allocate_interrupt(int level, int priority)
337{
338    static char used[7];
339    rtems_interrupt_level l;
340    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
341
342    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
343        return RTEMS_INVALID_NUMBER;
344    rtems_interrupt_disable(l);
345    if ((used[level-1] & (1 << priority)) == 0) {
346        used[level-1] |= (1 << priority);
347        ret = RTEMS_SUCCESSFUL;
348    }
349    rtems_interrupt_enable(l);
350    return ret;
351}
352
353/*
354 * Arcturus bootloader system calls
355 */
356#define syscall_return(type, ret)                      \
357do {                                                   \
358   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
359      errno = -(ret);                                  \
360      ret = -1;                                        \
361   }                                                   \
362   return (type)(ret);                                 \
363} while (0)
364#define syscall_1(type,name,d1type,d1)                      \
365type bsp_##name(d1type d1)                                  \
366{                                                           \
367   long ret;                                                \
368   register long __d1 __asm__ ("%d1") = (long)d1;           \
369   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
370                         "trap #2\n\t"                      \
371                         "move.l %%d0,%0"                   \
372                         : "=g" (ret)                       \
373                         : "i" (SysCode_##name), "d" (__d1) \
374                         : "d0" );                          \
375   syscall_return(type,ret);                                \
376}
377#define syscall_2(type,name,d1type,d1,d2type,d2)            \
378type bsp_##name(d1type d1, d2type d2)                       \
379{                                                           \
380   long ret;                                                \
381   register long __d1 __asm__ ("%d1") = (long)d1;           \
382   register long __d2 __asm__ ("%d2") = (long)d2;           \
383   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
384                         "trap #2\n\t"                      \
385                         "move.l %%d0,%0"                   \
386                         : "=g" (ret)                       \
387                         : "i" (SysCode_##name), "d" (__d1),\
388                                                 "d" (__d2) \
389                         : "d0" );                          \
390   syscall_return(type,ret);                                \
391}
392#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
393type bsp_##name(d1type d1, d2type d2, d3type d3)            \
394{                                                           \
395   long ret;                                                \
396   register long __d1 __asm__ ("%d1") = (long)d1;           \
397   register long __d2 __asm__ ("%d2") = (long)d2;           \
398   register long __d3 __asm__ ("%d3") = (long)d3;           \
399   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
400                         "trap #2\n\t"                      \
401                         "move.l %%d0,%0"                   \
402                         : "=g" (ret)                       \
403                         : "i" (SysCode_##name), "d" (__d1),\
404                                                 "d" (__d2),\
405                                                 "d" (__d3) \
406                         : "d0" );                          \
407   syscall_return(type,ret);                                \
408}
409#define SysCode_reset              0 /* reset */
410#define SysCode_program            5 /* program flash memory */
411#define SysCode_gethwaddr         12 /* get hardware address */
412#define SysCode_getbenv           14 /* get bootloader environment variable */
413#define SysCode_setbenv           15 /* set bootloader environment variable */
414#define SysCode_flash_erase_range 19 /* erase a section of flash */
415#define SysCode_flash_write_range 20 /* write a section of flash */
416syscall_1(int, reset, int, flags)
417syscall_1(unsigned const char *, gethwaddr, int, a)
418syscall_1(const char *, getbenv, const char *, a)
419syscall_1(int, setbenv, const char *, a)
420syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
421syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
422syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
423
424/*
425 * 'Extended BSP' routines
426 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
427 */
428
429rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
430int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
431int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
432
433/*
434 * 'VME' interrupt support
435 * Interrupt vectors 192-255 are set aside for use by external logic which
436 * drives IRQ1*.  The actual interrupt source is read from the external
437 * logic at FPGA_IRQ_INFO.  The most-significant bit of the least-significant
438 * byte read from this location is set as long as the external logic has
439 * interrupts to be serviced.  The least-significant six bits indicate the
440 * interrupt source within the external logic and are used to select the
441 * specified interupt handler.
442 */
443#define NVECTOR 256
444#define FPGA_VECTOR (64+1)  /* IRQ1* pin connected to external FPGA */
445#define FPGA_EPPAR  MCF5282_EPORT_EPPAR_EPPA1_LEVEL
446#define FPGA_EPDDR  MCF5282_EPORT_EPDDR_EPDD1
447#define FPGA_EPIER  MCF5282_EPORT_EPIER_EPIE1
448#define FPGA_EPPDR  MCF5282_EPORT_EPPDR_EPPD1
449#define FPGA_IRQ_INFO    *((vuint16 *)(0x31000000 + 0xfffffe))
450
451static struct handlerTab {
452    BSP_VME_ISR_t func;
453    void         *arg;
454} handlerTab[NVECTOR];
455
456BSP_VME_ISR_t
457BSP_getVME_isr(unsigned long vector, void **pusrArg)
458{
459    if (vector >= NVECTOR)
460        return (BSP_VME_ISR_t)NULL;
461    if (pusrArg)
462        *pusrArg = handlerTab[vector].arg;
463    return handlerTab[vector].func;
464}
465
466static rtems_isr
467fpga_trampoline (rtems_vector_number v)
468{
469        /*
470         * Handle FPGA interrupts until all have been consumed
471         */
472        int loopcount = 0;
473        while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
474                v = 192 + (v & 0x3f);
475                if (++loopcount >= 50) {
476                        rtems_interrupt_level level;
477                        rtems_interrupt_disable(level);
478                        printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f);
479                        MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
480                        rtems_interrupt_enable(level);
481                        return;
482                }
483                if (handlerTab[v].func)  {
484                        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
485                }
486                else {
487                        rtems_interrupt_level level;
488                        rtems_vector_number nv;
489                        rtems_interrupt_disable(level);
490                        printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f);
491                        if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0)
492                                        && ((nv & 0x3f) == (v & 0x3f))) {
493                                printk("DISABLING ALL FPGA INTERRUPTS.\n");
494                                MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1;
495                        }
496                        rtems_interrupt_enable(level);
497                        return;
498                }
499        }
500}
501
502static rtems_isr
503trampoline (rtems_vector_number v)
504{
505    if (handlerTab[v].func)
506        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
507}
508
509static void
510enable_irq(unsigned source)
511{
512rtems_interrupt_level level;
513        rtems_interrupt_disable(level);
514        if (source >= 32)
515                MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
516        else
517                MCF5282_INTC0_IMRL &= ~((1 << source) |
518                                MCF5282_INTC_IMRL_MASKALL);
519        rtems_interrupt_enable(level);
520}
521
522static void
523disable_irq(unsigned source)
524{
525rtems_interrupt_level level;
526
527        rtems_interrupt_disable(level);
528        if (source >= 32)
529                MCF5282_INTC0_IMRH |= (1 << (source - 32));
530        else
531                MCF5282_INTC0_IMRL |= (1 << source);
532        rtems_interrupt_enable(level);
533}
534
535void
536BSP_enable_irq_at_pic(rtems_vector_number v)
537{
538int                   source = v - 64;
539
540        if ( source > 0 && source < 64 ) {
541                enable_irq(source);
542        }
543}
544
545void
546BSP_disable_irq_at_pic(rtems_vector_number v)
547{
548int                   source = v - 64;
549
550        if ( source > 0 && source < 64 ) {
551                disable_irq(source);
552        }
553}
554
555int
556BSP_irq_is_enabled_at_pic(rtems_vector_number v)
557{
558int                   source = v - 64;
559
560        if ( source > 0 && source < 64 ) {
561                return ! ((source >= 32) ?
562                        MCF5282_INTC0_IMRH & (1 << (source - 32)) :
563                        MCF5282_INTC0_IMRL & (1 << source));
564        }
565        return -1;
566}
567
568
569static int
570init_intc0_bit(unsigned long vector)
571{
572rtems_interrupt_level level;
573
574    /*
575     * Find an unused level/priority if this is an on-chip (INTC0)
576     * source and this is the first time the source is being used.
577     * Interrupt sources 1 through 7 are fixed level/priority
578     */
579
580    if ((vector >= 65) && (vector <= 127)) {
581        int l, p;
582        int source = vector - 64;
583        static unsigned char installed[8];
584
585        rtems_interrupt_disable(level);
586        if (installed[source/8] & (1 << (source % 8))) {
587            rtems_interrupt_enable(level);
588            return 0;
589        }
590        installed[source/8] |= (1 << (source % 8));
591        rtems_interrupt_enable(level);
592        for (l = 1 ; l < 7 ; l++) {
593            for (p = 0 ; p < 8 ; p++) {
594                if ((source < 8)
595                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
596                    if (source >= 8)
597                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
598                                                       MCF5282_INTC_ICR_IL(l) |
599                                                       MCF5282_INTC_ICR_IP(p);
600                                        enable_irq(source);
601                    return 0;
602                }
603            }
604        }
605        return -1;
606    }
607        return 0;
608}
609
610int
611BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
612{
613    rtems_isr_entry old_handler;
614    rtems_interrupt_level level;
615
616    /*
617     * Register the handler information
618     */
619    if (vector >= NVECTOR)
620        return -1;
621    handlerTab[vector].func = handler;
622    handlerTab[vector].arg = usrArg;
623
624    /*
625     * If this is an external FPGA ('VME') vector set up the real IRQ.
626     */
627    if ((vector >= 192) && (vector <= 255)) {
628        int i;
629        static volatile int setupDone;
630        rtems_interrupt_disable(level);
631        if (setupDone) {
632            rtems_interrupt_enable(level);
633            return 0;
634        }
635        MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
636        MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
637        MCF5282_EPORT_EPIER |=  FPGA_EPIER;
638        MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
639                                MCF5282_INTC_IMRL_MASKALL);
640        setupDone = 1;
641        handlerTab[vector].func = NULL;
642        handlerTab[vector].arg  = NULL;
643                rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler);
644        i = init_intc0_bit(FPGA_VECTOR);
645        rtems_interrupt_enable(level);
646        return i;
647    }
648
649    /*
650     * Make the connection between the interrupt and the local handler
651     */
652    rtems_interrupt_catch(trampoline, vector, &old_handler);
653
654    return init_intc0_bit(vector);
655}
656
657int
658BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
659{
660    if (vector >= NVECTOR)
661        return -1;
662    if ((handlerTab[vector].func != handler)
663     || (handlerTab[vector].arg != usrArg))
664        return -1;
665    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
666    return 0;
667}
668
669int
670BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
671{
672    unsigned long offset;
673
674    switch (am) {
675    default:    return -1;
676    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
677    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
678    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
679    }
680    *plocaladdr = vmeaddr + offset;
681    return 0;
682}
683
684void
685rtems_bsp_reset_cause(char *buf, size_t capacity)
686{
687   int bit, rsr;
688   size_t i;
689   const char *cp;
690   
691    if (buf == NULL)
692        return;
693    if (capacity)
694        buf[0] = '\0';
695    rsr = MCF5282_RESET_RSR;
696    for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) {
697        if (rsr & bit) {
698            switch (bit) {
699            case MCF5282_RESET_RSR_LVD:  cp = "Low voltage";        break;
700            case MCF5282_RESET_RSR_SOFT: cp = "Software reset";     break;
701            case MCF5282_RESET_RSR_WDR:  cp = "Watchdog reset";     break;
702            case MCF5282_RESET_RSR_POR:  cp = "Power-on reset";     break;
703            case MCF5282_RESET_RSR_EXT:  cp = "External reset";     break;
704            case MCF5282_RESET_RSR_LOC:  cp = "Loss of clock";      break;
705            case MCF5282_RESET_RSR_LOL:  cp = "Loss of lock";       break;
706            default:                     cp = "??";                 break;
707            }
708            i += snprintf(buf+i, capacity-i, cp);
709            if (i >= capacity)
710                break;
711            rsr &= ~bit;
712            if (rsr == 0)
713                break;
714            i += snprintf(buf+i, capacity-i, ", ");
715            if (i >= capacity)
716                break;
717        }
718    }
719}
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