source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 239b819

4.104.114.84.95
Last change on this file since 239b819 was 572484f, checked in by Eric Norum <WENorum@…>, on Jan 28, 2005 at 7:35:23 PM

New BSP for Arcturus uCDIMM ColdFire? 5282.

  • Property mode set to 100644
File size: 6.6 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29 
30/*
31 *  The original table from the application and our copy of it with
32 *  some changes.
33 */
34extern rtems_configuration_table Configuration;
35rtems_configuration_table  BSP_Configuration;
36rtems_cpu_table Cpu_table;
37char *rtems_progname;
38
39/*
40 * Location of 'VME' access
41 */
42#define VME_ONE_BASE    0x30000000
43#define VME_TWO_BASE    0x31000000
44
45/*
46 * Cacheable areas
47 */
48#define SDRAM_BASE      0
49#define SDRAM_SIZE      (16*1024*1024)
50#define FLASH_BASE      0x10C10000
51#define FLASH_SIZE      (4*1024*1024)
52
53/*
54 * CPU-space access
55 */
56#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
57#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
58#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
59
60/*
61 * Read/write copy of common cache
62 *   Split I/D cache
63 *   Allow CPUSHL to invalidate a cache line
64 *   Enable buffered writes
65 *   No burst transfers on non-cacheable accesses
66 *   Default cache mode is *disabled* (cache only ACRx areas)
67 */
68static unsigned32 cacr_mode = MCF5XXX_CACR_CENB |
69                              MCF5XXX_CACR_DBWE |
70                              MCF5XXX_CACR_DCM;
71/*
72 * Cannot be frozen
73 */
74void _CPU_cache_freeze_data(void) {}
75void _CPU_cache_unfreeze_data(void) {}
76void _CPU_cache_freeze_instruction(void) {}
77void _CPU_cache_unfreeze_instruction(void) {}
78
79/*
80 * Write-through data cache -- flushes are unnecessary
81 */
82void _CPU_cache_flush_1_data_line(const void *d_addr) {}
83void _CPU_cache_flush_entire_data(void) {}
84
85void _CPU_cache_enable_instruction(void)
86{
87    rtems_interrupt_level level;
88
89    rtems_interrupt_disable(level);
90    cacr_mode &= ~MCF5XXX_CACR_DIDI;
91    m68k_set_cacr(cacr_mode);
92    rtems_interrupt_enable(level);
93}
94
95void _CPU_cache_disable_instruction(void)
96{
97    rtems_interrupt_level level;
98
99    rtems_interrupt_disable(level);
100    cacr_mode |= MCF5XXX_CACR_DIDI;
101    m68k_set_cacr(cacr_mode);
102    rtems_interrupt_enable(level);
103}
104
105void _CPU_cache_invalidate_entire_instruction(void)
106{
107    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
108}
109
110void _CPU_cache_invalidate_1_instruction_line(const void *addr)
111{
112  asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
113}
114
115void _CPU_cache_enable_data(void)
116{
117    rtems_interrupt_level level;
118
119    rtems_interrupt_disable(level);
120    cacr_mode &= ~MCF5XXX_CACR_DISD;
121    m68k_set_cacr(cacr_mode);
122    rtems_interrupt_enable(level);
123}
124
125void _CPU_cache_disable_data(void)
126{
127    rtems_interrupt_level level;
128
129    rtems_interrupt_disable(level);
130    cacr_mode |= MCF5XXX_CACR_DISD;
131    m68k_set_cacr(cacr_mode);
132    rtems_interrupt_enable(level);
133}
134
135void _CPU_cache_invalidate_entire_data(void)
136{
137    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
138}
139
140void _CPU_cache_invalidate_1_data_line(const void *addr)
141{
142  asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
143}
144
145/*
146 *  Use the shared implementations of the following routines
147 */
148void bsp_postdriver_hook(void);
149void bsp_libc_init( void *, unsigned32, int );
150void bsp_pretasking_hook(void);                 /* m68k version */
151
152/*
153 *  bsp_start
154 *
155 *  This routine does the bulk of the system initialisation.
156 */
157void bsp_start( void )
158{
159  extern char _WorkspaceBase[];
160  extern char _RamSize[];
161  extern unsigned long  _M68k_Ramsize;
162
163  _M68k_Ramsize = (unsigned long)_RamSize;              /* RAM size set in linker script */
164
165  /*
166   *  Allocate the memory for the RTEMS Work Space.  This can come from
167   *  a variety of places: hard coded address, malloc'ed from outside
168   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
169   *  typically done by stock BSPs) by subtracting the required amount
170   *  of work space from the last physical address on the CPU board.
171   */
172
173  /*
174   *  Need to "allocate" the memory for the RTEMS Workspace and
175   *  tell the RTEMS configuration where it is.  This memory is
176   *  not malloc'ed.  It is just "pulled from the air".
177   */
178
179  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
180
181  /*
182   *  initialize the CPU table for this BSP
183   */
184  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
185  Cpu_table.postdriver_hook = bsp_postdriver_hook;
186  Cpu_table.do_zero_of_workspace = TRUE;
187  Cpu_table.interrupt_stack_size = 4096;
188
189  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
190
191    /*
192     * Invalidate the cache and disable it
193     */
194    m68k_set_acr0(0);
195    m68k_set_acr1(0);
196    m68k_set_cacr(MCF5XXX_CACR_CINV);
197
198    /*
199     * Cache SDRAM and FLASH
200     */
201    m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE)    |
202                  MCF5XXX_ACR_AM(SDRAM_SIZE-1)  |
203                  MCF5XXX_ACR_EN                |
204                  MCF5XXX_ACR_BWE               |
205                  MCF5XXX_ACR_SM_IGNORE);
206    m68k_set_acr1(MCF5XXX_ACR_AB(FLASH_BASE)    |
207                  MCF5XXX_ACR_AM(FLASH_SIZE-1)  |
208                  MCF5XXX_ACR_EN                |
209                  MCF5XXX_ACR_BWE               |
210                  MCF5XXX_ACR_SM_IGNORE);
211
212    /*
213     * Enable the cache
214     */
215    m68k_set_cacr(cacr_mode);
216
217    /*
218     * Set up CS* space (fake 'VME')
219     *   Two A24/D16 spaces, supervisor data acces
220     */
221    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
222    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | 
223                       MCF5282_CS_CSMR_CI |
224                       MCF5282_CS_CSMR_SC |
225                       MCF5282_CS_CSMR_UC |
226                       MCF5282_CS_CSMR_UD |
227                       MCF5282_CS_CSMR_V;
228    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
229    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
230    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | 
231                       MCF5282_CS_CSMR_CI |
232                       MCF5282_CS_CSMR_SC |
233                       MCF5282_CS_CSMR_UC |
234                       MCF5282_CS_CSMR_UD |
235                       MCF5282_CS_CSMR_V;
236    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
237}
238
239unsigned32 get_CPU_clock_speed(void)
240{
241    extern char _CPUClockSpeed[];
242    return( (unsigned32)_CPUClockSpeed);
243}
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