1 | /* |
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2 | * BSP startup |
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3 | * |
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4 | * This routine starts the application. It includes application, |
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5 | * board, and monitor specific initialization and configuration. |
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6 | * The generic CPU dependent initialization has been performed |
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7 | * before this routine is invoked. |
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8 | * |
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9 | * Author: W. Eric Norum <norume@aps.anl.gov> |
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10 | * |
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11 | * COPYRIGHT (c) 2005. |
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12 | * On-Line Applications Research Corporation (OAR). |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in the file LICENSE in this distribution or at |
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16 | * http://www.rtems.com/license/LICENSE. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include <bsp.h> |
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22 | #include <rtems/error.h> |
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23 | #include <errno.h> |
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24 | #include <stdio.h> |
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25 | #include <mcf5282/mcf5282.h> |
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26 | |
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27 | /* |
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28 | * Location of 'VME' access |
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29 | */ |
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30 | #define VME_ONE_BASE 0x30000000 |
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31 | #define VME_TWO_BASE 0x31000000 |
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32 | |
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33 | /* |
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34 | * Linker Script Defined Variables |
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35 | */ |
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36 | extern char RamSize[]; |
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37 | extern char RamBase[]; |
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38 | extern char _CPUClockSpeed[]; |
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39 | extern char _PLLRefClockSpeed[]; |
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40 | |
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41 | uint32_t BSP_sys_clk_speed = (uint32_t)_CPUClockSpeed; |
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42 | uint32_t BSP_pll_ref_clock = (uint32_t)_PLLRefClockSpeed; |
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43 | /* |
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44 | * CPU-space access |
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45 | * The NOP after writing the CACR is there to address the following issue as |
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46 | * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004: |
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47 | * |
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48 | * 6 Possible Cache Corruption after Setting CACR[CINV] |
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49 | * 6.1 Description |
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50 | * The cache on the MCF5282 was enhanced to function as a unified data and |
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51 | * instruction cache, an instruction cache, or an operand cache. The cache |
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52 | * function and organization is controlled by the cache control register (CACR). |
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53 | * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. |
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54 | * If the cache is configured as a unified cache and the CINV bit is set, the |
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55 | * scope of the cache clear is controlled by two other bits in the CACR, |
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56 | * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data |
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57 | * cache only). These bits allow the entire cache, just the instruction |
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58 | * portion of the cache, or just the data portion of the cache to be cleared. |
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59 | * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set) |
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60 | * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set), |
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61 | * then cache corruption may occur. |
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62 | * |
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63 | * 6.2 Workaround |
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64 | * All loads of the CACR that perform a cache clear operation (CINV = BIT 24) |
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65 | * should be followed immediately by a NOP instruction. This avoids the cache |
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66 | * corruption problem. |
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67 | * DATECODES AFFECTED: All |
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68 | * |
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69 | * |
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70 | * Buffered writes must be disabled as described in "MCF5282 Chip Errata", |
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71 | * MCF5282DE, Rev. 6, 5/2009: |
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72 | * SECF124: Buffered Write May Be Executed Twice |
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73 | * Errata type: Silicon |
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74 | * Affected component: Cache |
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75 | * Description: If buffered writes are enabled using the CACR or ACR |
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76 | * registers, the imprecise write transaction generated |
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77 | * by a buffered write may be executed twice. |
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78 | * Workaround: Do not enable buffered writes in the CACR or ACR registers: |
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79 | * CACR[8] = DBWE (default buffered write enable) must be 0 |
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80 | * ACRn[5] = BUFW (buffered write enable) must be 0 |
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81 | * Fix plan: Currently, there are no plans to fix this. |
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82 | */ |
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83 | #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) |
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84 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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85 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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86 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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87 | |
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88 | /* |
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89 | * Read/write copy of cache registers |
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90 | * Split instruction/data or instruction-only |
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91 | * Allow CPUSHL to invalidate a cache line |
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92 | * Disable buffered writes |
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93 | * No burst transfers on non-cacheable accesses |
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94 | * Default cache mode is *disabled* (cache only ACRx areas) |
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95 | */ |
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96 | uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | |
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97 | #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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98 | MCF5XXX_CACR_DISD | |
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99 | #endif |
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100 | MCF5XXX_CACR_DCM; |
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101 | uint32_t mcf5282_acr0_mode = 0; |
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102 | uint32_t mcf5282_acr1_mode = 0; |
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103 | /* |
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104 | * Cannot be frozen |
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105 | */ |
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106 | void _CPU_cache_freeze_data(void) {} |
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107 | void _CPU_cache_unfreeze_data(void) {} |
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108 | void _CPU_cache_freeze_instruction(void) {} |
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109 | void _CPU_cache_unfreeze_instruction(void) {} |
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110 | |
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111 | /* |
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112 | * Write-through data cache -- flushes are unnecessary |
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113 | */ |
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114 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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115 | void _CPU_cache_flush_entire_data(void) {} |
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116 | |
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117 | void _CPU_cache_enable_instruction(void) |
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118 | { |
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119 | rtems_interrupt_level level; |
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120 | |
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121 | rtems_interrupt_disable(level); |
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122 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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123 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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124 | rtems_interrupt_enable(level); |
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125 | } |
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126 | |
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127 | void _CPU_cache_disable_instruction(void) |
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128 | { |
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129 | rtems_interrupt_level level; |
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130 | |
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131 | rtems_interrupt_disable(level); |
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132 | mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI; |
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133 | m68k_set_cacr(mcf5282_cacr_mode); |
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134 | rtems_interrupt_enable(level); |
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135 | } |
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136 | |
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137 | void _CPU_cache_invalidate_entire_instruction(void) |
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138 | { |
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139 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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140 | } |
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141 | |
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142 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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143 | { |
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144 | /* |
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145 | * Top half of cache is I-space |
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146 | */ |
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147 | addr = (void *)((int)addr | 0x400); |
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148 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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149 | } |
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150 | |
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151 | void _CPU_cache_enable_data(void) |
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152 | { |
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153 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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154 | rtems_interrupt_level level; |
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155 | |
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156 | rtems_interrupt_disable(level); |
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157 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_DISD; |
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158 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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159 | rtems_interrupt_enable(level); |
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160 | #endif |
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161 | } |
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162 | |
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163 | void _CPU_cache_disable_data(void) |
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164 | { |
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165 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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166 | rtems_interrupt_level level; |
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167 | |
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168 | rtems_interrupt_disable(level); |
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169 | mcf5282_cacr_mode |= MCF5XXX_CACR_DISD; |
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170 | m68k_set_cacr(mcf5282_cacr_mode); |
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171 | rtems_interrupt_enable(level); |
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172 | #endif |
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173 | } |
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174 | |
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175 | void _CPU_cache_invalidate_entire_data(void) |
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176 | { |
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177 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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178 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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179 | #endif |
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180 | } |
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181 | |
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182 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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183 | { |
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184 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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185 | /* |
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186 | * Bottom half of cache is D-space |
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187 | */ |
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188 | addr = (void *)((int)addr & ~0x400); |
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189 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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190 | #endif |
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191 | } |
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192 | |
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193 | extern void bsp_fake_syscall(int); |
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194 | |
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195 | /* |
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196 | * The Arcturus boot ROM prints exception information improperly |
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197 | * so use this default exception handler instead. This one also |
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198 | * prints a call backtrace |
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199 | */ |
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200 | static void handler(int pc) |
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201 | { |
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202 | int level; |
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203 | static volatile int reent; |
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204 | |
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205 | rtems_interrupt_disable(level); |
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206 | if (reent++) bsp_sysReset(0); |
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207 | { |
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208 | int *p = &pc; |
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209 | int info = p[-1]; |
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210 | int pc = p[0]; |
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211 | int format = (info >> 28) & 0xF; |
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212 | int faultStatus = ((info >> 24) & 0xC) | ((info >> 16) & 0x3); |
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213 | int vector = (info >> 18) & 0xFF; |
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214 | int statusRegister = info & 0xFFFF; |
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215 | int *fp; |
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216 | |
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217 | printk("\n\nPC:%x SR:%x VEC:%x FORMAT:%x STATUS:%x\n", pc, |
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218 | statusRegister, |
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219 | vector, |
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220 | format, |
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221 | faultStatus); |
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222 | fp = &p[-2]; |
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223 | for(;;) { |
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224 | int *nfp = (int *)*fp; |
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225 | if ((nfp <= fp) |
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226 | || ((char *)nfp >= RamSize) |
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227 | || ((char *)(nfp[1]) >= RamSize)) |
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228 | break; |
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229 | printk("FP:%x -> %x PC:%x\n", fp, nfp, nfp[1]); |
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230 | fp = nfp; |
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231 | } |
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232 | } |
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233 | rtems_task_suspend(0); |
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234 | rtems_panic("done"); |
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235 | } |
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236 | |
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237 | /* |
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238 | * bsp_start |
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239 | * |
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240 | * This routine does the bulk of the system initialisation. |
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241 | */ |
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242 | void bsp_start( void ) |
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243 | { |
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244 | int i; |
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245 | const char *clk_speed_str; |
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246 | uint32_t clk_speed, mfd, rfd; |
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247 | uint8_t byte; |
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248 | |
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249 | /* |
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250 | * Make sure UART TX is running - necessary for |
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251 | * early printk to work. The firmware monitor |
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252 | * usually enables this anyways but qemu doesn't! |
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253 | */ |
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254 | MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED; |
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255 | |
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256 | /* |
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257 | * Set up default exception handler |
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258 | */ |
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259 | for (i = 2 ; i < 256 ; i++) |
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260 | if (i != (32+2)) /* Catch all but bootrom system calls */ |
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261 | *((void (**)(int))(i * 4)) = handler; |
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262 | |
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263 | /* |
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264 | * Invalidate the cache and disable it |
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265 | */ |
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266 | m68k_set_acr0(mcf5282_acr0_mode); |
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267 | m68k_set_acr1(mcf5282_acr1_mode); |
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268 | m68k_set_cacr_nop(MCF5XXX_CACR_CINV); |
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269 | |
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270 | /* |
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271 | * Cache SDRAM |
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272 | * Enable buffered writes |
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273 | * As Device Errata SECF124 notes this may cause double writes, |
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274 | * but that's not really a big problem and benchmarking tests have |
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275 | * shown that buffered writes do gain some performance. |
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276 | */ |
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277 | mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)RamBase) | |
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278 | MCF5XXX_ACR_AM((uint32_t)RamSize-1) | |
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279 | MCF5XXX_ACR_EN | |
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280 | MCF5XXX_ACR_SM_IGNORE | |
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281 | MCF5XXX_ACR_BWE; |
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282 | m68k_set_acr0(mcf5282_acr0_mode); |
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283 | |
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284 | /* |
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285 | * Qemu has no trap handler; install our fake syscall |
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286 | * implementation if there is no existing handler. |
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287 | */ |
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288 | if ( 0 == *((void (**)(int))((32+2) * 4)) ) |
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289 | *((void (**)(int))((32+2) * 4)) = bsp_fake_syscall; |
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290 | |
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291 | /* |
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292 | * Enable the cache |
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293 | */ |
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294 | m68k_set_cacr(mcf5282_cacr_mode); |
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295 | |
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296 | /* |
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297 | * Set up CS* space (fake 'VME') |
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298 | * Two A24/D16 spaces, supervisor data acces |
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299 | */ |
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300 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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301 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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302 | MCF5282_CS_CSMR_CI | |
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303 | MCF5282_CS_CSMR_SC | |
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304 | MCF5282_CS_CSMR_UC | |
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305 | MCF5282_CS_CSMR_UD | |
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306 | MCF5282_CS_CSMR_V; |
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307 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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308 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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309 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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310 | MCF5282_CS_CSMR_CI | |
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311 | MCF5282_CS_CSMR_SC | |
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312 | MCF5282_CS_CSMR_UC | |
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313 | MCF5282_CS_CSMR_UD | |
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314 | MCF5282_CS_CSMR_V; |
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315 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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316 | MCF5282_GPIO_PJPAR |= 0x06; |
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317 | |
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318 | /* |
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319 | * Hopefully, the UART clock is still correctly set up |
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320 | * so they can see the printk() output... |
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321 | */ |
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322 | clk_speed = 0; |
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323 | printk("Trying to figure out the system clock\n"); |
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324 | printk("Checking ENV variable SYS_CLOCK_SPEED:\n"); |
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325 | if ( (clk_speed_str = bsp_getbenv("SYS_CLOCK_SPEED")) ) { |
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326 | printk("Found: %s\n", clk_speed_str); |
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327 | for ( clk_speed = 0, i=0; |
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328 | clk_speed_str[i] >= '0' && clk_speed_str[i] <= '9'; |
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329 | i++ ) { |
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330 | clk_speed = 10*clk_speed + clk_speed_str[i] - '0'; |
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331 | } |
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332 | if ( 0 != clk_speed_str[i] ) { |
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333 | printk("Not a decimal number; I'm not using this setting\n"); |
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334 | clk_speed = 0; |
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335 | } |
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336 | } else { |
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337 | printk("Not set.\n"); |
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338 | } |
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339 | |
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340 | if ( 0 == clk_speed ) |
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341 | clk_speed = BSP_sys_clk_speed; |
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342 | |
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343 | if ( 0 == clk_speed ) { |
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344 | printk("Using some heuristics to determine clock speed...\n"); |
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345 | byte = MCF5282_CLOCK_SYNSR; |
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346 | if ( 0 == byte ) { |
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347 | printk("SYNSR == 0; assuming QEMU at 66MHz\n"); |
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348 | BSP_pll_ref_clock = 8250000; |
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349 | mfd = ( 0 << 8 ) | ( 2 << 12 ); |
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350 | } else { |
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351 | if ( 0xf8 != byte ) { |
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352 | printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte); |
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353 | bsp_sysReset(0); |
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354 | } |
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355 | mfd = MCF5282_CLOCK_SYNCR; |
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356 | } |
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357 | printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock); |
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358 | rfd = (mfd >> 8) & 7; |
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359 | mfd = (mfd >> 12) & 7; |
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360 | /* Check against 'known' cases */ |
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361 | if ( 0 != rfd || (2 != mfd && 3 != mfd) ) { |
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362 | printk("WARNING: Pll divisor/multiplier has unknown value; \n"); |
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363 | printk(" either your board is not 64MHz or 80Mhz or\n"); |
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364 | printk(" it uses a PLL reference other than 8MHz.\n"); |
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365 | printk(" I'll proceed anyways but you might have to\n"); |
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366 | printk(" reset the board and set uCbootloader ENV\n"); |
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367 | printk(" variable \"SYS_CLOCK_SPEED\".\n"); |
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368 | } |
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369 | mfd = 2 * (mfd + 2); |
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370 | /* sysclk = pll_ref * 2 * (MFD + 2) / 2^(rfd) */ |
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371 | printk("PLL multiplier: %u, output divisor: %u\n", mfd, rfd); |
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372 | clk_speed = (BSP_pll_ref_clock * mfd) >> rfd; |
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373 | } |
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374 | |
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375 | if ( 0 == clk_speed ) { |
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376 | printk("FATAL ERROR: Unable to determine system clock speed\n"); |
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377 | bsp_sysReset(0); |
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378 | } else { |
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379 | BSP_sys_clk_speed = clk_speed; |
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380 | printk("System clock speed: %uHz\n", bsp_get_CPU_clock_speed()); |
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381 | } |
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382 | } |
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383 | |
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384 | uint32_t bsp_get_CPU_clock_speed(void) |
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385 | { |
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386 | return( BSP_sys_clk_speed ); |
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387 | } |
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388 | |
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389 | /* |
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390 | * Interrupt controller allocation |
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391 | */ |
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392 | rtems_status_code |
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393 | bsp_allocate_interrupt(int level, int priority) |
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394 | { |
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395 | static char used[7]; |
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396 | rtems_interrupt_level l; |
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397 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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398 | |
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399 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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400 | return RTEMS_INVALID_NUMBER; |
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401 | rtems_interrupt_disable(l); |
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402 | if ((used[level-1] & (1 << priority)) == 0) { |
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403 | used[level-1] |= (1 << priority); |
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404 | ret = RTEMS_SUCCESSFUL; |
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405 | } |
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406 | rtems_interrupt_enable(l); |
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407 | return ret; |
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408 | } |
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409 | |
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410 | /* |
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411 | * Arcturus bootloader system calls |
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412 | */ |
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413 | #define syscall_return(type, ret) \ |
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414 | do { \ |
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415 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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416 | errno = -(ret); \ |
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417 | ret = -1; \ |
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418 | } \ |
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419 | return (type)(ret); \ |
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420 | } while (0) |
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421 | |
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422 | #define syscall_1(type,name,d1type,d1) \ |
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423 | type bsp_##name(d1type d1) \ |
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424 | { \ |
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425 | long ret; \ |
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426 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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427 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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428 | "trap #2\n\t" \ |
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429 | "move.l %%d0,%0" \ |
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430 | : "=g" (ret) \ |
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431 | : "i" (SysCode_##name), "d" (__d1) \ |
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432 | : "d0" ); \ |
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433 | syscall_return(type,ret); \ |
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434 | } |
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435 | |
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436 | #define syscall_2(type,name,d1type,d1,d2type,d2) \ |
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437 | type bsp_##name(d1type d1, d2type d2) \ |
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438 | { \ |
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439 | long ret; \ |
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440 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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441 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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442 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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443 | "trap #2\n\t" \ |
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444 | "move.l %%d0,%0" \ |
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445 | : "=g" (ret) \ |
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446 | : "i" (SysCode_##name), "d" (__d1),\ |
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447 | "d" (__d2) \ |
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448 | : "d0" ); \ |
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449 | syscall_return(type,ret); \ |
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450 | } |
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451 | |
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452 | #define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \ |
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453 | type bsp_##name(d1type d1, d2type d2, d3type d3) \ |
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454 | { \ |
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455 | long ret; \ |
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456 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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457 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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458 | register long __d3 __asm__ ("%d3") = (long)d3; \ |
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459 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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460 | "trap #2\n\t" \ |
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461 | "move.l %%d0,%0" \ |
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462 | : "=g" (ret) \ |
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463 | : "i" (SysCode_##name), "d" (__d1),\ |
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464 | "d" (__d2),\ |
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465 | "d" (__d3) \ |
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466 | : "d0" ); \ |
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467 | syscall_return(type,ret); \ |
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468 | } |
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469 | |
---|
470 | #define SysCode_sysReset 0 /* system reset */ |
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471 | #define SysCode_program 5 /* program flash memory */ |
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472 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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473 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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474 | #define SysCode_setbenv 15 /* set bootloader environment variable */ |
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475 | #define SysCode_flash_erase_range 19 /* erase a section of flash */ |
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476 | #define SysCode_flash_write_range 20 /* write a section of flash */ |
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477 | syscall_1(int, sysReset, int, flags) |
---|
478 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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479 | syscall_1(const char *, getbenv, const char *, a) |
---|
480 | syscall_1(int, setbenv, const char *, a) |
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481 | syscall_2(int, program, bsp_mnode_t *, chain, int, flags) |
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482 | syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end); |
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483 | syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset); |
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484 | |
---|
485 | /* Provide a dummy-implementation of these syscalls |
---|
486 | * for qemu (which lacks the firmware). |
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487 | */ |
---|
488 | |
---|
489 | #define __STR(x) #x |
---|
490 | #define __STRSTR(x) __STR(x) |
---|
491 | #define ERRVAL __STRSTR(EACCES) |
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492 | |
---|
493 | /* reset-control register */ |
---|
494 | #define RCR "__IPSBAR + 0x110000" |
---|
495 | |
---|
496 | asm( |
---|
497 | "bsp_fake_syscall: \n" |
---|
498 | " cmpl #0, %d0 \n" /* sysreset */ |
---|
499 | " bne 1f \n" |
---|
500 | " moveb #0x80, %d0 \n" |
---|
501 | " moveb %d0, "RCR" \n" /* reset-controller */ |
---|
502 | /* should never get here - but we'd return -EACCESS if we do */ |
---|
503 | "1: \n" |
---|
504 | " cmpl #12, %d0 \n" /* gethwaddr */ |
---|
505 | " beq 2f \n" |
---|
506 | " cmpl #14, %d0 \n" /* getbenv */ |
---|
507 | " beq 2f \n" |
---|
508 | " movel #-"ERRVAL", %d0 \n" /* return -EACCESS */ |
---|
509 | " rte \n" |
---|
510 | "2: \n" |
---|
511 | " movel #0, %d0 \n" /* return NULL */ |
---|
512 | " rte \n" |
---|
513 | ); |
---|
514 | |
---|
515 | |
---|
516 | /* |
---|
517 | * 'Extended BSP' routines |
---|
518 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
---|
519 | */ |
---|
520 | |
---|
521 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
---|
522 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
---|
523 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
---|
524 | |
---|
525 | /* |
---|
526 | * 'VME' interrupt support |
---|
527 | * Interrupt vectors 192-255 are set aside for use by external logic which |
---|
528 | * drives IRQ1*. The actual interrupt source is read from the external |
---|
529 | * logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant |
---|
530 | * byte read from this location is set as long as the external logic has |
---|
531 | * interrupts to be serviced. The least-significant six bits indicate the |
---|
532 | * interrupt source within the external logic and are used to select the |
---|
533 | * specified interupt handler. |
---|
534 | */ |
---|
535 | #define NVECTOR 256 |
---|
536 | #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ |
---|
537 | #define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe)) |
---|
538 | |
---|
539 | static struct handlerTab { |
---|
540 | BSP_VME_ISR_t func; |
---|
541 | void *arg; |
---|
542 | } handlerTab[NVECTOR]; |
---|
543 | |
---|
544 | BSP_VME_ISR_t |
---|
545 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
---|
546 | { |
---|
547 | if (vector >= NVECTOR) |
---|
548 | return (BSP_VME_ISR_t)NULL; |
---|
549 | if (pusrArg) |
---|
550 | *pusrArg = handlerTab[vector].arg; |
---|
551 | return handlerTab[vector].func; |
---|
552 | } |
---|
553 | |
---|
554 | static rtems_isr |
---|
555 | fpga_trampoline (rtems_vector_number v) |
---|
556 | { |
---|
557 | /* |
---|
558 | * Handle FPGA interrupts until all have been consumed |
---|
559 | */ |
---|
560 | int loopcount = 0; |
---|
561 | while (((v = FPGA_IRQ_INFO) & 0x80) != 0) { |
---|
562 | v = 192 + (v & 0x3f); |
---|
563 | if (++loopcount >= 50) { |
---|
564 | rtems_interrupt_level level; |
---|
565 | rtems_interrupt_disable(level); |
---|
566 | printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f); |
---|
567 | MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1; |
---|
568 | rtems_interrupt_enable(level); |
---|
569 | return; |
---|
570 | } |
---|
571 | if (handlerTab[v].func) { |
---|
572 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
---|
573 | } |
---|
574 | else { |
---|
575 | rtems_interrupt_level level; |
---|
576 | rtems_vector_number nv; |
---|
577 | rtems_interrupt_disable(level); |
---|
578 | printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f); |
---|
579 | if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0) |
---|
580 | && ((nv & 0x3f) == (v & 0x3f))) { |
---|
581 | printk("DISABLING ALL FPGA INTERRUPTS.\n"); |
---|
582 | MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1; |
---|
583 | } |
---|
584 | rtems_interrupt_enable(level); |
---|
585 | return; |
---|
586 | } |
---|
587 | } |
---|
588 | } |
---|
589 | |
---|
590 | static rtems_isr |
---|
591 | trampoline (rtems_vector_number v) |
---|
592 | { |
---|
593 | if (handlerTab[v].func) |
---|
594 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
---|
595 | } |
---|
596 | |
---|
597 | static void |
---|
598 | enable_irq(unsigned source) |
---|
599 | { |
---|
600 | rtems_interrupt_level level; |
---|
601 | rtems_interrupt_disable(level); |
---|
602 | if (source >= 32) |
---|
603 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
---|
604 | else |
---|
605 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
---|
606 | MCF5282_INTC_IMRL_MASKALL); |
---|
607 | rtems_interrupt_enable(level); |
---|
608 | } |
---|
609 | |
---|
610 | static void |
---|
611 | disable_irq(unsigned source) |
---|
612 | { |
---|
613 | rtems_interrupt_level level; |
---|
614 | |
---|
615 | rtems_interrupt_disable(level); |
---|
616 | if (source >= 32) |
---|
617 | MCF5282_INTC0_IMRH |= (1 << (source - 32)); |
---|
618 | else |
---|
619 | MCF5282_INTC0_IMRL |= (1 << source); |
---|
620 | rtems_interrupt_enable(level); |
---|
621 | } |
---|
622 | |
---|
623 | void |
---|
624 | BSP_enable_irq_at_pic(rtems_vector_number v) |
---|
625 | { |
---|
626 | int source = v - 64; |
---|
627 | |
---|
628 | if ( source > 0 && source < 64 ) { |
---|
629 | enable_irq(source); |
---|
630 | } |
---|
631 | } |
---|
632 | |
---|
633 | void |
---|
634 | BSP_disable_irq_at_pic(rtems_vector_number v) |
---|
635 | { |
---|
636 | int source = v - 64; |
---|
637 | |
---|
638 | if ( source > 0 && source < 64 ) { |
---|
639 | disable_irq(source); |
---|
640 | } |
---|
641 | } |
---|
642 | |
---|
643 | int |
---|
644 | BSP_irq_is_enabled_at_pic(rtems_vector_number v) |
---|
645 | { |
---|
646 | int source = v - 64; |
---|
647 | |
---|
648 | if ( source > 0 && source < 64 ) { |
---|
649 | return ! ((source >= 32) ? |
---|
650 | MCF5282_INTC0_IMRH & (1 << (source - 32)) : |
---|
651 | MCF5282_INTC0_IMRL & (1 << source)); |
---|
652 | } |
---|
653 | return -1; |
---|
654 | } |
---|
655 | |
---|
656 | |
---|
657 | static int |
---|
658 | init_intc0_bit(unsigned long vector) |
---|
659 | { |
---|
660 | rtems_interrupt_level level; |
---|
661 | |
---|
662 | /* |
---|
663 | * Find an unused level/priority if this is an on-chip (INTC0) |
---|
664 | * source and this is the first time the source is being used. |
---|
665 | * Interrupt sources 1 through 7 are fixed level/priority |
---|
666 | */ |
---|
667 | |
---|
668 | if ((vector >= 65) && (vector <= 127)) { |
---|
669 | int l, p; |
---|
670 | int source = vector - 64; |
---|
671 | static unsigned char installed[8]; |
---|
672 | |
---|
673 | rtems_interrupt_disable(level); |
---|
674 | if (installed[source/8] & (1 << (source % 8))) { |
---|
675 | rtems_interrupt_enable(level); |
---|
676 | return 0; |
---|
677 | } |
---|
678 | installed[source/8] |= (1 << (source % 8)); |
---|
679 | rtems_interrupt_enable(level); |
---|
680 | for (l = 1 ; l < 7 ; l++) { |
---|
681 | for (p = 0 ; p < 8 ; p++) { |
---|
682 | if ((source < 8) |
---|
683 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
---|
684 | if (source < 8) |
---|
685 | MCF5282_EPORT_EPIER |= 1 << source; |
---|
686 | else |
---|
687 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
---|
688 | MCF5282_INTC_ICR_IL(l) | |
---|
689 | MCF5282_INTC_ICR_IP(p); |
---|
690 | enable_irq(source); |
---|
691 | return 0; |
---|
692 | } |
---|
693 | } |
---|
694 | } |
---|
695 | return -1; |
---|
696 | } |
---|
697 | return 0; |
---|
698 | } |
---|
699 | |
---|
700 | int |
---|
701 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
---|
702 | { |
---|
703 | rtems_isr_entry old_handler; |
---|
704 | rtems_interrupt_level level; |
---|
705 | |
---|
706 | /* |
---|
707 | * Register the handler information |
---|
708 | */ |
---|
709 | if (vector >= NVECTOR) |
---|
710 | return -1; |
---|
711 | handlerTab[vector].func = handler; |
---|
712 | handlerTab[vector].arg = usrArg; |
---|
713 | |
---|
714 | /* |
---|
715 | * If this is an external FPGA ('VME') vector set up the real IRQ. |
---|
716 | */ |
---|
717 | if ((vector >= 192) && (vector <= 255)) { |
---|
718 | int i; |
---|
719 | static volatile int setupDone; |
---|
720 | rtems_interrupt_disable(level); |
---|
721 | if (setupDone) { |
---|
722 | rtems_interrupt_enable(level); |
---|
723 | return 0; |
---|
724 | } |
---|
725 | setupDone = 1; |
---|
726 | rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler); |
---|
727 | i = init_intc0_bit(FPGA_VECTOR); |
---|
728 | rtems_interrupt_enable(level); |
---|
729 | return i; |
---|
730 | } |
---|
731 | |
---|
732 | /* |
---|
733 | * Make the connection between the interrupt and the local handler |
---|
734 | */ |
---|
735 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
---|
736 | |
---|
737 | return init_intc0_bit(vector); |
---|
738 | } |
---|
739 | |
---|
740 | int |
---|
741 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
---|
742 | { |
---|
743 | if (vector >= NVECTOR) |
---|
744 | return -1; |
---|
745 | if ((handlerTab[vector].func != handler) |
---|
746 | || (handlerTab[vector].arg != usrArg)) |
---|
747 | return -1; |
---|
748 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
---|
749 | return 0; |
---|
750 | } |
---|
751 | |
---|
752 | int |
---|
753 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
---|
754 | { |
---|
755 | unsigned long offset; |
---|
756 | |
---|
757 | switch (am) { |
---|
758 | default: return -1; |
---|
759 | case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */ |
---|
760 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
---|
761 | case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */ |
---|
762 | } |
---|
763 | *plocaladdr = vmeaddr + offset; |
---|
764 | return 0; |
---|
765 | } |
---|
766 | |
---|
767 | void |
---|
768 | rtems_bsp_reset_cause(char *buf, size_t capacity) |
---|
769 | { |
---|
770 | int bit, rsr; |
---|
771 | size_t i; |
---|
772 | const char *cp; |
---|
773 | |
---|
774 | if (buf == NULL) |
---|
775 | return; |
---|
776 | if (capacity) |
---|
777 | buf[0] = '\0'; |
---|
778 | rsr = MCF5282_RESET_RSR; |
---|
779 | for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) { |
---|
780 | if (rsr & bit) { |
---|
781 | switch (bit) { |
---|
782 | case MCF5282_RESET_RSR_LVD: cp = "Low voltage"; break; |
---|
783 | case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break; |
---|
784 | case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break; |
---|
785 | case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break; |
---|
786 | case MCF5282_RESET_RSR_EXT: cp = "External reset"; break; |
---|
787 | case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break; |
---|
788 | case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break; |
---|
789 | default: cp = "??"; break; |
---|
790 | } |
---|
791 | i += snprintf(buf+i, capacity-i, cp); |
---|
792 | if (i >= capacity) |
---|
793 | break; |
---|
794 | rsr &= ~bit; |
---|
795 | if (rsr == 0) |
---|
796 | break; |
---|
797 | i += snprintf(buf+i, capacity-i, ", "); |
---|
798 | if (i >= capacity) |
---|
799 | break; |
---|
800 | } |
---|
801 | } |
---|
802 | } |
---|