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source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 1eb65053

4.104.114.84.95

Last change on this file since 1eb65053 was ac9bbe7, checked in by Eric Norum <WENorum@…>, on 04/21/05 at 00:25:53
Try insructioin-only cache.
Property mode set to `100644`
File size: 18.2 KB

Line
1	/*
2	* BSP startup
3	*
4	* This routine starts the application. It includes application,
5	* board, and monitor specific initialization and configuration.
6	* The generic CPU dependent initialization has been performed
7	* before this routine is invoked.
8	*
9	* Author:
10	* David Fiddes, D.J@fiddes.surfaid.org
11	* http://www.calm.hw.ac.uk/davidf/coldfire/
12	*
13	* COPYRIGHT (c) 1989-1998.
14	* On-Line Applications Research Corporation (OAR).
15	* Copyright assigned to U.S. Government, 1994.
16	*
17	* The license and distribution terms for this file may be
18	* found in the file LICENSE in this distribution or at
19	*
20	* http://www.OARcorp.com/rtems/license.html.
21	*
22	* $Id$
23	*/
24
25	#include <bsp.h>
26	#include <rtems/libio.h>
27	#include <rtems/libcsupport.h>
28	#include <string.h>
29	#include <errno.h>
30
31	/*
32	* The original table from the application and our copy of it with
33	* some changes.
34	*/
35	extern rtems_configuration_table Configuration;
36	rtems_configuration_table BSP_Configuration;
37	rtems_cpu_table Cpu_table;
38	char *rtems_progname;
39
40	/*
41	* Location of 'VME' access
42	*/
43	#define VME_ONE_BASE 0x30000000
44	#define VME_TWO_BASE 0x31000000
45
46	/*
47	* CPU-space access
48	* The NOP after writing the CACR is there to address the following issue as
49	* described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
50	*
51	* 6 Possible Cache Corruption after Setting CACR[CINV]
52	* 6.1 Description
53	* The cache on the MCF5282 was enhanced to function as a unified data and
54	* instruction cache, an instruction cache, or an operand cache. The cache
55	* function and organization is controlled by the cache control register (CACR).
56	* The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
57	* If the cache is configured as a unified cache and the CINV bit is set, the
58	* scope of the cache clear is controlled by two other bits in the CACR,
59	* INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
60	* cache only). These bits allow the entire cache, just the instruction
61	* portion of the cache, or just the data portion of the cache to be cleared.
62	* If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
63	* and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
64	* then cache corruption may occur.
65	*
66	* 6.2 Workaround
67	* All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
68	* should be followed immediately by a NOP instruction. This avoids the cache
69	* corruption problem.
70	* DATECODES AFFECTED: All
71	*/
72	#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
73	#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
74	#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
75	#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
76
77	/*
78	* Read/write copy of cache registers
79	* Split instruction/data or instruction-only
80	* Allow CPUSHL to invalidate a cache line
81	* Enable buffered writes
82	* No burst transfers on non-cacheable accesses
83	* Default cache mode is disabled (cache only ACRx areas)
84	*/
85	uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB \|
86	#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
87	MCF5XXX_CACR_DISD \|
88	#endif
89	MCF5XXX_CACR_DBWE \|
90	MCF5XXX_CACR_DCM;
91	uint32_t mcf5282_acr0_mode = 0;
92	uint32_t mcf5282_acr1_mode = 0;
93	/*
94	* Cannot be frozen
95	*/
96	void _CPU_cache_freeze_data(void) {}
97	void _CPU_cache_unfreeze_data(void) {}
98	void _CPU_cache_freeze_instruction(void) {}
99	void _CPU_cache_unfreeze_instruction(void) {}
100
101	/*
102	* Write-through data cache -- flushes are unnecessary
103	*/
104	void _CPU_cache_flush_1_data_line(const void *d_addr) {}
105	void _CPU_cache_flush_entire_data(void) {}
106
107	void _CPU_cache_enable_instruction(void)
108	{
109	rtems_interrupt_level level;
110
111	rtems_interrupt_disable(level);
112	mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
113	m68k_set_cacr(mcf5282_cacr_mode);
114	rtems_interrupt_enable(level);
115	}
116
117	void _CPU_cache_disable_instruction(void)
118	{
119	rtems_interrupt_level level;
120
121	rtems_interrupt_disable(level);
122	mcf5282_cacr_mode \|= MCF5XXX_CACR_DIDI;
123	m68k_set_cacr(mcf5282_cacr_mode);
124	rtems_interrupt_enable(level);
125	}
126
127	void _CPU_cache_invalidate_entire_instruction(void)
128	{
129	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVI);
130	}
131
132	void _CPU_cache_invalidate_1_instruction_line(const void *addr)
133	{
134	/*
135	* Top half of cache is I-space
136	*/
137	addr = (void *)((int)addr \| 0x400);
138	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
139	}
140
141	void _CPU_cache_enable_data(void)
142	{
143	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
144	rtems_interrupt_level level;
145
146	rtems_interrupt_disable(level);
147	mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
148	m68k_set_cacr(mcf5282_cacr_mode);
149	rtems_interrupt_enable(level);
150	#endif
151	}
152
153	void _CPU_cache_disable_data(void)
154	{
155	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
156	rtems_interrupt_level level;
157
158	rtems_interrupt_disable(level);
159	rtems_interrupt_disable(level);
160	mcf5282_cacr_mode \|= MCF5XXX_CACR_CENB;
161	m68k_set_cacr(mcf5282_cacr_mode);
162	rtems_interrupt_enable(level);
163	#endif
164	}
165
166	void _CPU_cache_invalidate_entire_data(void)
167	{
168	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
169	m68k_set_cacr_nop(mcf5282_cacr_mode \| MCF5XXX_CACR_CINV \| MCF5XXX_CACR_INVD);
170	#endif
171	}
172
173	void _CPU_cache_invalidate_1_data_line(const void *addr)
174	{
175	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
176	/*
177	* Bottom half of cache is D-space
178	*/
179	addr = (void *)((int)addr & ~0x400);
180	asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
181	#endif
182	}
183
184	/*
185	* Use the shared implementations of the following routines
186	*/
187	void bsp_postdriver_hook(void);
188	void bsp_libc_init( void *, uint32_t, int );
189	void bsp_pretasking_hook(void); /* m68k version */
190
191	/*
192	* bsp_start
193	*
194	* This routine does the bulk of the system initialisation.
195	*/
196	void bsp_start( void )
197	{
198	extern char _WorkspaceBase[];
199	extern char _RamBase[], _RamSize[];
200	extern unsigned long _M68k_Ramsize;
201
202	_M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */
203
204	/*
205	* Allocate the memory for the RTEMS Work Space. This can come from
206	* a variety of places: hard coded address, malloc'ed from outside
207	* RTEMS world (e.g. simulator or primitive memory manager), or (as
208	* typically done by stock BSPs) by subtracting the required amount
209	* of work space from the last physical address on the CPU board.
210	*/
211
212	/*
213	* Need to "allocate" the memory for the RTEMS Workspace and
214	* tell the RTEMS configuration where it is. This memory is
215	* not malloc'ed. It is just "pulled from the air".
216	*/
217
218	BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
219
220	/*
221	* initialize the CPU table for this BSP
222	*/
223	Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
224	Cpu_table.postdriver_hook = bsp_postdriver_hook;
225	Cpu_table.do_zero_of_workspace = TRUE;
226	Cpu_table.interrupt_stack_size = 4096;
227
228	Cpu_table.interrupt_vector_table = (m68k_isr )0; / vectors at start of RAM */
229
230	/*
231	* Invalidate the cache and disable it
232	*/
233	m68k_set_acr0(mcf5282_acr0_mode);
234	m68k_set_acr1(mcf5282_acr1_mode);
235	m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
236
237	/*
238	* Cache SDRAM
239	*/
240	mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) \|
241	MCF5XXX_ACR_AM((uint32_t)_RamSize-1) \|
242	MCF5XXX_ACR_EN \|
243	MCF5XXX_ACR_BWE \|
244	MCF5XXX_ACR_SM_IGNORE;
245	m68k_set_acr0(mcf5282_acr0_mode);
246
247	/*
248	* Enable the cache
249	*/
250	m68k_set_cacr(mcf5282_cacr_mode);
251
252	/*
253	* Set up CS* space (fake 'VME')
254	* Two A24/D16 spaces, supervisor data acces
255	*/
256	MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
257	MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M \|
258	MCF5282_CS_CSMR_CI \|
259	MCF5282_CS_CSMR_SC \|
260	MCF5282_CS_CSMR_UC \|
261	MCF5282_CS_CSMR_UD \|
262	MCF5282_CS_CSMR_V;
263	MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
264	MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
265	MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M \|
266	MCF5282_CS_CSMR_CI \|
267	MCF5282_CS_CSMR_SC \|
268	MCF5282_CS_CSMR_UC \|
269	MCF5282_CS_CSMR_UD \|
270	MCF5282_CS_CSMR_V;
271	MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
272	}
273
274	uint32_t bsp_get_CPU_clock_speed(void)
275	{
276	extern char _CPUClockSpeed[];
277	return( (uint32_t)_CPUClockSpeed);
278	}
279
280	/*
281	* Interrupt controller allocation
282	*/
283	rtems_status_code
284	bsp_allocate_interrupt(int level, int priority)
285	{
286	static char used[7];
287	rtems_interrupt_level l;
288	rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
289
290	if ((level < 1) \|\| (level > 7) \|\| (priority < 0) \|\| (priority > 7))
291	return RTEMS_INVALID_NUMBER;
292	rtems_interrupt_disable(l);
293	if ((used[level-1] & (1 << priority)) == 0) {
294	used[level-1] \|= (1 << priority);
295	ret = RTEMS_SUCCESSFUL;
296	}
297	rtems_interrupt_enable(l);
298	return ret;
299	}
300
301	/*
302	* Arcturus bootloader system calls
303	*/
304	#define syscall_return(type, ret) \
305	do { \
306	if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
307	errno = -(ret); \
308	ret = -1; \
309	} \
310	return (type)(ret); \
311	} while (0)
312	#define syscall_1(type,name,d1type,d1) \
313	type bsp_##name(d1type d1) \
314	{ \
315	long ret; \
316	register long __d1 __asm__ ("%d1") = (long)d1; \
317	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
318	"trap #2\n\t" \
319	"move.l %%d0,%0" \
320	: "=g" (ret) \
321	: "i" (SysCode_##name), "d" (__d1) \
322	: "d0" ); \
323	syscall_return(type,ret); \
324	}
325	#define syscall_2(type,name,d1type,d1,d2type,d2) \
326	type bsp_##name(d1type d1, d2type d2) \
327	{ \
328	long ret; \
329	register long __d1 __asm__ ("%d1") = (long)d1; \
330	register long __d2 __asm__ ("%d2") = (long)d2; \
331	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
332	"trap #2\n\t" \
333	"move.l %%d0,%0" \
334	: "=g" (ret) \
335	: "i" (SysCode_##name), "d" (__d1),\
336	"d" (__d2) \
337	: "d0" ); \
338	syscall_return(type,ret); \
339	}
340	#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \
341	type bsp_##name(d1type d1, d2type d2, d3type d3) \
342	{ \
343	long ret; \
344	register long __d1 __asm__ ("%d1") = (long)d1; \
345	register long __d2 __asm__ ("%d2") = (long)d2; \
346	register long __d3 __asm__ ("%d3") = (long)d3; \
347	__asm__ __volatile__ ("move.l %1,%%d0\n\t" \
348	"trap #2\n\t" \
349	"move.l %%d0,%0" \
350	: "=g" (ret) \
351	: "i" (SysCode_##name), "d" (__d1),\
352	"d" (__d2),\
353	"d" (__d3) \
354	: "d0" ); \
355	syscall_return(type,ret); \
356	}
357	#define SysCode_reset 0 /* reset */
358	#define SysCode_program 5 /* program flash memory */
359	#define SysCode_gethwaddr 12 /* get hardware address */
360	#define SysCode_getbenv 14 /* get bootloader environment variable */
361	#define SysCode_setbenv 15 /* get bootloader environment variable */
362	#define SysCode_flash_erase_range 19 /* erase a section of flash */
363	#define SysCode_flash_write_range 20 /* write a section of flash */
364	syscall_1(unsigned const char *, gethwaddr, int, a)
365	syscall_1(const char , getbenv, const char , a)
366	syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
367	syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
368	syscall_3(int, flash_write_range, volatile unsigned short , flashptr, bsp_mnode_t , chain, int, offset);
369
370	/*
371	* 'Extended BSP' routines
372	* Should move to cpukit/score/cpu/m68k/cpu.c someday.
373	*/
374
375	rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
376	int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
377	int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
378
379	/*
380	* 'VME' interrupt support
381	* Interrupt vectors 192-255 are set aside for use by external logic which
382	* drives IRQ1*. The actual interrupt source is read from the external
383	* logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant
384	* byte read from this location is set as long as the external logic has
385	* interrupts to be serviced. The least-significant six bits indicate the
386	* interrupt source within the external logic and are used to select the
387	* specified interupt handler.
388	*/
389	#define NVECTOR 256
390	#define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */
391	#define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL
392	#define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1
393	#define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1
394	#define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1
395	#define FPGA_IRQ_INFO ((vuint16 )(0x31000000 + 0xfffffe))
396
397	static struct handlerTab {
398	BSP_VME_ISR_t func;
399	void *arg;
400	} handlerTab[NVECTOR];
401
402	BSP_VME_ISR_t
403	BSP_getVME_isr(unsigned long vector, void **pusrArg)
404	{
405	if (vector >= NVECTOR)
406	return (BSP_VME_ISR_t)NULL;
407	if (pusrArg)
408	*pusrArg = handlerTab[vector].arg;
409	return handlerTab[vector].func;
410	}
411
412	static rtems_isr
413	trampoline (rtems_vector_number v)
414	{
415	/*
416	* Handle FPGA interrupts until all have been consumed
417	*/
418	if (v == FPGA_VECTOR) {
419	while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
420	v = 192 + (v & 0x3f);
421	if (handlerTab[v].func)
422	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
423	else
424	rtems_fatal_error_occurred(v);
425	}
426	}
427	else if (handlerTab[v].func)
428	(*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
429	}
430
431	int
432	BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
433	{
434	rtems_isr_entry old_handler;
435	rtems_interrupt_level level;
436
437	/*
438	* Register the handler information
439	*/
440	if (vector >= NVECTOR)
441	return -1;
442	handlerTab[vector].func = handler;
443	handlerTab[vector].arg = usrArg;
444
445	/*
446	* If this is an external FPGA ('VME') vector set up the real IRQ.
447	*/
448	if ((vector >= 192) && (vector <= 255)) {
449	int i;
450	static volatile int setupDone;
451	rtems_interrupt_disable(level);
452	if (setupDone) {
453	rtems_interrupt_enable(level);
454	return 0;
455	}
456	MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
457	MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
458	MCF5282_EPORT_EPIER \|= FPGA_EPIER;
459	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 \|
460	MCF5282_INTC_IMRL_MASKALL);
461	setupDone = 1;
462	i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
463	rtems_interrupt_enable(level);
464	return i;
465	}
466
467	/*
468	* Make the connection between the interrupt and the local handler
469	*/
470	rtems_interrupt_catch(trampoline, vector, &old_handler);
471
472	/*
473	* Find an unused level/priority if this is an on-chip (INTC0)
474	* source and this is the first time the source is being used.
475	* Interrupt sources 1 through 7 are fixed level/priority
476	*/
477	if ((vector >= 65) && (vector <= 127)) {
478	int l, p;
479	int source = vector - 64;
480	static unsigned char installed[8];
481
482	rtems_interrupt_disable(level);
483	if (installed[source/8] & (1 << (source % 8))) {
484	rtems_interrupt_enable(level);
485	return 0;
486	}
487	installed[source/8] \|= (1 << (source % 8));
488	rtems_interrupt_enable(level);
489	for (l = 1 ; l < 7 ; l++) {
490	for (p = 0 ; p < 8 ; p++) {
491	if ((source < 8)
492	\|\| (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
493	if (source >= 8)
494	*(&MCF5282_INTC0_ICR1 + (source - 1)) =
495	MCF5282_INTC_ICR_IL(l) \|
496	MCF5282_INTC_ICR_IP(p);
497	rtems_interrupt_disable(level);
498	if (source >= 32)
499	MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
500	else
501	MCF5282_INTC0_IMRL &= ~((1 << source) \|
502	MCF5282_INTC_IMRL_MASKALL);
503	rtems_interrupt_enable(level);
504	return 0;
505	}
506	}
507	}
508	return -1;
509	}
510	return 0;
511	}
512
513	int
514	BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
515	{
516	if (vector >= NVECTOR)
517	return -1;
518	if ((handlerTab[vector].func != handler)
519	\|\| (handlerTab[vector].arg != usrArg))
520	return -1;
521	handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
522	return 0;
523	}
524
525	int
526	BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
527	{
528	unsigned long offset;
529
530	switch (am) {
531	default: return -1;
532	case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
533	case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
534	case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
535	}
536	*plocaladdr = vmeaddr + offset;
537	return 0;
538	}

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