source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 12b36efe

4.104.114.84.95
Last change on this file since 12b36efe was 12b36efe, checked in by Eric Norum <WENorum@…>, on 11/07/05 at 17:22:23

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1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author: W. Eric Norum <norume@aps.anl.gov>
10 *
11 *  COPYRIGHT (c) 2005.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.OARcorp.com/rtems/license.html.
17 *
18 *  $Id$
19 */
20
21#include <bsp.h>
22#include <rtems/libio.h>
23#include <rtems/libcsupport.h>
24#include <string.h>
25#include <errno.h>
26 
27/*
28 *  The original table from the application and our copy of it with
29 *  some changes.
30 */
31extern rtems_configuration_table Configuration;
32rtems_configuration_table  BSP_Configuration;
33rtems_cpu_table Cpu_table;
34char *rtems_progname;
35
36/*
37 * Location of 'VME' access
38 */
39#define VME_ONE_BASE    0x30000000
40#define VME_TWO_BASE    0x31000000
41
42/*
43 * CPU-space access
44 * The NOP after writing the CACR is there to address the following issue as
45 * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004:
46 *
47 * 6 Possible Cache Corruption after Setting  CACR[CINV]
48 * 6.1 Description
49 * The cache on the MCF5282 was enhanced to function as a unified data and
50 * instruction cache, an instruction cache, or an operand cache.  The cache
51 * function and organization is controlled by the cache control register (CACR).
52 * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear.
53 * If the cache is configured as a unified cache and the CINV bit is set, the
54 * scope of the cache clear is controlled by two other bits in the CACR,
55 * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data
56 * cache only).  These bits allow the entire cache, just the instruction
57 * portion of the cache, or just the data portion of the cache to be cleared.
58 * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set)
59 * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set),
60 * then cache corruption may  occur.
61 *
62 * 6.2 Workaround
63 * All loads of the CACR that perform a cache clear operation (CINV = BIT 24)
64 * should be followed immediately by a NOP instruction.  This avoids the cache
65 * corruption problem.
66 * DATECODES AFFECTED: All
67 */
68#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
69#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
70#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
71#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
72
73/*
74 * Read/write copy of cache registers
75 *   Split instruction/data or instruction-only
76 *   Allow CPUSHL to invalidate a cache line
77 *   Enable buffered writes
78 *   No burst transfers on non-cacheable accesses
79 *   Default cache mode is *disabled* (cache only ACRx areas)
80 */
81uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB |
82#ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
83                             MCF5XXX_CACR_DISD |
84#endif
85                             MCF5XXX_CACR_DBWE |
86                             MCF5XXX_CACR_DCM;
87uint32_t mcf5282_acr0_mode = 0;
88uint32_t mcf5282_acr1_mode = 0;
89/*
90 * Cannot be frozen
91 */
92void _CPU_cache_freeze_data(void) {}
93void _CPU_cache_unfreeze_data(void) {}
94void _CPU_cache_freeze_instruction(void) {}
95void _CPU_cache_unfreeze_instruction(void) {}
96
97/*
98 * Write-through data cache -- flushes are unnecessary
99 */
100void _CPU_cache_flush_1_data_line(const void *d_addr) {}
101void _CPU_cache_flush_entire_data(void) {}
102
103void _CPU_cache_enable_instruction(void)
104{
105    rtems_interrupt_level level;
106
107    rtems_interrupt_disable(level);
108    mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI;
109    m68k_set_cacr(mcf5282_cacr_mode);
110    rtems_interrupt_enable(level);
111}
112
113void _CPU_cache_disable_instruction(void)
114{
115    rtems_interrupt_level level;
116
117    rtems_interrupt_disable(level);
118    mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI;
119    m68k_set_cacr(mcf5282_cacr_mode);
120    rtems_interrupt_enable(level);
121}
122
123void _CPU_cache_invalidate_entire_instruction(void)
124{
125    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
126}
127
128void _CPU_cache_invalidate_1_instruction_line(const void *addr)
129{
130    /*
131     * Top half of cache is I-space
132     */
133    addr = (void *)((int)addr | 0x400);
134    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
135}
136
137void _CPU_cache_enable_data(void)
138{
139#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
140    rtems_interrupt_level level;
141
142    rtems_interrupt_disable(level);
143    mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB;
144    m68k_set_cacr(mcf5282_cacr_mode);
145    rtems_interrupt_enable(level);
146#endif
147}
148
149void _CPU_cache_disable_data(void)
150{
151#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
152    rtems_interrupt_level level;
153
154    rtems_interrupt_disable(level);
155    rtems_interrupt_disable(level);
156    mcf5282_cacr_mode |= MCF5XXX_CACR_CENB;
157    m68k_set_cacr(mcf5282_cacr_mode);
158    rtems_interrupt_enable(level);
159#endif
160}
161
162void _CPU_cache_invalidate_entire_data(void)
163{
164#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
165    m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
166#endif
167}
168
169void _CPU_cache_invalidate_1_data_line(const void *addr)
170{
171#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
172    /*
173     * Bottom half of cache is D-space
174     */
175    addr = (void *)((int)addr & ~0x400);
176    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
177#endif
178}
179
180/*
181 *  Use the shared implementations of the following routines
182 */
183void bsp_postdriver_hook(void);
184void bsp_libc_init( void *, uint32_t, int );
185void bsp_pretasking_hook(void);         /* m68k version */
186
187/*
188 *  bsp_start
189 *
190 *  This routine does the bulk of the system initialisation.
191 */
192void bsp_start( void )
193{
194  extern char _WorkspaceBase[];
195  extern char _RamBase[], _RamSize[];
196  extern unsigned long  _M68k_Ramsize;
197
198  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
199
200  /*
201   *  Allocate the memory for the RTEMS Work Space.  This can come from
202   *  a variety of places: hard coded address, malloc'ed from outside
203   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
204   *  typically done by stock BSPs) by subtracting the required amount
205   *  of work space from the last physical address on the CPU board.
206   */
207
208  /*
209   *  Need to "allocate" the memory for the RTEMS Workspace and
210   *  tell the RTEMS configuration where it is.  This memory is
211   *  not malloc'ed.  It is just "pulled from the air".
212   */
213
214  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
215
216  /*
217   *  initialize the CPU table for this BSP
218   */
219  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
220  Cpu_table.postdriver_hook = bsp_postdriver_hook;
221  Cpu_table.do_zero_of_workspace = TRUE;
222  Cpu_table.interrupt_stack_size = 4096;
223
224  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
225
226    /*
227     * Invalidate the cache and disable it
228     */
229    m68k_set_acr0(mcf5282_acr0_mode);
230    m68k_set_acr1(mcf5282_acr1_mode);
231    m68k_set_cacr_nop(MCF5XXX_CACR_CINV);
232
233    /*
234     * Cache SDRAM
235     */
236    mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
237                        MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
238                        MCF5XXX_ACR_EN                         |
239                        MCF5XXX_ACR_BWE                        |
240                        MCF5XXX_ACR_SM_IGNORE;
241    m68k_set_acr0(mcf5282_acr0_mode);
242
243    /*
244     * Enable the cache
245     */
246    m68k_set_cacr(mcf5282_cacr_mode);
247
248    /*
249     * Set up CS* space (fake 'VME')
250     *   Two A24/D16 spaces, supervisor data acces
251     */
252    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
253    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
254                       MCF5282_CS_CSMR_CI |
255                       MCF5282_CS_CSMR_SC |
256                       MCF5282_CS_CSMR_UC |
257                       MCF5282_CS_CSMR_UD |
258                       MCF5282_CS_CSMR_V;
259    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
260    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
261    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
262                       MCF5282_CS_CSMR_CI |
263                       MCF5282_CS_CSMR_SC |
264                       MCF5282_CS_CSMR_UC |
265                       MCF5282_CS_CSMR_UD |
266                       MCF5282_CS_CSMR_V;
267    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
268    MCF5282_GPIO_PJPAR |= 0x06;
269}
270
271uint32_t bsp_get_CPU_clock_speed(void)
272{
273    extern char _CPUClockSpeed[];
274    return( (uint32_t)_CPUClockSpeed);
275}
276
277/*
278 * Interrupt controller allocation
279 */
280rtems_status_code
281bsp_allocate_interrupt(int level, int priority)
282{
283    static char used[7];
284    rtems_interrupt_level l;
285    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
286
287    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
288        return RTEMS_INVALID_NUMBER;
289    rtems_interrupt_disable(l);
290    if ((used[level-1] & (1 << priority)) == 0) {
291        used[level-1] |= (1 << priority);
292        ret = RTEMS_SUCCESSFUL;
293    }
294    rtems_interrupt_enable(l);
295    return ret;
296}
297
298/*
299 * Arcturus bootloader system calls
300 */
301#define syscall_return(type, ret)                      \
302do {                                                   \
303   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
304      errno = -(ret);                                  \
305      ret = -1;                                        \
306   }                                                   \
307   return (type)(ret);                                 \
308} while (0)
309#define syscall_1(type,name,d1type,d1)                      \
310type bsp_##name(d1type d1)                                  \
311{                                                           \
312   long ret;                                                \
313   register long __d1 __asm__ ("%d1") = (long)d1;           \
314   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
315                         "trap #2\n\t"                      \
316                         "move.l %%d0,%0"                   \
317                         : "=g" (ret)                       \
318                         : "i" (SysCode_##name), "d" (__d1) \
319                         : "d0" );                          \
320   syscall_return(type,ret);                                \
321}
322#define syscall_2(type,name,d1type,d1,d2type,d2)            \
323type bsp_##name(d1type d1, d2type d2)                       \
324{                                                           \
325   long ret;                                                \
326   register long __d1 __asm__ ("%d1") = (long)d1;           \
327   register long __d2 __asm__ ("%d2") = (long)d2;           \
328   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
329                         "trap #2\n\t"                      \
330                         "move.l %%d0,%0"                   \
331                         : "=g" (ret)                       \
332                         : "i" (SysCode_##name), "d" (__d1),\
333                                                 "d" (__d2) \
334                         : "d0" );                          \
335   syscall_return(type,ret);                                \
336}
337#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
338type bsp_##name(d1type d1, d2type d2, d3type d3)            \
339{                                                           \
340   long ret;                                                \
341   register long __d1 __asm__ ("%d1") = (long)d1;           \
342   register long __d2 __asm__ ("%d2") = (long)d2;           \
343   register long __d3 __asm__ ("%d3") = (long)d3;           \
344   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
345                         "trap #2\n\t"                      \
346                         "move.l %%d0,%0"                   \
347                         : "=g" (ret)                       \
348                         : "i" (SysCode_##name), "d" (__d1),\
349                                                 "d" (__d2),\
350                                                 "d" (__d3) \
351                         : "d0" );                          \
352   syscall_return(type,ret);                                \
353}
354#define SysCode_reset              0 /* reset */
355#define SysCode_program            5 /* program flash memory */
356#define SysCode_gethwaddr         12 /* get hardware address */
357#define SysCode_getbenv           14 /* get bootloader environment variable */
358#define SysCode_setbenv           15 /* get bootloader environment variable */
359#define SysCode_flash_erase_range 19 /* erase a section of flash */
360#define SysCode_flash_write_range 20 /* write a section of flash */
361syscall_1(int, reset, int, flags)
362syscall_1(unsigned const char *, gethwaddr, int, a)
363syscall_1(const char *, getbenv, const char *, a)
364syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
365syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
366syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
367
368/*
369 * 'Extended BSP' routines
370 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
371 */
372
373rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
374int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
375int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
376
377/*
378 * 'VME' interrupt support
379 * Interrupt vectors 192-255 are set aside for use by external logic which
380 * drives IRQ1*.  The actual interrupt source is read from the external
381 * logic at FPGA_IRQ_INFO.  The most-significant bit of the least-significant
382 * byte read from this location is set as long as the external logic has
383 * interrupts to be serviced.  The least-significant six bits indicate the
384 * interrupt source within the external logic and are used to select the
385 * specified interupt handler.
386 */
387#define NVECTOR 256
388#define FPGA_VECTOR (64+1)  /* IRQ1* pin connected to external FPGA */
389#define FPGA_EPPAR  MCF5282_EPORT_EPPAR_EPPA1_LEVEL
390#define FPGA_EPDDR  MCF5282_EPORT_EPDDR_EPDD1
391#define FPGA_EPIER  MCF5282_EPORT_EPIER_EPIE1
392#define FPGA_EPPDR  MCF5282_EPORT_EPPDR_EPPD1
393#define FPGA_IRQ_INFO    *((vuint16 *)(0x31000000 + 0xfffffe))
394
395static struct handlerTab {
396    BSP_VME_ISR_t func;
397    void         *arg;
398} handlerTab[NVECTOR];
399
400BSP_VME_ISR_t
401BSP_getVME_isr(unsigned long vector, void **pusrArg)
402{
403    if (vector >= NVECTOR)
404        return (BSP_VME_ISR_t)NULL;
405    if (pusrArg)
406        *pusrArg = handlerTab[vector].arg;
407    return handlerTab[vector].func;
408}
409
410static rtems_isr
411trampoline (rtems_vector_number v)
412{
413    /*
414     * Handle FPGA interrupts until all have been consumed
415     */
416    if (v == FPGA_VECTOR) {
417        while (((v = FPGA_IRQ_INFO) & 0x80) != 0) {
418            v = 192 + (v & 0x3f);
419            if (handlerTab[v].func)
420                (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
421            else
422                rtems_fatal_error_occurred(v);
423        }
424    }
425    else if (handlerTab[v].func)
426        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
427}
428
429int
430BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
431{
432    rtems_isr_entry old_handler;
433    rtems_interrupt_level level;
434
435    /*
436     * Register the handler information
437     */
438    if (vector >= NVECTOR)
439        return -1;
440    handlerTab[vector].func = handler;
441    handlerTab[vector].arg = usrArg;
442
443    /*
444     * If this is an external FPGA ('VME') vector set up the real IRQ.
445     */
446    if ((vector >= 192) && (vector <= 255)) {
447        int i;
448        static volatile int setupDone;
449        rtems_interrupt_disable(level);
450        if (setupDone) {
451            rtems_interrupt_enable(level);
452            return 0;
453        }
454        MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR;
455        MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR;
456        MCF5282_EPORT_EPIER |=  FPGA_EPIER;
457        MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 |
458                                MCF5282_INTC_IMRL_MASKALL);
459        setupDone = 1;
460        i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL);
461        rtems_interrupt_enable(level);
462        return i;
463    }
464
465    /*
466     * Make the connection between the interrupt and the local handler
467     */
468    rtems_interrupt_catch(trampoline, vector, &old_handler);
469
470    /*
471     * Find an unused level/priority if this is an on-chip (INTC0)
472     * source and this is the first time the source is being used.
473     * Interrupt sources 1 through 7 are fixed level/priority
474     */
475    if ((vector >= 65) && (vector <= 127)) {
476        int l, p;
477        int source = vector - 64;
478        static unsigned char installed[8];
479
480        rtems_interrupt_disable(level);
481        if (installed[source/8] & (1 << (source % 8))) {
482            rtems_interrupt_enable(level);
483            return 0;
484        }
485        installed[source/8] |= (1 << (source % 8));
486        rtems_interrupt_enable(level);
487        for (l = 1 ; l < 7 ; l++) {
488            for (p = 0 ; p < 8 ; p++) {
489                if ((source < 8)
490                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
491                    if (source >= 8)
492                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
493                                                       MCF5282_INTC_ICR_IL(l) |
494                                                       MCF5282_INTC_ICR_IP(p);
495                    rtems_interrupt_disable(level);
496                    if (source >= 32)
497                        MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
498                    else
499                        MCF5282_INTC0_IMRL &= ~((1 << source) |
500                                                MCF5282_INTC_IMRL_MASKALL);
501                    rtems_interrupt_enable(level);
502                    return 0;
503                }
504            }
505        }
506        return -1;
507    }
508    return 0;
509}
510
511int
512BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
513{
514    if (vector >= NVECTOR)
515        return -1;
516    if ((handlerTab[vector].func != handler)
517     || (handlerTab[vector].arg != usrArg))
518        return -1;
519    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
520    return 0;
521}
522
523int
524BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
525{
526    unsigned long offset;
527
528    switch (am) {
529    default:    return -1;
530    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
531    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
532    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
533    }
534    *plocaladdr = vmeaddr + offset;
535    return 0;
536}
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