source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ 059c95e

4.104.114.84.95
Last change on this file since 059c95e was 059c95e, checked in by Eric Norum <WENorum@…>, on 02/14/05 at 22:05:04

Don't cache flash.
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File size: 14.3 KB
Line 
1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
29#include <errno.h>
30 
31/*
32 *  The original table from the application and our copy of it with
33 *  some changes.
34 */
35extern rtems_configuration_table Configuration;
36rtems_configuration_table  BSP_Configuration;
37rtems_cpu_table Cpu_table;
38char *rtems_progname;
39
40/*
41 * Location of 'VME' access
42 */
43#define VME_ONE_BASE    0x30000000
44#define VME_TWO_BASE    0x31000000
45
46/*
47 * CPU-space access
48 */
49#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
50#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
51#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
52
53/*
54 * Read/write copy of common cache
55 *   Split I/D cache
56 *   Allow CPUSHL to invalidate a cache line
57 *   Enable buffered writes
58 *   No burst transfers on non-cacheable accesses
59 *   Default cache mode is *disabled* (cache only ACRx areas)
60 */
61static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
62                              MCF5XXX_CACR_DBWE |
63                              MCF5XXX_CACR_DCM;
64/*
65 * Cannot be frozen
66 */
67void _CPU_cache_freeze_data(void) {}
68void _CPU_cache_unfreeze_data(void) {}
69void _CPU_cache_freeze_instruction(void) {}
70void _CPU_cache_unfreeze_instruction(void) {}
71
72/*
73 * Write-through data cache -- flushes are unnecessary
74 */
75void _CPU_cache_flush_1_data_line(const void *d_addr) {}
76void _CPU_cache_flush_entire_data(void) {}
77
78void _CPU_cache_enable_instruction(void)
79{
80    rtems_interrupt_level level;
81
82    rtems_interrupt_disable(level);
83    cacr_mode &= ~MCF5XXX_CACR_DIDI;
84    m68k_set_cacr(cacr_mode);
85    rtems_interrupt_enable(level);
86}
87
88void _CPU_cache_disable_instruction(void)
89{
90    rtems_interrupt_level level;
91
92    rtems_interrupt_disable(level);
93    cacr_mode |= MCF5XXX_CACR_DIDI;
94    m68k_set_cacr(cacr_mode);
95    rtems_interrupt_enable(level);
96}
97
98void _CPU_cache_invalidate_entire_instruction(void)
99{
100    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
101}
102
103void _CPU_cache_invalidate_1_instruction_line(const void *addr)
104{
105    /*
106     * Top half of cache is I-space
107     */
108    addr = (void *)((int)addr | 0x400);
109    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
110}
111
112void _CPU_cache_enable_data(void)
113{
114    rtems_interrupt_level level;
115
116    rtems_interrupt_disable(level);
117    cacr_mode &= ~MCF5XXX_CACR_DISD;
118    m68k_set_cacr(cacr_mode);
119    rtems_interrupt_enable(level);
120}
121
122void _CPU_cache_disable_data(void)
123{
124    rtems_interrupt_level level;
125
126    rtems_interrupt_disable(level);
127    rtems_interrupt_disable(level);
128    cacr_mode |= MCF5XXX_CACR_DISD;
129    m68k_set_cacr(cacr_mode);
130    rtems_interrupt_enable(level);
131}
132
133void _CPU_cache_invalidate_entire_data(void)
134{
135    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
136}
137
138void _CPU_cache_invalidate_1_data_line(const void *addr)
139{
140    /*
141     * Bottom half of cache is D-space
142     */
143    addr = (void *)((int)addr & ~0x400);
144    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
145}
146
147/*
148 *  Use the shared implementations of the following routines
149 */
150void bsp_postdriver_hook(void);
151void bsp_libc_init( void *, uint32_t, int );
152void bsp_pretasking_hook(void);         /* m68k version */
153
154/*
155 *  bsp_start
156 *
157 *  This routine does the bulk of the system initialisation.
158 */
159void bsp_start( void )
160{
161  extern char _WorkspaceBase[];
162  extern char _RamBase[], _RamSize[];
163  extern char _FlashBase[], _FlashSize[];
164  extern unsigned long  _M68k_Ramsize;
165
166  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
167
168  /*
169   *  Allocate the memory for the RTEMS Work Space.  This can come from
170   *  a variety of places: hard coded address, malloc'ed from outside
171   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
172   *  typically done by stock BSPs) by subtracting the required amount
173   *  of work space from the last physical address on the CPU board.
174   */
175
176  /*
177   *  Need to "allocate" the memory for the RTEMS Workspace and
178   *  tell the RTEMS configuration where it is.  This memory is
179   *  not malloc'ed.  It is just "pulled from the air".
180   */
181
182  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
183
184  /*
185   *  initialize the CPU table for this BSP
186   */
187  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
188  Cpu_table.postdriver_hook = bsp_postdriver_hook;
189  Cpu_table.do_zero_of_workspace = TRUE;
190  Cpu_table.interrupt_stack_size = 4096;
191
192  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
193
194    /*
195     * Invalidate the cache and disable it
196     */
197    m68k_set_acr0(0);
198    m68k_set_acr1(0);
199    m68k_set_cacr(MCF5XXX_CACR_CINV);
200
201    /*
202     * Cache SDRAM
203     */
204    m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
205                  MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
206                  MCF5XXX_ACR_EN                         |
207                  MCF5XXX_ACR_BWE                        |
208                  MCF5XXX_ACR_SM_IGNORE);
209
210    /*
211     * Enable the cache
212     */
213    m68k_set_cacr(cacr_mode);
214
215    /*
216     * Set up CS* space (fake 'VME')
217     *   Two A24/D16 spaces, supervisor data acces
218     */
219    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
220    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
221                       MCF5282_CS_CSMR_CI |
222                       MCF5282_CS_CSMR_SC |
223                       MCF5282_CS_CSMR_UC |
224                       MCF5282_CS_CSMR_UD |
225                       MCF5282_CS_CSMR_V;
226    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
227    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
228    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
229                       MCF5282_CS_CSMR_CI |
230                       MCF5282_CS_CSMR_SC |
231                       MCF5282_CS_CSMR_UC |
232                       MCF5282_CS_CSMR_UD |
233                       MCF5282_CS_CSMR_V;
234    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
235}
236
237uint32_t bsp_get_CPU_clock_speed(void)
238{
239    extern char _CPUClockSpeed[];
240    return( (uint32_t)_CPUClockSpeed);
241}
242
243/*
244 * Interrupt controller allocation
245 */
246rtems_status_code
247bsp_allocate_interrupt(int level, int priority)
248{
249    static char used[7];
250    rtems_interrupt_level l;
251    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
252
253    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
254        return RTEMS_INVALID_NUMBER;
255    rtems_interrupt_disable(l);
256    if ((used[level-1] & (1 << priority)) == 0) {
257        used[level-1] |= (1 << priority);
258        ret = RTEMS_SUCCESSFUL;
259    }
260    rtems_interrupt_enable(l);
261    return ret;
262}
263
264/*
265 * Arcturus bootloader system calls
266 */
267#define syscall_return(type, ret)                      \
268do {                                                   \
269   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
270      errno = -(ret);                                  \
271      ret = -1;                                        \
272   }                                                   \
273   return (type)(ret);                                 \
274} while (0)
275#define syscall_1(type,name,d1type,d1)                      \
276type bsp_##name(d1type d1)                                  \
277{                                                           \
278   long ret;                                                \
279   register long __d1 __asm__ ("%d1") = (long)d1;           \
280   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
281                         "trap #2\n\t"                      \
282                         "move.l %%d0,%0"                   \
283                         : "=g" (ret)                       \
284                         : "i" (SysCode_##name), "d" (__d1) \
285                         : "d0" );                          \
286   syscall_return(type,ret);                                \
287}
288#define syscall_2(type,name,d1type,d1,d2type,d2)            \
289type bsp_##name(d1type d1, d2type d2)                       \
290{                                                           \
291   long ret;                                                \
292   register long __d1 __asm__ ("%d1") = (long)d1;           \
293   register long __d2 __asm__ ("%d2") = (long)d2;           \
294   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
295                         "trap #2\n\t"                      \
296                         "move.l %%d0,%0"                   \
297                         : "=g" (ret)                       \
298                         : "i" (SysCode_##name), "d" (__d1),\
299                                                 "d" (__d2) \
300                         : "d0" );                          \
301   syscall_return(type,ret);                                \
302}
303#define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3)  \
304type bsp_##name(d1type d1, d2type d2, d3type d3)            \
305{                                                           \
306   long ret;                                                \
307   register long __d1 __asm__ ("%d1") = (long)d1;           \
308   register long __d2 __asm__ ("%d2") = (long)d2;           \
309   register long __d3 __asm__ ("%d3") = (long)d3;           \
310   __asm__ __volatile__ ("move.l %1,%%d0\n\t"               \
311                         "trap #2\n\t"                      \
312                         "move.l %%d0,%0"                   \
313                         : "=g" (ret)                       \
314                         : "i" (SysCode_##name), "d" (__d1),\
315                                                 "d" (__d2),\
316                                                 "d" (__d3) \
317                         : "d0" );                          \
318   syscall_return(type,ret);                                \
319}
320#define SysCode_reset              0 /* reset */
321#define SysCode_program            5 /* program flash memory */
322#define SysCode_gethwaddr         12 /* get hardware address */
323#define SysCode_getbenv           14 /* get bootloader environment variable */
324#define SysCode_setbenv           15 /* get bootloader environment variable */
325#define SysCode_flash_erase_range 19 /* erase a section of flash */
326#define SysCode_flash_write_range 20 /* write a section of flash */
327syscall_1(unsigned const char *, gethwaddr, int, a)
328syscall_1(const char *, getbenv, const char *, a)
329syscall_2(int, program, bsp_mnode_t *, chain, int, flags)
330syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end);
331syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset);
332
333/*
334 * 'Extended BSP' routines
335 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
336 */
337
338rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
339int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
340int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
341
342/*
343 * VME interrupt support
344 */
345#define NVECTOR 256
346
347static struct handlerTab {
348    BSP_VME_ISR_t func;
349    void         *arg;
350} handlerTab[NVECTOR];
351
352BSP_VME_ISR_t
353BSP_getVME_isr(unsigned long vector, void **pusrArg)
354{
355    if (vector >= NVECTOR)
356        return (BSP_VME_ISR_t)NULL;
357    if (pusrArg)
358        *pusrArg = handlerTab[vector].arg;
359    return handlerTab[vector].func;
360}
361
362static rtems_isr
363trampoline (rtems_vector_number v)
364{
365    if (handlerTab[v].func)
366        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
367}
368
369int
370BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
371{
372    rtems_isr_entry old_handler;
373
374    if (vector >= NVECTOR)
375        return -1;
376    handlerTab[vector].func = handler;
377    handlerTab[vector].arg = usrArg;
378    rtems_interrupt_catch(trampoline, vector, &old_handler);
379
380    /*
381     * Find an unused level/priority if this is an on-chip (INTC0)
382     * source and this is the first time the source is being used.
383     * Interrupt sources 1 through 7 are fixed level/priority
384     */
385    if ((vector >= 65) && (vector <= 127)) {
386        int l, p;
387        int source = vector - 64;
388        rtems_interrupt_level level;
389        static unsigned char installed[8];
390
391        rtems_interrupt_disable(level);
392        if (installed[source/8] & (1 << (source % 8))) {
393            rtems_interrupt_enable(level);
394            return 0;
395        }
396        installed[source/8] |= (1 << (source % 8));
397        rtems_interrupt_enable(level);
398        for (l = 1 ; l < 7 ; l++) {
399            for (p = 0 ; p < 8 ; p++) {
400                if ((source < 8)
401                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
402                    if (source >= 8)
403                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
404                                                       MCF5282_INTC_ICR_IL(l) |
405                                                       MCF5282_INTC_ICR_IP(p);
406                    rtems_interrupt_disable(level);
407                    if (source >= 32)
408                        MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
409                    else
410                        MCF5282_INTC0_IMRL &= ~((1 << source) |
411                                                MCF5282_INTC_IMRL_MASKALL);
412                    rtems_interrupt_enable(level);
413                    return 0;
414                }
415            }
416        }
417        return -1;
418    }
419    return 0;
420}
421
422int
423BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
424{
425    if (vector >= NVECTOR)
426        return -1;
427    if ((handlerTab[vector].func != handler)
428     || (handlerTab[vector].arg != usrArg))
429        return -1;
430    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
431    return 0;
432}
433
434int
435BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
436{
437    unsigned long offset;
438
439    switch (am) {
440    default:    return -1;
441    case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */
442    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
443    case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */
444    }
445    *plocaladdr = vmeaddr + offset;
446    return 0;
447}
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