[572484f] | 1 | /* |
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| 2 | * BSP startup |
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| 3 | * |
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| 4 | * This routine starts the application. It includes application, |
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| 5 | * board, and monitor specific initialization and configuration. |
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| 6 | * The generic CPU dependent initialization has been performed |
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| 7 | * before this routine is invoked. |
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| 8 | * |
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| 9 | * Author: |
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| 10 | * David Fiddes, D.J@fiddes.surfaid.org |
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| 11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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| 12 | * |
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| 13 | * COPYRIGHT (c) 1989-1998. |
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| 14 | * On-Line Applications Research Corporation (OAR). |
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| 15 | * Copyright assigned to U.S. Government, 1994. |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * |
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| 20 | * http://www.OARcorp.com/rtems/license.html. |
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| 21 | * |
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| 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <bsp.h> |
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| 26 | #include <rtems/libio.h> |
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| 27 | #include <rtems/libcsupport.h> |
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| 28 | #include <string.h> |
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[7eab0f78] | 29 | #include <errno.h> |
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[572484f] | 30 | |
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| 31 | /* |
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| 32 | * The original table from the application and our copy of it with |
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| 33 | * some changes. |
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| 34 | */ |
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| 35 | extern rtems_configuration_table Configuration; |
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| 36 | rtems_configuration_table BSP_Configuration; |
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| 37 | rtems_cpu_table Cpu_table; |
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| 38 | char *rtems_progname; |
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| 39 | |
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| 40 | /* |
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| 41 | * Location of 'VME' access |
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| 42 | */ |
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| 43 | #define VME_ONE_BASE 0x30000000 |
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| 44 | #define VME_TWO_BASE 0x31000000 |
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| 45 | |
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| 46 | /* |
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| 47 | * CPU-space access |
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| 48 | */ |
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| 49 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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| 50 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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| 51 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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| 52 | |
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| 53 | /* |
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| 54 | * Read/write copy of common cache |
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| 55 | * Split I/D cache |
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| 56 | * Allow CPUSHL to invalidate a cache line |
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| 57 | * Enable buffered writes |
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| 58 | * No burst transfers on non-cacheable accesses |
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| 59 | * Default cache mode is *disabled* (cache only ACRx areas) |
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| 60 | */ |
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[0b2c943] | 61 | static uint32_t cacr_mode = MCF5XXX_CACR_CENB | |
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[572484f] | 62 | MCF5XXX_CACR_DBWE | |
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| 63 | MCF5XXX_CACR_DCM; |
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| 64 | /* |
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| 65 | * Cannot be frozen |
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| 66 | */ |
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| 67 | void _CPU_cache_freeze_data(void) {} |
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| 68 | void _CPU_cache_unfreeze_data(void) {} |
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| 69 | void _CPU_cache_freeze_instruction(void) {} |
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| 70 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 71 | |
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| 72 | /* |
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| 73 | * Write-through data cache -- flushes are unnecessary |
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| 74 | */ |
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| 75 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 76 | void _CPU_cache_flush_entire_data(void) {} |
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| 77 | |
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| 78 | void _CPU_cache_enable_instruction(void) |
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| 79 | { |
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| 80 | rtems_interrupt_level level; |
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| 81 | |
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| 82 | rtems_interrupt_disable(level); |
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| 83 | cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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| 84 | m68k_set_cacr(cacr_mode); |
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| 85 | rtems_interrupt_enable(level); |
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| 86 | } |
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| 87 | |
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| 88 | void _CPU_cache_disable_instruction(void) |
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| 89 | { |
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| 90 | rtems_interrupt_level level; |
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| 91 | |
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| 92 | rtems_interrupt_disable(level); |
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| 93 | cacr_mode |= MCF5XXX_CACR_DIDI; |
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| 94 | m68k_set_cacr(cacr_mode); |
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| 95 | rtems_interrupt_enable(level); |
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| 96 | } |
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| 97 | |
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| 98 | void _CPU_cache_invalidate_entire_instruction(void) |
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| 99 | { |
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| 100 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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| 101 | } |
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| 102 | |
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| 103 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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| 104 | { |
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[518edef] | 105 | /* |
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| 106 | * Top half of cache is I-space |
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| 107 | */ |
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| 108 | addr = (void *)((int)addr | 0x400); |
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| 109 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[572484f] | 110 | } |
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| 111 | |
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| 112 | void _CPU_cache_enable_data(void) |
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| 113 | { |
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| 114 | rtems_interrupt_level level; |
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| 115 | |
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| 116 | rtems_interrupt_disable(level); |
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| 117 | cacr_mode &= ~MCF5XXX_CACR_DISD; |
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| 118 | m68k_set_cacr(cacr_mode); |
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| 119 | rtems_interrupt_enable(level); |
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| 120 | } |
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| 121 | |
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| 122 | void _CPU_cache_disable_data(void) |
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| 123 | { |
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| 124 | rtems_interrupt_level level; |
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| 125 | |
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[518edef] | 126 | rtems_interrupt_disable(level); |
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[572484f] | 127 | rtems_interrupt_disable(level); |
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| 128 | cacr_mode |= MCF5XXX_CACR_DISD; |
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| 129 | m68k_set_cacr(cacr_mode); |
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| 130 | rtems_interrupt_enable(level); |
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| 131 | } |
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| 132 | |
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| 133 | void _CPU_cache_invalidate_entire_data(void) |
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| 134 | { |
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| 135 | m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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| 136 | } |
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| 137 | |
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| 138 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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| 139 | { |
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[518edef] | 140 | /* |
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| 141 | * Bottom half of cache is D-space |
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| 142 | */ |
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| 143 | addr = (void *)((int)addr & ~0x400); |
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| 144 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[572484f] | 145 | } |
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| 146 | |
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| 147 | /* |
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| 148 | * Use the shared implementations of the following routines |
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| 149 | */ |
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| 150 | void bsp_postdriver_hook(void); |
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[0b2c943] | 151 | void bsp_libc_init( void *, uint32_t, int ); |
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[d75023e] | 152 | void bsp_pretasking_hook(void); /* m68k version */ |
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[572484f] | 153 | |
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| 154 | /* |
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| 155 | * bsp_start |
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| 156 | * |
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| 157 | * This routine does the bulk of the system initialisation. |
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| 158 | */ |
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| 159 | void bsp_start( void ) |
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| 160 | { |
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| 161 | extern char _WorkspaceBase[]; |
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[0eff7b8] | 162 | extern char _RamBase[], _RamSize[]; |
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| 163 | extern char _FlashBase[], _FlashSize[]; |
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[572484f] | 164 | extern unsigned long _M68k_Ramsize; |
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| 165 | |
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[d75023e] | 166 | _M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */ |
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[572484f] | 167 | |
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| 168 | /* |
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| 169 | * Allocate the memory for the RTEMS Work Space. This can come from |
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| 170 | * a variety of places: hard coded address, malloc'ed from outside |
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| 171 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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| 172 | * typically done by stock BSPs) by subtracting the required amount |
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| 173 | * of work space from the last physical address on the CPU board. |
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| 174 | */ |
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| 175 | |
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| 176 | /* |
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| 177 | * Need to "allocate" the memory for the RTEMS Workspace and |
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| 178 | * tell the RTEMS configuration where it is. This memory is |
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| 179 | * not malloc'ed. It is just "pulled from the air". |
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| 180 | */ |
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| 181 | |
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| 182 | BSP_Configuration.work_space_start = (void *)_WorkspaceBase; |
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| 183 | |
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| 184 | /* |
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| 185 | * initialize the CPU table for this BSP |
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| 186 | */ |
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| 187 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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| 188 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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| 189 | Cpu_table.do_zero_of_workspace = TRUE; |
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| 190 | Cpu_table.interrupt_stack_size = 4096; |
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| 191 | |
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| 192 | Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */ |
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| 193 | |
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| 194 | /* |
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| 195 | * Invalidate the cache and disable it |
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| 196 | */ |
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| 197 | m68k_set_acr0(0); |
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| 198 | m68k_set_acr1(0); |
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| 199 | m68k_set_cacr(MCF5XXX_CACR_CINV); |
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| 200 | |
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| 201 | /* |
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| 202 | * Cache SDRAM and FLASH |
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| 203 | */ |
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[0eff7b8] | 204 | m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase) | |
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| 205 | MCF5XXX_ACR_AM((uint32_t)_RamSize-1) | |
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| 206 | MCF5XXX_ACR_EN | |
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| 207 | MCF5XXX_ACR_BWE | |
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[572484f] | 208 | MCF5XXX_ACR_SM_IGNORE); |
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[0eff7b8] | 209 | m68k_set_acr1(MCF5XXX_ACR_AB((uint32_t)_FlashBase) | |
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| 210 | MCF5XXX_ACR_AM((uint32_t)_FlashSize-1) | |
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| 211 | MCF5XXX_ACR_EN | |
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[572484f] | 212 | MCF5XXX_ACR_SM_IGNORE); |
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| 213 | |
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| 214 | /* |
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| 215 | * Enable the cache |
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| 216 | */ |
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| 217 | m68k_set_cacr(cacr_mode); |
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| 218 | |
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| 219 | /* |
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| 220 | * Set up CS* space (fake 'VME') |
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| 221 | * Two A24/D16 spaces, supervisor data acces |
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| 222 | */ |
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| 223 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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| 224 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 225 | MCF5282_CS_CSMR_CI | |
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| 226 | MCF5282_CS_CSMR_SC | |
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| 227 | MCF5282_CS_CSMR_UC | |
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| 228 | MCF5282_CS_CSMR_UD | |
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| 229 | MCF5282_CS_CSMR_V; |
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| 230 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 231 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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| 232 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 233 | MCF5282_CS_CSMR_CI | |
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| 234 | MCF5282_CS_CSMR_SC | |
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| 235 | MCF5282_CS_CSMR_UC | |
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| 236 | MCF5282_CS_CSMR_UD | |
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| 237 | MCF5282_CS_CSMR_V; |
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| 238 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 239 | } |
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| 240 | |
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[0b2c943] | 241 | uint32_t bsp_get_CPU_clock_speed(void) |
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[572484f] | 242 | { |
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| 243 | extern char _CPUClockSpeed[]; |
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[0b2c943] | 244 | return( (uint32_t)_CPUClockSpeed); |
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[572484f] | 245 | } |
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[7eab0f78] | 246 | |
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[5b6111b] | 247 | /* |
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| 248 | * Interrupt controller allocation |
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| 249 | */ |
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[d75023e] | 250 | rtems_status_code |
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| 251 | bsp_allocate_interrupt(int level, int priority) |
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[5b6111b] | 252 | { |
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| 253 | static char used[7]; |
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| 254 | rtems_interrupt_level l; |
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[d75023e] | 255 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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[5b6111b] | 256 | |
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| 257 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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[d75023e] | 258 | return RTEMS_INVALID_NUMBER; |
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[5b6111b] | 259 | rtems_interrupt_disable(l); |
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| 260 | if ((used[level-1] & (1 << priority)) == 0) { |
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| 261 | used[level-1] |= (1 << priority); |
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[d75023e] | 262 | ret = RTEMS_SUCCESSFUL; |
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[5b6111b] | 263 | } |
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| 264 | rtems_interrupt_enable(l); |
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| 265 | return ret; |
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| 266 | } |
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| 267 | |
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[7eab0f78] | 268 | /* |
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[12993b3] | 269 | * Arcturus bootloader system calls |
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[7eab0f78] | 270 | */ |
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[12993b3] | 271 | #define syscall_return(type, ret) \ |
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| 272 | do { \ |
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| 273 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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| 274 | errno = -(ret); \ |
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| 275 | ret = -1; \ |
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| 276 | } \ |
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| 277 | return (type)(ret); \ |
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[7eab0f78] | 278 | } while (0) |
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[12993b3] | 279 | #define syscall_1(type,name,d1type,d1) \ |
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| 280 | type uC5282_##name(d1type d1) \ |
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| 281 | { \ |
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| 282 | long ret; \ |
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| 283 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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| 284 | __asm__ __volatile__ ("move.l %0,%%d0\n\t" \ |
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| 285 | "trap #2\n\t" \ |
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| 286 | "move.l %%d0,%0" \ |
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| 287 | : "=g" (ret) \ |
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| 288 | : "d" (SysCode_##name), "d" (__d1) \ |
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| 289 | : "d0" ); \ |
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| 290 | syscall_return(type,ret); \ |
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[7eab0f78] | 291 | } |
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[12993b3] | 292 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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| 293 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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| 294 | #define SysCode_setbenv 15 /* get bootloader environment variable */ |
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| 295 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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| 296 | syscall_1(const char *, getbenv, const char *, a) |
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[d75023e] | 297 | |
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| 298 | |
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| 299 | /* |
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| 300 | * 'Extended BSP' routines |
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| 301 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
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| 302 | */ |
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| 303 | |
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| 304 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
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| 305 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
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| 306 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
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| 307 | |
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| 308 | /* |
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| 309 | * VME interrupt support |
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| 310 | */ |
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[a7e6bc96] | 311 | #define NVECTOR 256 |
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| 312 | |
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[d75023e] | 313 | static struct handlerTab { |
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| 314 | BSP_VME_ISR_t func; |
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| 315 | void *arg; |
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[a7e6bc96] | 316 | } handlerTab[NVECTOR]; |
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[d75023e] | 317 | |
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| 318 | BSP_VME_ISR_t |
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| 319 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
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| 320 | { |
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[a7e6bc96] | 321 | if (vector >= NVECTOR) |
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[d75023e] | 322 | return (BSP_VME_ISR_t)NULL; |
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| 323 | if (pusrArg) |
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| 324 | *pusrArg = handlerTab[vector].arg; |
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| 325 | return handlerTab[vector].func; |
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| 326 | } |
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| 327 | |
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| 328 | static rtems_isr |
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[a7e6bc96] | 329 | trampoline (rtems_vector_number v) |
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[d75023e] | 330 | { |
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[a7e6bc96] | 331 | if (handlerTab[v].func) |
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[d75023e] | 332 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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| 333 | } |
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| 334 | |
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| 335 | int |
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| 336 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 337 | { |
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| 338 | rtems_isr_entry old_handler; |
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| 339 | |
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[a7e6bc96] | 340 | if (vector >= NVECTOR) |
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[d75023e] | 341 | return -1; |
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| 342 | handlerTab[vector].func = handler; |
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| 343 | handlerTab[vector].arg = usrArg; |
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[be129f69] | 344 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
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[d75023e] | 345 | |
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| 346 | /* |
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[a7e6bc96] | 347 | * Find an unused level/priority if this is an on-chip (INTC0) |
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| 348 | * source and this is the first time the source is being used. |
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| 349 | * Interrupt sources 1 through 7 are fixed level/priority |
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[d75023e] | 350 | */ |
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| 351 | if ((vector >= 65) && (vector <= 127)) { |
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| 352 | int l, p; |
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[a7e6bc96] | 353 | int source = vector - 64; |
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[d75023e] | 354 | rtems_interrupt_level level; |
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[a7e6bc96] | 355 | static unsigned char installed[8]; |
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[d75023e] | 356 | |
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[f3f4be7] | 357 | rtems_interrupt_disable(level); |
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| 358 | if (installed[source/8] & (1 << (source % 8))) { |
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| 359 | rtems_interrupt_enable(level); |
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[a7e6bc96] | 360 | return 0; |
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[f3f4be7] | 361 | } |
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[a7e6bc96] | 362 | installed[source/8] |= (1 << (source % 8)); |
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[f3f4be7] | 363 | rtems_interrupt_enable(level); |
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[d75023e] | 364 | for (l = 1 ; l < 7 ; l++) { |
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| 365 | for (p = 0 ; p < 7 ; p++) { |
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[a7e6bc96] | 366 | if ((source < 8) |
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| 367 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
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[8e712757] | 368 | if (source >= 8) |
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[a7e6bc96] | 369 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
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[d75023e] | 370 | MCF5282_INTC_ICR_IL(l) | |
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| 371 | MCF5282_INTC_ICR_IP(p); |
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| 372 | rtems_interrupt_disable(level); |
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[a7e6bc96] | 373 | if (source >= 32) |
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| 374 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
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[d75023e] | 375 | else |
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[a7e6bc96] | 376 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
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[d75023e] | 377 | MCF5282_INTC_IMRL_MASKALL); |
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| 378 | rtems_interrupt_enable(level); |
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| 379 | return 0; |
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| 380 | } |
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| 381 | } |
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| 382 | } |
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[a7e6bc96] | 383 | return -1; |
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[d75023e] | 384 | } |
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[a7e6bc96] | 385 | return 0; |
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[d75023e] | 386 | } |
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| 387 | |
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| 388 | int |
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| 389 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 390 | { |
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[a7e6bc96] | 391 | if (vector >= NVECTOR) |
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[d75023e] | 392 | return -1; |
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| 393 | if ((handlerTab[vector].func != handler) |
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| 394 | || (handlerTab[vector].arg != usrArg)) |
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| 395 | return -1; |
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| 396 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
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| 397 | return 0; |
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| 398 | } |
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| 399 | |
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| 400 | int |
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| 401 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
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| 402 | { |
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| 403 | unsigned long offset; |
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| 404 | |
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| 405 | switch (am) { |
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| 406 | default: return -1; |
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| 407 | case VME_AM_SUP_SHORT_IO: offset = 0x31000000; break; /* A16/D16 */ |
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| 408 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
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| 409 | case VME_AM_EXT_SUP_DATA: return -1; /* A32/D32 */ |
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| 410 | } |
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| 411 | *plocaladdr = vmeaddr + offset; |
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| 412 | return 0; |
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| 413 | } |
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