source: rtems/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @ f3f4be7

4.104.114.84.95
Last change on this file since f3f4be7 was f3f4be7, checked in by Eric Norum <WENorum@…>, on 02/08/05 at 00:21:08

Ensure consistency of 'installed' bitmap.

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[572484f]1/*
2 *  BSP startup
3 *
4 *  This routine starts the application.  It includes application,
5 *  board, and monitor specific initialization and configuration.
6 *  The generic CPU dependent initialization has been performed
7 *  before this routine is invoked.
8 *
9 *  Author:
10 *    David Fiddes, D.J@fiddes.surfaid.org
11 *    http://www.calm.hw.ac.uk/davidf/coldfire/
12 *
13 *  COPYRIGHT (c) 1989-1998.
14 *  On-Line Applications Research Corporation (OAR).
15 *  Copyright assigned to U.S. Government, 1994.
16 *
17 *  The license and distribution terms for this file may be
18 *  found in the file LICENSE in this distribution or at
19 *
20 *  http://www.OARcorp.com/rtems/license.html.
21 *
22 *  $Id$
23 */
24
25#include <bsp.h>
26#include <rtems/libio.h>
27#include <rtems/libcsupport.h>
28#include <string.h>
[7eab0f78]29#include <errno.h>
[572484f]30 
31/*
32 *  The original table from the application and our copy of it with
33 *  some changes.
34 */
35extern rtems_configuration_table Configuration;
36rtems_configuration_table  BSP_Configuration;
37rtems_cpu_table Cpu_table;
38char *rtems_progname;
39
40/*
41 * Location of 'VME' access
42 */
43#define VME_ONE_BASE    0x30000000
44#define VME_TWO_BASE    0x31000000
45
46/*
47 * CPU-space access
48 */
49#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr))
50#define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0))
51#define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1))
52
53/*
54 * Read/write copy of common cache
55 *   Split I/D cache
56 *   Allow CPUSHL to invalidate a cache line
57 *   Enable buffered writes
58 *   No burst transfers on non-cacheable accesses
59 *   Default cache mode is *disabled* (cache only ACRx areas)
60 */
[0b2c943]61static uint32_t cacr_mode = MCF5XXX_CACR_CENB |
[572484f]62                              MCF5XXX_CACR_DBWE |
63                              MCF5XXX_CACR_DCM;
64/*
65 * Cannot be frozen
66 */
67void _CPU_cache_freeze_data(void) {}
68void _CPU_cache_unfreeze_data(void) {}
69void _CPU_cache_freeze_instruction(void) {}
70void _CPU_cache_unfreeze_instruction(void) {}
71
72/*
73 * Write-through data cache -- flushes are unnecessary
74 */
75void _CPU_cache_flush_1_data_line(const void *d_addr) {}
76void _CPU_cache_flush_entire_data(void) {}
77
78void _CPU_cache_enable_instruction(void)
79{
80    rtems_interrupt_level level;
81
82    rtems_interrupt_disable(level);
83    cacr_mode &= ~MCF5XXX_CACR_DIDI;
84    m68k_set_cacr(cacr_mode);
85    rtems_interrupt_enable(level);
86}
87
88void _CPU_cache_disable_instruction(void)
89{
90    rtems_interrupt_level level;
91
92    rtems_interrupt_disable(level);
93    cacr_mode |= MCF5XXX_CACR_DIDI;
94    m68k_set_cacr(cacr_mode);
95    rtems_interrupt_enable(level);
96}
97
98void _CPU_cache_invalidate_entire_instruction(void)
99{
100    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI);
101}
102
103void _CPU_cache_invalidate_1_instruction_line(const void *addr)
104{
[518edef]105    /*
106     * Top half of cache is I-space
107     */
108    addr = (void *)((int)addr | 0x400);
109    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
[572484f]110}
111
112void _CPU_cache_enable_data(void)
113{
114    rtems_interrupt_level level;
115
116    rtems_interrupt_disable(level);
117    cacr_mode &= ~MCF5XXX_CACR_DISD;
118    m68k_set_cacr(cacr_mode);
119    rtems_interrupt_enable(level);
120}
121
122void _CPU_cache_disable_data(void)
123{
124    rtems_interrupt_level level;
125
[518edef]126    rtems_interrupt_disable(level);
[572484f]127    rtems_interrupt_disable(level);
128    cacr_mode |= MCF5XXX_CACR_DISD;
129    m68k_set_cacr(cacr_mode);
130    rtems_interrupt_enable(level);
131}
132
133void _CPU_cache_invalidate_entire_data(void)
134{
135    m68k_set_cacr(cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD);
136}
137
138void _CPU_cache_invalidate_1_data_line(const void *addr)
139{
[518edef]140    /*
141     * Bottom half of cache is D-space
142     */
143    addr = (void *)((int)addr & ~0x400);
144    asm volatile ("cpushl %%bc,(%0)" :: "a" (addr));
[572484f]145}
146
147/*
148 *  Use the shared implementations of the following routines
149 */
150void bsp_postdriver_hook(void);
[0b2c943]151void bsp_libc_init( void *, uint32_t, int );
[d75023e]152void bsp_pretasking_hook(void);         /* m68k version */
[572484f]153
154/*
155 *  bsp_start
156 *
157 *  This routine does the bulk of the system initialisation.
158 */
159void bsp_start( void )
160{
161  extern char _WorkspaceBase[];
[0eff7b8]162  extern char _RamBase[], _RamSize[];
163  extern char _FlashBase[], _FlashSize[];
[572484f]164  extern unsigned long  _M68k_Ramsize;
165
[d75023e]166  _M68k_Ramsize = (unsigned long)_RamSize;      /* RAM size set in linker script */
[572484f]167
168  /*
169   *  Allocate the memory for the RTEMS Work Space.  This can come from
170   *  a variety of places: hard coded address, malloc'ed from outside
171   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
172   *  typically done by stock BSPs) by subtracting the required amount
173   *  of work space from the last physical address on the CPU board.
174   */
175
176  /*
177   *  Need to "allocate" the memory for the RTEMS Workspace and
178   *  tell the RTEMS configuration where it is.  This memory is
179   *  not malloc'ed.  It is just "pulled from the air".
180   */
181
182  BSP_Configuration.work_space_start = (void *)_WorkspaceBase;
183
184  /*
185   *  initialize the CPU table for this BSP
186   */
187  Cpu_table.pretasking_hook = bsp_pretasking_hook;  /* init libc, etc. */
188  Cpu_table.postdriver_hook = bsp_postdriver_hook;
189  Cpu_table.do_zero_of_workspace = TRUE;
190  Cpu_table.interrupt_stack_size = 4096;
191
192  Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */
193
194    /*
195     * Invalidate the cache and disable it
196     */
197    m68k_set_acr0(0);
198    m68k_set_acr1(0);
199    m68k_set_cacr(MCF5XXX_CACR_CINV);
200
201    /*
202     * Cache SDRAM and FLASH
203     */
[0eff7b8]204    m68k_set_acr0(MCF5XXX_ACR_AB((uint32_t)_RamBase)     |
205                  MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
206                  MCF5XXX_ACR_EN                         |
207                  MCF5XXX_ACR_BWE                        |
[572484f]208                  MCF5XXX_ACR_SM_IGNORE);
[0eff7b8]209    m68k_set_acr1(MCF5XXX_ACR_AB((uint32_t)_FlashBase)   |
210                  MCF5XXX_ACR_AM((uint32_t)_FlashSize-1) |
211                  MCF5XXX_ACR_EN                         |
[572484f]212                  MCF5XXX_ACR_SM_IGNORE);
213
214    /*
215     * Enable the cache
216     */
217    m68k_set_cacr(cacr_mode);
218
219    /*
220     * Set up CS* space (fake 'VME')
221     *   Two A24/D16 spaces, supervisor data acces
222     */
223    MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE);
224    MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M |
225                       MCF5282_CS_CSMR_CI |
226                       MCF5282_CS_CSMR_SC |
227                       MCF5282_CS_CSMR_UC |
228                       MCF5282_CS_CSMR_UD |
229                       MCF5282_CS_CSMR_V;
230    MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16;
231    MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE);
232    MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M |
233                       MCF5282_CS_CSMR_CI |
234                       MCF5282_CS_CSMR_SC |
235                       MCF5282_CS_CSMR_UC |
236                       MCF5282_CS_CSMR_UD |
237                       MCF5282_CS_CSMR_V;
238    MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16;
239}
240
[0b2c943]241uint32_t bsp_get_CPU_clock_speed(void)
[572484f]242{
243    extern char _CPUClockSpeed[];
[0b2c943]244    return( (uint32_t)_CPUClockSpeed);
[572484f]245}
[7eab0f78]246
[5b6111b]247/*
248 * Interrupt controller allocation
249 */
[d75023e]250rtems_status_code
251bsp_allocate_interrupt(int level, int priority)
[5b6111b]252{
253    static char used[7];
254    rtems_interrupt_level l;
[d75023e]255    rtems_status_code ret = RTEMS_RESOURCE_IN_USE;
[5b6111b]256
257    if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7))
[d75023e]258        return RTEMS_INVALID_NUMBER;
[5b6111b]259    rtems_interrupt_disable(l);
260    if ((used[level-1] & (1 << priority)) == 0) {
261        used[level-1] |= (1 << priority);
[d75023e]262        ret = RTEMS_SUCCESSFUL;
[5b6111b]263    }
264    rtems_interrupt_enable(l);
265    return ret;
266}
267
[7eab0f78]268/*
[12993b3]269 * Arcturus bootloader system calls
[7eab0f78]270 */
[12993b3]271#define syscall_return(type, ret)                      \
272do {                                                   \
273   if ((unsigned long)(ret) >= (unsigned long)(-64)) { \
274      errno = -(ret);                                  \
275      ret = -1;                                        \
276   }                                                   \
277   return (type)(ret);                                 \
[7eab0f78]278} while (0)
[12993b3]279#define syscall_1(type,name,d1type,d1)                      \
280type uC5282_##name(d1type d1)                               \
281{                                                           \
282   long ret;                                                \
283   register long __d1 __asm__ ("%d1") = (long)d1;           \
284   __asm__ __volatile__ ("move.l %0,%%d0\n\t"               \
285                         "trap #2\n\t"                      \
286                         "move.l %%d0,%0"                   \
287                         : "=g" (ret)                       \
288                         : "d" (SysCode_##name), "d" (__d1) \
289                         : "d0" );                          \
290   syscall_return(type,ret);                                \
[7eab0f78]291}
[12993b3]292#define SysCode_gethwaddr    12 /* get hardware address */
293#define SysCode_getbenv      14 /* get bootloader environment variable */
294#define SysCode_setbenv      15 /* get bootloader environment variable */
295syscall_1(unsigned const char *, gethwaddr, int, a)
296syscall_1(const char *, getbenv, const char *, a)
[d75023e]297
298
299/*
300 * 'Extended BSP' routines
301 * Should move to cpukit/score/cpu/m68k/cpu.c someday.
302 */
303
304rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; }
305int BSP_enableVME_int_lvl(unsigned int level) { return 0; }
306int BSP_disableVME_int_lvl(unsigned int level) { return 0; }
307
308/*
309 * VME interrupt support
310 */
[a7e6bc96]311#define NVECTOR 256
312
[d75023e]313static struct handlerTab {
314    BSP_VME_ISR_t func;
315    void         *arg;
[a7e6bc96]316} handlerTab[NVECTOR];
[d75023e]317
318BSP_VME_ISR_t
319BSP_getVME_isr(unsigned long vector, void **pusrArg)
320{
[a7e6bc96]321    if (vector >= NVECTOR)
[d75023e]322        return (BSP_VME_ISR_t)NULL;
323    if (pusrArg)
324        *pusrArg = handlerTab[vector].arg;
325    return handlerTab[vector].func;
326}
327
328static rtems_isr
[a7e6bc96]329trampoline (rtems_vector_number v)
[d75023e]330{
[a7e6bc96]331    if (handlerTab[v].func)
[d75023e]332        (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v);
333}
334
335int
336BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
337{
338    rtems_isr_entry old_handler;
339
[a7e6bc96]340    if (vector >= NVECTOR)
[d75023e]341        return -1;
342    handlerTab[vector].func = handler;
343    handlerTab[vector].arg = usrArg;
[be129f69]344    rtems_interrupt_catch(trampoline, vector, &old_handler);
[d75023e]345
346    /*
[a7e6bc96]347     * Find an unused level/priority if this is an on-chip (INTC0)
348     * source and this is the first time the source is being used.
349     * Interrupt sources 1 through 7 are fixed level/priority
[d75023e]350     */
351    if ((vector >= 65) && (vector <= 127)) {
352        int l, p;
[a7e6bc96]353        int source = vector - 64;
[d75023e]354        rtems_interrupt_level level;
[a7e6bc96]355        static unsigned char installed[8];
[d75023e]356
[f3f4be7]357        rtems_interrupt_disable(level);
358        if (installed[source/8] & (1 << (source % 8))) {
359            rtems_interrupt_enable(level);
[a7e6bc96]360            return 0;
[f3f4be7]361        }
[a7e6bc96]362        installed[source/8] |= (1 << (source % 8));
[f3f4be7]363        rtems_interrupt_enable(level);
[d75023e]364        for (l = 1 ; l < 7 ; l++) {
365            for (p = 0 ; p < 7 ; p++) {
[a7e6bc96]366                if ((source < 8)
367                 || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) {
[8e712757]368                    if (source >= 8)
[a7e6bc96]369                        *(&MCF5282_INTC0_ICR1 + (source - 1)) =
[d75023e]370                                                       MCF5282_INTC_ICR_IL(l) |
371                                                       MCF5282_INTC_ICR_IP(p);
372                    rtems_interrupt_disable(level);
[a7e6bc96]373                    if (source >= 32)
374                        MCF5282_INTC0_IMRH &= ~(1 << (source - 32));
[d75023e]375                    else
[a7e6bc96]376                        MCF5282_INTC0_IMRL &= ~((1 << source) |
[d75023e]377                                                MCF5282_INTC_IMRL_MASKALL);
378                    rtems_interrupt_enable(level);
379                    return 0;
380                }
381            }
382        }
[a7e6bc96]383        return -1;
[d75023e]384    }
[a7e6bc96]385    return 0;
[d75023e]386}
387
388int
389BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg)
390{
[a7e6bc96]391    if (vector >= NVECTOR)
[d75023e]392        return -1;
393    if ((handlerTab[vector].func != handler)
394     || (handlerTab[vector].arg != usrArg))
395        return -1;
396    handlerTab[vector].func = (BSP_VME_ISR_t)NULL;
397    return 0;
398}
399
400int
401BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr)
402{
403    unsigned long offset;
404
405    switch (am) {
406    default:    return -1;
407    case VME_AM_SUP_SHORT_IO: offset = 0x31000000; break; /* A16/D16 */
408    case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */
409    case VME_AM_EXT_SUP_DATA: return -1;                  /* A32/D32 */
410    }
411    *plocaladdr = vmeaddr + offset;
412    return 0;
413}
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