[572484f] | 1 | /* |
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| 2 | * BSP startup |
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| 3 | * |
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| 4 | * This routine starts the application. It includes application, |
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| 5 | * board, and monitor specific initialization and configuration. |
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| 6 | * The generic CPU dependent initialization has been performed |
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| 7 | * before this routine is invoked. |
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| 8 | * |
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[12b36efe] | 9 | * Author: W. Eric Norum <norume@aps.anl.gov> |
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[572484f] | 10 | * |
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[12b36efe] | 11 | * COPYRIGHT (c) 2005. |
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[572484f] | 12 | * On-Line Applications Research Corporation (OAR). |
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| 13 | * |
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| 14 | * The license and distribution terms for this file may be |
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| 15 | * found in the file LICENSE in this distribution or at |
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[688696e4] | 16 | * http://www.rtems.com/license/LICENSE. |
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[572484f] | 17 | * |
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| 18 | * $Id$ |
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| 19 | */ |
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| 20 | |
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| 21 | #include <bsp.h> |
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[e846fc9] | 22 | #include <rtems/error.h> |
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[7eab0f78] | 23 | #include <errno.h> |
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[572484f] | 24 | |
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| 25 | /* |
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| 26 | * Location of 'VME' access |
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| 27 | */ |
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| 28 | #define VME_ONE_BASE 0x30000000 |
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| 29 | #define VME_TWO_BASE 0x31000000 |
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| 30 | |
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[18aa55ee] | 31 | /* |
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| 32 | * Linker Script Defined Variables |
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| 33 | */ |
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[4c5212e] | 34 | extern char RamSize[]; |
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| 35 | extern char RamBase[]; |
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[18aa55ee] | 36 | |
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[572484f] | 37 | /* |
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| 38 | * CPU-space access |
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[cbb615b] | 39 | * The NOP after writing the CACR is there to address the following issue as |
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| 40 | * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004: |
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| 41 | * |
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| 42 | * 6 Possible Cache Corruption after Setting CACR[CINV] |
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| 43 | * 6.1 Description |
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| 44 | * The cache on the MCF5282 was enhanced to function as a unified data and |
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| 45 | * instruction cache, an instruction cache, or an operand cache. The cache |
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| 46 | * function and organization is controlled by the cache control register (CACR). |
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| 47 | * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. |
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| 48 | * If the cache is configured as a unified cache and the CINV bit is set, the |
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| 49 | * scope of the cache clear is controlled by two other bits in the CACR, |
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| 50 | * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data |
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| 51 | * cache only). These bits allow the entire cache, just the instruction |
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| 52 | * portion of the cache, or just the data portion of the cache to be cleared. |
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| 53 | * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set) |
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| 54 | * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set), |
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| 55 | * then cache corruption may occur. |
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| 56 | * |
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| 57 | * 6.2 Workaround |
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| 58 | * All loads of the CACR that perform a cache clear operation (CINV = BIT 24) |
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| 59 | * should be followed immediately by a NOP instruction. This avoids the cache |
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| 60 | * corruption problem. |
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| 61 | * DATECODES AFFECTED: All |
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[572484f] | 62 | */ |
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[ac9bbe7] | 63 | #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) |
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| 64 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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[572484f] | 65 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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| 66 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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| 67 | |
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| 68 | /* |
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[d5fe91e] | 69 | * Read/write copy of cache registers |
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[ac9bbe7] | 70 | * Split instruction/data or instruction-only |
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[572484f] | 71 | * Allow CPUSHL to invalidate a cache line |
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| 72 | * Enable buffered writes |
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| 73 | * No burst transfers on non-cacheable accesses |
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| 74 | * Default cache mode is *disabled* (cache only ACRx areas) |
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| 75 | */ |
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[d5fe91e] | 76 | uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | |
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[ac9bbe7] | 77 | #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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| 78 | MCF5XXX_CACR_DISD | |
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| 79 | #endif |
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[d5fe91e] | 80 | MCF5XXX_CACR_DBWE | |
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| 81 | MCF5XXX_CACR_DCM; |
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| 82 | uint32_t mcf5282_acr0_mode = 0; |
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| 83 | uint32_t mcf5282_acr1_mode = 0; |
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[572484f] | 84 | /* |
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| 85 | * Cannot be frozen |
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| 86 | */ |
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| 87 | void _CPU_cache_freeze_data(void) {} |
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| 88 | void _CPU_cache_unfreeze_data(void) {} |
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| 89 | void _CPU_cache_freeze_instruction(void) {} |
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| 90 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 91 | |
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| 92 | /* |
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| 93 | * Write-through data cache -- flushes are unnecessary |
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| 94 | */ |
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| 95 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 96 | void _CPU_cache_flush_entire_data(void) {} |
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| 97 | |
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| 98 | void _CPU_cache_enable_instruction(void) |
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| 99 | { |
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| 100 | rtems_interrupt_level level; |
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| 101 | |
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| 102 | rtems_interrupt_disable(level); |
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[d5fe91e] | 103 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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| 104 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 105 | rtems_interrupt_enable(level); |
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| 106 | } |
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| 107 | |
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| 108 | void _CPU_cache_disable_instruction(void) |
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| 109 | { |
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| 110 | rtems_interrupt_level level; |
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| 111 | |
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| 112 | rtems_interrupt_disable(level); |
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[d5fe91e] | 113 | mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI; |
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| 114 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 115 | rtems_interrupt_enable(level); |
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| 116 | } |
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| 117 | |
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| 118 | void _CPU_cache_invalidate_entire_instruction(void) |
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| 119 | { |
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[ac9bbe7] | 120 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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[572484f] | 121 | } |
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| 122 | |
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| 123 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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| 124 | { |
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[518edef] | 125 | /* |
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| 126 | * Top half of cache is I-space |
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| 127 | */ |
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| 128 | addr = (void *)((int)addr | 0x400); |
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| 129 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[572484f] | 130 | } |
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| 131 | |
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| 132 | void _CPU_cache_enable_data(void) |
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| 133 | { |
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[ac9bbe7] | 134 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[572484f] | 135 | rtems_interrupt_level level; |
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| 136 | |
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| 137 | rtems_interrupt_disable(level); |
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[ac9bbe7] | 138 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB; |
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[d5fe91e] | 139 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 140 | rtems_interrupt_enable(level); |
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[ac9bbe7] | 141 | #endif |
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[572484f] | 142 | } |
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| 143 | |
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| 144 | void _CPU_cache_disable_data(void) |
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| 145 | { |
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[ac9bbe7] | 146 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[572484f] | 147 | rtems_interrupt_level level; |
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| 148 | |
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[518edef] | 149 | rtems_interrupt_disable(level); |
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[572484f] | 150 | rtems_interrupt_disable(level); |
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[ac9bbe7] | 151 | mcf5282_cacr_mode |= MCF5XXX_CACR_CENB; |
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[d5fe91e] | 152 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 153 | rtems_interrupt_enable(level); |
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[ac9bbe7] | 154 | #endif |
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[572484f] | 155 | } |
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| 156 | |
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| 157 | void _CPU_cache_invalidate_entire_data(void) |
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| 158 | { |
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[ac9bbe7] | 159 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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| 160 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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| 161 | #endif |
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[572484f] | 162 | } |
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| 163 | |
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| 164 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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| 165 | { |
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[ac9bbe7] | 166 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[518edef] | 167 | /* |
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| 168 | * Bottom half of cache is D-space |
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| 169 | */ |
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| 170 | addr = (void *)((int)addr & ~0x400); |
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| 171 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[ac9bbe7] | 172 | #endif |
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[572484f] | 173 | } |
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| 174 | |
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[e846fc9] | 175 | /* |
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| 176 | * The Arcturus boot ROM prints exception information improperly |
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| 177 | * so use this default exception handler instead. This one also |
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| 178 | * prints a call backtrace |
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| 179 | */ |
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| 180 | static void handler(int pc) |
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| 181 | { |
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| 182 | int level; |
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| 183 | static volatile int reent; |
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| 184 | |
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| 185 | rtems_interrupt_disable(level); |
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| 186 | if (reent++) bsp_reset(0); |
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| 187 | { |
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| 188 | int *p = &pc; |
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| 189 | int info = p[-1]; |
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| 190 | int pc = p[0]; |
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| 191 | int format = (info >> 28) & 0xF; |
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| 192 | int faultStatus = ((info >> 24) & 0xC) | ((info >> 16) & 0x3); |
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| 193 | int vector = (info >> 18) & 0xFF; |
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| 194 | int statusRegister = info & 0xFFFF; |
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| 195 | int *fp; |
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| 196 | |
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| 197 | printk("\n\nPC:%x SR:%x VEC:%x FORMAT:%x STATUS:%x\n", pc, |
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| 198 | statusRegister, |
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| 199 | vector, |
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| 200 | format, |
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| 201 | faultStatus); |
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| 202 | fp = &p[-2]; |
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| 203 | for(;;) { |
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| 204 | int *nfp = (int *)*fp; |
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| 205 | if ((nfp <= fp) |
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[4c5212e] | 206 | || ((char *)nfp >= RamSize) |
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| 207 | || ((char *)(nfp[1]) >= RamSize)) |
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[e846fc9] | 208 | break; |
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| 209 | printk("FP:%x -> %x PC:%x\n", fp, nfp, nfp[1]); |
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| 210 | fp = nfp; |
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| 211 | } |
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| 212 | } |
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| 213 | rtems_task_suspend(0); |
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| 214 | rtems_panic("done"); |
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| 215 | } |
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| 216 | |
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[572484f] | 217 | /* |
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| 218 | * bsp_start |
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| 219 | * |
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| 220 | * This routine does the bulk of the system initialisation. |
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| 221 | */ |
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| 222 | void bsp_start( void ) |
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| 223 | { |
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[e846fc9] | 224 | int i; |
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[b5b9e75] | 225 | |
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| 226 | /* |
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[18aa55ee] | 227 | * Set up default exception handler |
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[b5b9e75] | 228 | */ |
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[18aa55ee] | 229 | for (i = 2 ; i < 256 ; i++) |
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| 230 | if (i != (32+2)) /* Catch all but bootrom system calls */ |
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| 231 | *((void (**)(int))(i * 4)) = handler; |
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[572484f] | 232 | |
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[1693c131] | 233 | /* |
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| 234 | * Invalidate the cache and disable it |
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| 235 | */ |
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| 236 | m68k_set_acr0(mcf5282_acr0_mode); |
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| 237 | m68k_set_acr1(mcf5282_acr1_mode); |
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| 238 | m68k_set_cacr_nop(MCF5XXX_CACR_CINV); |
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[572484f] | 239 | |
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[1693c131] | 240 | /* |
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| 241 | * Cache SDRAM |
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| 242 | */ |
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[4c5212e] | 243 | mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)RamBase) | |
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| 244 | MCF5XXX_ACR_AM((uint32_t)RamSize-1) | |
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[1693c131] | 245 | MCF5XXX_ACR_EN | |
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| 246 | MCF5XXX_ACR_BWE | |
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| 247 | MCF5XXX_ACR_SM_IGNORE; |
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| 248 | m68k_set_acr0(mcf5282_acr0_mode); |
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[572484f] | 249 | |
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[1693c131] | 250 | /* |
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| 251 | * Enable the cache |
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| 252 | */ |
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| 253 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 254 | |
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[1693c131] | 255 | /* |
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| 256 | * Set up CS* space (fake 'VME') |
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| 257 | * Two A24/D16 spaces, supervisor data acces |
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| 258 | */ |
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| 259 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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| 260 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 261 | MCF5282_CS_CSMR_CI | |
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| 262 | MCF5282_CS_CSMR_SC | |
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| 263 | MCF5282_CS_CSMR_UC | |
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| 264 | MCF5282_CS_CSMR_UD | |
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| 265 | MCF5282_CS_CSMR_V; |
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| 266 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 267 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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| 268 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 269 | MCF5282_CS_CSMR_CI | |
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| 270 | MCF5282_CS_CSMR_SC | |
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| 271 | MCF5282_CS_CSMR_UC | |
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| 272 | MCF5282_CS_CSMR_UD | |
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| 273 | MCF5282_CS_CSMR_V; |
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| 274 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 275 | MCF5282_GPIO_PJPAR |= 0x06; |
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[572484f] | 276 | } |
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| 277 | |
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[18aa55ee] | 278 | extern char _CPUClockSpeed[]; |
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| 279 | |
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[0b2c943] | 280 | uint32_t bsp_get_CPU_clock_speed(void) |
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[572484f] | 281 | { |
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[1693c131] | 282 | return( (uint32_t)_CPUClockSpeed); |
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[572484f] | 283 | } |
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[7eab0f78] | 284 | |
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[5b6111b] | 285 | /* |
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| 286 | * Interrupt controller allocation |
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| 287 | */ |
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[d75023e] | 288 | rtems_status_code |
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| 289 | bsp_allocate_interrupt(int level, int priority) |
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[5b6111b] | 290 | { |
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[1693c131] | 291 | static char used[7]; |
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| 292 | rtems_interrupt_level l; |
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| 293 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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| 294 | |
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| 295 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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| 296 | return RTEMS_INVALID_NUMBER; |
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| 297 | rtems_interrupt_disable(l); |
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| 298 | if ((used[level-1] & (1 << priority)) == 0) { |
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| 299 | used[level-1] |= (1 << priority); |
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| 300 | ret = RTEMS_SUCCESSFUL; |
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| 301 | } |
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| 302 | rtems_interrupt_enable(l); |
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| 303 | return ret; |
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[5b6111b] | 304 | } |
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| 305 | |
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[7eab0f78] | 306 | /* |
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[12993b3] | 307 | * Arcturus bootloader system calls |
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[7eab0f78] | 308 | */ |
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[12993b3] | 309 | #define syscall_return(type, ret) \ |
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| 310 | do { \ |
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| 311 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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| 312 | errno = -(ret); \ |
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| 313 | ret = -1; \ |
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| 314 | } \ |
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| 315 | return (type)(ret); \ |
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[7eab0f78] | 316 | } while (0) |
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[1693c131] | 317 | |
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[12993b3] | 318 | #define syscall_1(type,name,d1type,d1) \ |
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[8af3643] | 319 | type bsp_##name(d1type d1) \ |
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[12993b3] | 320 | { \ |
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| 321 | long ret; \ |
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| 322 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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[16ae480] | 323 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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[12993b3] | 324 | "trap #2\n\t" \ |
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| 325 | "move.l %%d0,%0" \ |
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| 326 | : "=g" (ret) \ |
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[8af3643] | 327 | : "i" (SysCode_##name), "d" (__d1) \ |
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[12993b3] | 328 | : "d0" ); \ |
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| 329 | syscall_return(type,ret); \ |
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[7eab0f78] | 330 | } |
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[1693c131] | 331 | |
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[16ae480] | 332 | #define syscall_2(type,name,d1type,d1,d2type,d2) \ |
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[8af3643] | 333 | type bsp_##name(d1type d1, d2type d2) \ |
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[16ae480] | 334 | { \ |
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| 335 | long ret; \ |
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| 336 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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| 337 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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| 338 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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| 339 | "trap #2\n\t" \ |
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| 340 | "move.l %%d0,%0" \ |
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| 341 | : "=g" (ret) \ |
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[8af3643] | 342 | : "i" (SysCode_##name), "d" (__d1),\ |
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[16ae480] | 343 | "d" (__d2) \ |
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| 344 | : "d0" ); \ |
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| 345 | syscall_return(type,ret); \ |
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| 346 | } |
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[1693c131] | 347 | |
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[8af3643] | 348 | #define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \ |
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| 349 | type bsp_##name(d1type d1, d2type d2, d3type d3) \ |
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| 350 | { \ |
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| 351 | long ret; \ |
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| 352 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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| 353 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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| 354 | register long __d3 __asm__ ("%d3") = (long)d3; \ |
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| 355 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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| 356 | "trap #2\n\t" \ |
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| 357 | "move.l %%d0,%0" \ |
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| 358 | : "=g" (ret) \ |
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| 359 | : "i" (SysCode_##name), "d" (__d1),\ |
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| 360 | "d" (__d2),\ |
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| 361 | "d" (__d3) \ |
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| 362 | : "d0" ); \ |
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| 363 | syscall_return(type,ret); \ |
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| 364 | } |
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[1693c131] | 365 | |
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[8af3643] | 366 | #define SysCode_reset 0 /* reset */ |
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| 367 | #define SysCode_program 5 /* program flash memory */ |
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| 368 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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| 369 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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[167818a] | 370 | #define SysCode_setbenv 15 /* set bootloader environment variable */ |
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[8af3643] | 371 | #define SysCode_flash_erase_range 19 /* erase a section of flash */ |
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| 372 | #define SysCode_flash_write_range 20 /* write a section of flash */ |
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[b7115915] | 373 | syscall_1(int, reset, int, flags) |
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[12993b3] | 374 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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| 375 | syscall_1(const char *, getbenv, const char *, a) |
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[167818a] | 376 | syscall_1(int, setbenv, const char *, a) |
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[16ae480] | 377 | syscall_2(int, program, bsp_mnode_t *, chain, int, flags) |
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[8af3643] | 378 | syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end); |
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| 379 | syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset); |
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[d75023e] | 380 | |
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| 381 | /* |
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| 382 | * 'Extended BSP' routines |
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| 383 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
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| 384 | */ |
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| 385 | |
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| 386 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
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| 387 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
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| 388 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
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| 389 | |
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| 390 | /* |
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[a81e4f1] | 391 | * 'VME' interrupt support |
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[402f4df] | 392 | * Interrupt vectors 192-255 are set aside for use by external logic which |
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| 393 | * drives IRQ1*. The actual interrupt source is read from the external |
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| 394 | * logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant |
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| 395 | * byte read from this location is set as long as the external logic has |
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| 396 | * interrupts to be serviced. The least-significant six bits indicate the |
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| 397 | * interrupt source within the external logic and are used to select the |
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| 398 | * specified interupt handler. |
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[d75023e] | 399 | */ |
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[a7e6bc96] | 400 | #define NVECTOR 256 |
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[a81e4f1] | 401 | #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ |
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| 402 | #define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe)) |
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[a7e6bc96] | 403 | |
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[d75023e] | 404 | static struct handlerTab { |
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[1693c131] | 405 | BSP_VME_ISR_t func; |
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| 406 | void *arg; |
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[a7e6bc96] | 407 | } handlerTab[NVECTOR]; |
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[d75023e] | 408 | |
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| 409 | BSP_VME_ISR_t |
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| 410 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
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| 411 | { |
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[1693c131] | 412 | if (vector >= NVECTOR) |
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| 413 | return (BSP_VME_ISR_t)NULL; |
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| 414 | if (pusrArg) |
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| 415 | *pusrArg = handlerTab[vector].arg; |
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| 416 | return handlerTab[vector].func; |
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[d75023e] | 417 | } |
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| 418 | |
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[215e019] | 419 | static rtems_isr |
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| 420 | fpga_trampoline (rtems_vector_number v) |
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| 421 | { |
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[1693c131] | 422 | /* |
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| 423 | * Handle FPGA interrupts until all have been consumed |
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| 424 | */ |
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| 425 | int loopcount = 0; |
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| 426 | while (((v = FPGA_IRQ_INFO) & 0x80) != 0) { |
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| 427 | v = 192 + (v & 0x3f); |
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| 428 | if (++loopcount >= 50) { |
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| 429 | rtems_interrupt_level level; |
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| 430 | rtems_interrupt_disable(level); |
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| 431 | printk("\nTOO MANY FPGA INTERRUPTS (LAST WAS 0x%x) -- DISABLING ALL FPGA INTERRUPTS.\n", v & 0x3f); |
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| 432 | MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1; |
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| 433 | rtems_interrupt_enable(level); |
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| 434 | return; |
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| 435 | } |
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| 436 | if (handlerTab[v].func) { |
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| 437 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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| 438 | } |
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| 439 | else { |
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| 440 | rtems_interrupt_level level; |
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| 441 | rtems_vector_number nv; |
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| 442 | rtems_interrupt_disable(level); |
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| 443 | printk("\nSPURIOUS FPGA INTERRUPT (0x%x).\n", v & 0x3f); |
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| 444 | if ((((nv = FPGA_IRQ_INFO) & 0x80) != 0) |
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| 445 | && ((nv & 0x3f) == (v & 0x3f))) { |
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| 446 | printk("DISABLING ALL FPGA INTERRUPTS.\n"); |
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| 447 | MCF5282_INTC0_IMRL |= MCF5282_INTC_IMRL_INT1; |
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| 448 | } |
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| 449 | rtems_interrupt_enable(level); |
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| 450 | return; |
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| 451 | } |
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| 452 | } |
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[215e019] | 453 | } |
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| 454 | |
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[d75023e] | 455 | static rtems_isr |
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[a7e6bc96] | 456 | trampoline (rtems_vector_number v) |
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[d75023e] | 457 | { |
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[215e019] | 458 | if (handlerTab[v].func) |
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| 459 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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| 460 | } |
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| 461 | |
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| 462 | static void |
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| 463 | enable_irq(unsigned source) |
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| 464 | { |
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| 465 | rtems_interrupt_level level; |
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[1693c131] | 466 | rtems_interrupt_disable(level); |
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| 467 | if (source >= 32) |
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| 468 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
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| 469 | else |
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| 470 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
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| 471 | MCF5282_INTC_IMRL_MASKALL); |
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| 472 | rtems_interrupt_enable(level); |
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[215e019] | 473 | } |
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| 474 | |
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| 475 | static void |
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| 476 | disable_irq(unsigned source) |
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| 477 | { |
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| 478 | rtems_interrupt_level level; |
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| 479 | |
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[1693c131] | 480 | rtems_interrupt_disable(level); |
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| 481 | if (source >= 32) |
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| 482 | MCF5282_INTC0_IMRH |= (1 << (source - 32)); |
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| 483 | else |
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| 484 | MCF5282_INTC0_IMRL |= (1 << source); |
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| 485 | rtems_interrupt_enable(level); |
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[215e019] | 486 | } |
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| 487 | |
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| 488 | void |
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| 489 | BSP_enable_irq_at_pic(rtems_vector_number v) |
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| 490 | { |
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| 491 | int source = v - 64; |
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| 492 | |
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[1693c131] | 493 | if ( source > 0 && source < 64 ) { |
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| 494 | enable_irq(source); |
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| 495 | } |
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[215e019] | 496 | } |
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| 497 | |
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| 498 | void |
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| 499 | BSP_disable_irq_at_pic(rtems_vector_number v) |
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| 500 | { |
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| 501 | int source = v - 64; |
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| 502 | |
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[1693c131] | 503 | if ( source > 0 && source < 64 ) { |
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| 504 | disable_irq(source); |
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| 505 | } |
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[215e019] | 506 | } |
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| 507 | |
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| 508 | int |
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| 509 | BSP_irq_is_enabled_at_pic(rtems_vector_number v) |
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| 510 | { |
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| 511 | int source = v - 64; |
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| 512 | |
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[1693c131] | 513 | if ( source > 0 && source < 64 ) { |
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| 514 | return ! ((source >= 32) ? |
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| 515 | MCF5282_INTC0_IMRH & (1 << (source - 32)) : |
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| 516 | MCF5282_INTC0_IMRL & (1 << source)); |
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| 517 | } |
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| 518 | return -1; |
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[215e019] | 519 | } |
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| 520 | |
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| 521 | |
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| 522 | static int |
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| 523 | init_intc0_bit(unsigned long vector) |
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| 524 | { |
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| 525 | rtems_interrupt_level level; |
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| 526 | |
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[a81e4f1] | 527 | /* |
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[215e019] | 528 | * Find an unused level/priority if this is an on-chip (INTC0) |
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| 529 | * source and this is the first time the source is being used. |
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| 530 | * Interrupt sources 1 through 7 are fixed level/priority |
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[a81e4f1] | 531 | */ |
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[215e019] | 532 | |
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| 533 | if ((vector >= 65) && (vector <= 127)) { |
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| 534 | int l, p; |
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| 535 | int source = vector - 64; |
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| 536 | static unsigned char installed[8]; |
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| 537 | |
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| 538 | rtems_interrupt_disable(level); |
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| 539 | if (installed[source/8] & (1 << (source % 8))) { |
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| 540 | rtems_interrupt_enable(level); |
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| 541 | return 0; |
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| 542 | } |
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| 543 | installed[source/8] |= (1 << (source % 8)); |
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| 544 | rtems_interrupt_enable(level); |
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| 545 | for (l = 1 ; l < 7 ; l++) { |
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| 546 | for (p = 0 ; p < 8 ; p++) { |
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| 547 | if ((source < 8) |
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| 548 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
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[9797991] | 549 | if (source < 8) |
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| 550 | MCF5282_EPORT_EPIER |= 1 << source; |
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| 551 | else |
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[215e019] | 552 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
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| 553 | MCF5282_INTC_ICR_IL(l) | |
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| 554 | MCF5282_INTC_ICR_IP(p); |
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[1693c131] | 555 | enable_irq(source); |
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[215e019] | 556 | return 0; |
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[8a742dd] | 557 | } |
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[a7edc92] | 558 | } |
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[a81e4f1] | 559 | } |
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[215e019] | 560 | return -1; |
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[a81e4f1] | 561 | } |
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[1693c131] | 562 | return 0; |
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[d75023e] | 563 | } |
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| 564 | |
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| 565 | int |
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| 566 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 567 | { |
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[1693c131] | 568 | rtems_isr_entry old_handler; |
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| 569 | rtems_interrupt_level level; |
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[d75023e] | 570 | |
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[1693c131] | 571 | /* |
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| 572 | * Register the handler information |
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| 573 | */ |
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| 574 | if (vector >= NVECTOR) |
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| 575 | return -1; |
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| 576 | handlerTab[vector].func = handler; |
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| 577 | handlerTab[vector].arg = usrArg; |
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[a81e4f1] | 578 | |
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[1693c131] | 579 | /* |
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| 580 | * If this is an external FPGA ('VME') vector set up the real IRQ. |
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| 581 | */ |
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| 582 | if ((vector >= 192) && (vector <= 255)) { |
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| 583 | int i; |
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| 584 | static volatile int setupDone; |
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| 585 | rtems_interrupt_disable(level); |
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| 586 | if (setupDone) { |
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| 587 | rtems_interrupt_enable(level); |
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| 588 | return 0; |
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[a81e4f1] | 589 | } |
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[7decb66] | 590 | setupDone = 1; |
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[1693c131] | 591 | rtems_interrupt_catch(fpga_trampoline, FPGA_VECTOR, &old_handler); |
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| 592 | i = init_intc0_bit(FPGA_VECTOR); |
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| 593 | rtems_interrupt_enable(level); |
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| 594 | return i; |
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| 595 | } |
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[a81e4f1] | 596 | |
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[1693c131] | 597 | /* |
---|
| 598 | * Make the connection between the interrupt and the local handler |
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| 599 | */ |
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| 600 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
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[d75023e] | 601 | |
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[1693c131] | 602 | return init_intc0_bit(vector); |
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[d75023e] | 603 | } |
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| 604 | |
---|
| 605 | int |
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| 606 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 607 | { |
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[1693c131] | 608 | if (vector >= NVECTOR) |
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| 609 | return -1; |
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| 610 | if ((handlerTab[vector].func != handler) |
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[d75023e] | 611 | || (handlerTab[vector].arg != usrArg)) |
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[1693c131] | 612 | return -1; |
---|
| 613 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
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| 614 | return 0; |
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[d75023e] | 615 | } |
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| 616 | |
---|
| 617 | int |
---|
| 618 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
---|
| 619 | { |
---|
[1693c131] | 620 | unsigned long offset; |
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[d75023e] | 621 | |
---|
[1693c131] | 622 | switch (am) { |
---|
[d75023e] | 623 | default: return -1; |
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[008c4b5] | 624 | case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */ |
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[d75023e] | 625 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
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[008c4b5] | 626 | case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */ |
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[1693c131] | 627 | } |
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| 628 | *plocaladdr = vmeaddr + offset; |
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| 629 | return 0; |
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[d75023e] | 630 | } |
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[91cb065] | 631 | |
---|
| 632 | void |
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| 633 | rtems_bsp_reset_cause(char *buf, size_t capacity) |
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| 634 | { |
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[1693c131] | 635 | int bit, rsr; |
---|
| 636 | size_t i; |
---|
| 637 | const char *cp; |
---|
[91cb065] | 638 | |
---|
[1693c131] | 639 | if (buf == NULL) |
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| 640 | return; |
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| 641 | if (capacity) |
---|
| 642 | buf[0] = '\0'; |
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| 643 | rsr = MCF5282_RESET_RSR; |
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| 644 | for (i = 0, bit = 0x80 ; bit != 0 ; bit >>= 1) { |
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| 645 | if (rsr & bit) { |
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| 646 | switch (bit) { |
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| 647 | case MCF5282_RESET_RSR_LVD: cp = "Low voltage"; break; |
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| 648 | case MCF5282_RESET_RSR_SOFT: cp = "Software reset"; break; |
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| 649 | case MCF5282_RESET_RSR_WDR: cp = "Watchdog reset"; break; |
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| 650 | case MCF5282_RESET_RSR_POR: cp = "Power-on reset"; break; |
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| 651 | case MCF5282_RESET_RSR_EXT: cp = "External reset"; break; |
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| 652 | case MCF5282_RESET_RSR_LOC: cp = "Loss of clock"; break; |
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| 653 | case MCF5282_RESET_RSR_LOL: cp = "Loss of lock"; break; |
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| 654 | default: cp = "??"; break; |
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| 655 | } |
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| 656 | i += snprintf(buf+i, capacity-i, cp); |
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| 657 | if (i >= capacity) |
---|
| 658 | break; |
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| 659 | rsr &= ~bit; |
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| 660 | if (rsr == 0) |
---|
| 661 | break; |
---|
| 662 | i += snprintf(buf+i, capacity-i, ", "); |
---|
| 663 | if (i >= capacity) |
---|
| 664 | break; |
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[91cb065] | 665 | } |
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[1693c131] | 666 | } |
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[91cb065] | 667 | } |
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