[572484f] | 1 | /* |
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| 2 | * BSP startup |
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| 3 | * |
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| 4 | * This routine starts the application. It includes application, |
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| 5 | * board, and monitor specific initialization and configuration. |
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| 6 | * The generic CPU dependent initialization has been performed |
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| 7 | * before this routine is invoked. |
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| 8 | * |
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| 9 | * Author: |
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| 10 | * David Fiddes, D.J@fiddes.surfaid.org |
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| 11 | * http://www.calm.hw.ac.uk/davidf/coldfire/ |
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| 12 | * |
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| 13 | * COPYRIGHT (c) 1989-1998. |
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| 14 | * On-Line Applications Research Corporation (OAR). |
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| 15 | * Copyright assigned to U.S. Government, 1994. |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * |
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| 20 | * http://www.OARcorp.com/rtems/license.html. |
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| 21 | * |
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| 22 | * $Id$ |
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| 23 | */ |
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| 24 | |
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| 25 | #include <bsp.h> |
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| 26 | #include <rtems/libio.h> |
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| 27 | #include <rtems/libcsupport.h> |
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| 28 | #include <string.h> |
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[7eab0f78] | 29 | #include <errno.h> |
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[572484f] | 30 | |
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| 31 | /* |
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| 32 | * The original table from the application and our copy of it with |
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| 33 | * some changes. |
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| 34 | */ |
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| 35 | extern rtems_configuration_table Configuration; |
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| 36 | rtems_configuration_table BSP_Configuration; |
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| 37 | rtems_cpu_table Cpu_table; |
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| 38 | char *rtems_progname; |
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| 39 | |
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| 40 | /* |
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| 41 | * Location of 'VME' access |
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| 42 | */ |
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| 43 | #define VME_ONE_BASE 0x30000000 |
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| 44 | #define VME_TWO_BASE 0x31000000 |
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| 45 | |
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| 46 | /* |
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| 47 | * CPU-space access |
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[cbb615b] | 48 | * The NOP after writing the CACR is there to address the following issue as |
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| 49 | * described in "Device Errata MCF5282DE", Rev. 1.7, 09/2004: |
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| 50 | * |
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| 51 | * 6 Possible Cache Corruption after Setting CACR[CINV] |
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| 52 | * 6.1 Description |
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| 53 | * The cache on the MCF5282 was enhanced to function as a unified data and |
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| 54 | * instruction cache, an instruction cache, or an operand cache. The cache |
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| 55 | * function and organization is controlled by the cache control register (CACR). |
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| 56 | * The CINV (Bit 24 = cache invalidate) bit in the CACR causes a cache clear. |
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| 57 | * If the cache is configured as a unified cache and the CINV bit is set, the |
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| 58 | * scope of the cache clear is controlled by two other bits in the CACR, |
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| 59 | * INVI (BIT 21 = CINV instruction cache only) and INVD (BIT 20 = CINV data |
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| 60 | * cache only). These bits allow the entire cache, just the instruction |
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| 61 | * portion of the cache, or just the data portion of the cache to be cleared. |
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| 62 | * If a write to the CACR is performed to clear the cache (CINV = BIT 24 set) |
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| 63 | * and only a partial clear will be done (INVI = BIT 21 or INVD = BIT 20 set), |
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| 64 | * then cache corruption may occur. |
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| 65 | * |
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| 66 | * 6.2 Workaround |
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| 67 | * All loads of the CACR that perform a cache clear operation (CINV = BIT 24) |
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| 68 | * should be followed immediately by a NOP instruction. This avoids the cache |
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| 69 | * corruption problem. |
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| 70 | * DATECODES AFFECTED: All |
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[572484f] | 71 | */ |
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[ac9bbe7] | 72 | #define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr)) |
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| 73 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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[572484f] | 74 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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| 75 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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| 76 | |
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| 77 | /* |
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[d5fe91e] | 78 | * Read/write copy of cache registers |
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[ac9bbe7] | 79 | * Split instruction/data or instruction-only |
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[572484f] | 80 | * Allow CPUSHL to invalidate a cache line |
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| 81 | * Enable buffered writes |
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| 82 | * No burst transfers on non-cacheable accesses |
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| 83 | * Default cache mode is *disabled* (cache only ACRx areas) |
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| 84 | */ |
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[d5fe91e] | 85 | uint32_t mcf5282_cacr_mode = MCF5XXX_CACR_CENB | |
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[ac9bbe7] | 86 | #ifndef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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| 87 | MCF5XXX_CACR_DISD | |
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| 88 | #endif |
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[d5fe91e] | 89 | MCF5XXX_CACR_DBWE | |
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| 90 | MCF5XXX_CACR_DCM; |
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| 91 | uint32_t mcf5282_acr0_mode = 0; |
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| 92 | uint32_t mcf5282_acr1_mode = 0; |
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[572484f] | 93 | /* |
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| 94 | * Cannot be frozen |
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| 95 | */ |
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| 96 | void _CPU_cache_freeze_data(void) {} |
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| 97 | void _CPU_cache_unfreeze_data(void) {} |
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| 98 | void _CPU_cache_freeze_instruction(void) {} |
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| 99 | void _CPU_cache_unfreeze_instruction(void) {} |
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| 100 | |
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| 101 | /* |
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| 102 | * Write-through data cache -- flushes are unnecessary |
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| 103 | */ |
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| 104 | void _CPU_cache_flush_1_data_line(const void *d_addr) {} |
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| 105 | void _CPU_cache_flush_entire_data(void) {} |
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| 106 | |
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| 107 | void _CPU_cache_enable_instruction(void) |
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| 108 | { |
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| 109 | rtems_interrupt_level level; |
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| 110 | |
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| 111 | rtems_interrupt_disable(level); |
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[d5fe91e] | 112 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_DIDI; |
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| 113 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 114 | rtems_interrupt_enable(level); |
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| 115 | } |
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| 116 | |
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| 117 | void _CPU_cache_disable_instruction(void) |
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| 118 | { |
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| 119 | rtems_interrupt_level level; |
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| 120 | |
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| 121 | rtems_interrupt_disable(level); |
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[d5fe91e] | 122 | mcf5282_cacr_mode |= MCF5XXX_CACR_DIDI; |
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| 123 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 124 | rtems_interrupt_enable(level); |
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| 125 | } |
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| 126 | |
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| 127 | void _CPU_cache_invalidate_entire_instruction(void) |
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| 128 | { |
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[ac9bbe7] | 129 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVI); |
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[572484f] | 130 | } |
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| 131 | |
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| 132 | void _CPU_cache_invalidate_1_instruction_line(const void *addr) |
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| 133 | { |
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[518edef] | 134 | /* |
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| 135 | * Top half of cache is I-space |
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| 136 | */ |
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| 137 | addr = (void *)((int)addr | 0x400); |
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| 138 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[572484f] | 139 | } |
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| 140 | |
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| 141 | void _CPU_cache_enable_data(void) |
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| 142 | { |
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[ac9bbe7] | 143 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[572484f] | 144 | rtems_interrupt_level level; |
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| 145 | |
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| 146 | rtems_interrupt_disable(level); |
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[ac9bbe7] | 147 | mcf5282_cacr_mode &= ~MCF5XXX_CACR_CENB; |
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[d5fe91e] | 148 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 149 | rtems_interrupt_enable(level); |
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[ac9bbe7] | 150 | #endif |
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[572484f] | 151 | } |
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| 152 | |
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| 153 | void _CPU_cache_disable_data(void) |
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| 154 | { |
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[ac9bbe7] | 155 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[572484f] | 156 | rtems_interrupt_level level; |
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| 157 | |
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[518edef] | 158 | rtems_interrupt_disable(level); |
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[572484f] | 159 | rtems_interrupt_disable(level); |
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[ac9bbe7] | 160 | mcf5282_cacr_mode |= MCF5XXX_CACR_CENB; |
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[d5fe91e] | 161 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 162 | rtems_interrupt_enable(level); |
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[ac9bbe7] | 163 | #endif |
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[572484f] | 164 | } |
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| 165 | |
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| 166 | void _CPU_cache_invalidate_entire_data(void) |
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| 167 | { |
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[ac9bbe7] | 168 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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| 169 | m68k_set_cacr_nop(mcf5282_cacr_mode | MCF5XXX_CACR_CINV | MCF5XXX_CACR_INVD); |
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| 170 | #endif |
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[572484f] | 171 | } |
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| 172 | |
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| 173 | void _CPU_cache_invalidate_1_data_line(const void *addr) |
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| 174 | { |
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[ac9bbe7] | 175 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
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[518edef] | 176 | /* |
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| 177 | * Bottom half of cache is D-space |
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| 178 | */ |
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| 179 | addr = (void *)((int)addr & ~0x400); |
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| 180 | asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); |
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[ac9bbe7] | 181 | #endif |
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[572484f] | 182 | } |
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| 183 | |
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| 184 | /* |
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| 185 | * Use the shared implementations of the following routines |
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| 186 | */ |
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| 187 | void bsp_postdriver_hook(void); |
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[0b2c943] | 188 | void bsp_libc_init( void *, uint32_t, int ); |
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[d75023e] | 189 | void bsp_pretasking_hook(void); /* m68k version */ |
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[572484f] | 190 | |
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| 191 | /* |
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| 192 | * bsp_start |
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| 193 | * |
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| 194 | * This routine does the bulk of the system initialisation. |
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| 195 | */ |
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| 196 | void bsp_start( void ) |
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| 197 | { |
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| 198 | extern char _WorkspaceBase[]; |
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[0eff7b8] | 199 | extern char _RamBase[], _RamSize[]; |
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[572484f] | 200 | extern unsigned long _M68k_Ramsize; |
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| 201 | |
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[d75023e] | 202 | _M68k_Ramsize = (unsigned long)_RamSize; /* RAM size set in linker script */ |
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[572484f] | 203 | |
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| 204 | /* |
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| 205 | * Allocate the memory for the RTEMS Work Space. This can come from |
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| 206 | * a variety of places: hard coded address, malloc'ed from outside |
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| 207 | * RTEMS world (e.g. simulator or primitive memory manager), or (as |
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| 208 | * typically done by stock BSPs) by subtracting the required amount |
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| 209 | * of work space from the last physical address on the CPU board. |
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| 210 | */ |
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| 211 | |
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| 212 | /* |
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| 213 | * Need to "allocate" the memory for the RTEMS Workspace and |
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| 214 | * tell the RTEMS configuration where it is. This memory is |
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| 215 | * not malloc'ed. It is just "pulled from the air". |
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| 216 | */ |
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| 217 | |
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| 218 | BSP_Configuration.work_space_start = (void *)_WorkspaceBase; |
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| 219 | |
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| 220 | /* |
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| 221 | * initialize the CPU table for this BSP |
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| 222 | */ |
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| 223 | Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ |
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| 224 | Cpu_table.postdriver_hook = bsp_postdriver_hook; |
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| 225 | Cpu_table.do_zero_of_workspace = TRUE; |
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| 226 | Cpu_table.interrupt_stack_size = 4096; |
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| 227 | |
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| 228 | Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */ |
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| 229 | |
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| 230 | /* |
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| 231 | * Invalidate the cache and disable it |
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| 232 | */ |
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[d5fe91e] | 233 | m68k_set_acr0(mcf5282_acr0_mode); |
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| 234 | m68k_set_acr1(mcf5282_acr1_mode); |
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[ac9bbe7] | 235 | m68k_set_cacr_nop(MCF5XXX_CACR_CINV); |
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[572484f] | 236 | |
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| 237 | /* |
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[059c95e] | 238 | * Cache SDRAM |
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[572484f] | 239 | */ |
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[d5fe91e] | 240 | mcf5282_acr0_mode = MCF5XXX_ACR_AB((uint32_t)_RamBase) | |
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| 241 | MCF5XXX_ACR_AM((uint32_t)_RamSize-1) | |
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| 242 | MCF5XXX_ACR_EN | |
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| 243 | MCF5XXX_ACR_BWE | |
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| 244 | MCF5XXX_ACR_SM_IGNORE; |
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| 245 | m68k_set_acr0(mcf5282_acr0_mode); |
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[572484f] | 246 | |
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| 247 | /* |
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| 248 | * Enable the cache |
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| 249 | */ |
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[d5fe91e] | 250 | m68k_set_cacr(mcf5282_cacr_mode); |
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[572484f] | 251 | |
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| 252 | /* |
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| 253 | * Set up CS* space (fake 'VME') |
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| 254 | * Two A24/D16 spaces, supervisor data acces |
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| 255 | */ |
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| 256 | MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(VME_ONE_BASE); |
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| 257 | MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 258 | MCF5282_CS_CSMR_CI | |
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| 259 | MCF5282_CS_CSMR_SC | |
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| 260 | MCF5282_CS_CSMR_UC | |
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| 261 | MCF5282_CS_CSMR_UD | |
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| 262 | MCF5282_CS_CSMR_V; |
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| 263 | MCF5282_CS1_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 264 | MCF5282_CS2_CSAR = MCF5282_CS_CSAR_BA(VME_TWO_BASE); |
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| 265 | MCF5282_CS2_CSMR = MCF5282_CS_CSMR_BAM_16M | |
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| 266 | MCF5282_CS_CSMR_CI | |
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| 267 | MCF5282_CS_CSMR_SC | |
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| 268 | MCF5282_CS_CSMR_UC | |
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| 269 | MCF5282_CS_CSMR_UD | |
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| 270 | MCF5282_CS_CSMR_V; |
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| 271 | MCF5282_CS2_CSCR = MCF5282_CS_CSCR_PS_16; |
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| 272 | } |
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| 273 | |
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[0b2c943] | 274 | uint32_t bsp_get_CPU_clock_speed(void) |
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[572484f] | 275 | { |
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| 276 | extern char _CPUClockSpeed[]; |
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[0b2c943] | 277 | return( (uint32_t)_CPUClockSpeed); |
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[572484f] | 278 | } |
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[7eab0f78] | 279 | |
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[5b6111b] | 280 | /* |
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| 281 | * Interrupt controller allocation |
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| 282 | */ |
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[d75023e] | 283 | rtems_status_code |
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| 284 | bsp_allocate_interrupt(int level, int priority) |
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[5b6111b] | 285 | { |
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| 286 | static char used[7]; |
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| 287 | rtems_interrupt_level l; |
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[d75023e] | 288 | rtems_status_code ret = RTEMS_RESOURCE_IN_USE; |
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[5b6111b] | 289 | |
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| 290 | if ((level < 1) || (level > 7) || (priority < 0) || (priority > 7)) |
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[d75023e] | 291 | return RTEMS_INVALID_NUMBER; |
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[5b6111b] | 292 | rtems_interrupt_disable(l); |
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| 293 | if ((used[level-1] & (1 << priority)) == 0) { |
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| 294 | used[level-1] |= (1 << priority); |
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[d75023e] | 295 | ret = RTEMS_SUCCESSFUL; |
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[5b6111b] | 296 | } |
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| 297 | rtems_interrupt_enable(l); |
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| 298 | return ret; |
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| 299 | } |
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| 300 | |
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[7eab0f78] | 301 | /* |
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[12993b3] | 302 | * Arcturus bootloader system calls |
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[7eab0f78] | 303 | */ |
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[12993b3] | 304 | #define syscall_return(type, ret) \ |
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| 305 | do { \ |
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| 306 | if ((unsigned long)(ret) >= (unsigned long)(-64)) { \ |
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| 307 | errno = -(ret); \ |
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| 308 | ret = -1; \ |
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| 309 | } \ |
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| 310 | return (type)(ret); \ |
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[7eab0f78] | 311 | } while (0) |
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[12993b3] | 312 | #define syscall_1(type,name,d1type,d1) \ |
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[8af3643] | 313 | type bsp_##name(d1type d1) \ |
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[12993b3] | 314 | { \ |
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| 315 | long ret; \ |
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| 316 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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[16ae480] | 317 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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[12993b3] | 318 | "trap #2\n\t" \ |
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| 319 | "move.l %%d0,%0" \ |
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| 320 | : "=g" (ret) \ |
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[8af3643] | 321 | : "i" (SysCode_##name), "d" (__d1) \ |
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[12993b3] | 322 | : "d0" ); \ |
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| 323 | syscall_return(type,ret); \ |
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[7eab0f78] | 324 | } |
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[16ae480] | 325 | #define syscall_2(type,name,d1type,d1,d2type,d2) \ |
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[8af3643] | 326 | type bsp_##name(d1type d1, d2type d2) \ |
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[16ae480] | 327 | { \ |
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| 328 | long ret; \ |
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| 329 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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| 330 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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| 331 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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| 332 | "trap #2\n\t" \ |
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| 333 | "move.l %%d0,%0" \ |
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| 334 | : "=g" (ret) \ |
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[8af3643] | 335 | : "i" (SysCode_##name), "d" (__d1),\ |
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[16ae480] | 336 | "d" (__d2) \ |
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| 337 | : "d0" ); \ |
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| 338 | syscall_return(type,ret); \ |
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| 339 | } |
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[8af3643] | 340 | #define syscall_3(type,name,d1type,d1,d2type,d2,d3type,d3) \ |
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| 341 | type bsp_##name(d1type d1, d2type d2, d3type d3) \ |
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| 342 | { \ |
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| 343 | long ret; \ |
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| 344 | register long __d1 __asm__ ("%d1") = (long)d1; \ |
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| 345 | register long __d2 __asm__ ("%d2") = (long)d2; \ |
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| 346 | register long __d3 __asm__ ("%d3") = (long)d3; \ |
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| 347 | __asm__ __volatile__ ("move.l %1,%%d0\n\t" \ |
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| 348 | "trap #2\n\t" \ |
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| 349 | "move.l %%d0,%0" \ |
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| 350 | : "=g" (ret) \ |
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| 351 | : "i" (SysCode_##name), "d" (__d1),\ |
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| 352 | "d" (__d2),\ |
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| 353 | "d" (__d3) \ |
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| 354 | : "d0" ); \ |
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| 355 | syscall_return(type,ret); \ |
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| 356 | } |
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| 357 | #define SysCode_reset 0 /* reset */ |
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| 358 | #define SysCode_program 5 /* program flash memory */ |
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| 359 | #define SysCode_gethwaddr 12 /* get hardware address */ |
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| 360 | #define SysCode_getbenv 14 /* get bootloader environment variable */ |
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| 361 | #define SysCode_setbenv 15 /* get bootloader environment variable */ |
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| 362 | #define SysCode_flash_erase_range 19 /* erase a section of flash */ |
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| 363 | #define SysCode_flash_write_range 20 /* write a section of flash */ |
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[12993b3] | 364 | syscall_1(unsigned const char *, gethwaddr, int, a) |
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| 365 | syscall_1(const char *, getbenv, const char *, a) |
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[16ae480] | 366 | syscall_2(int, program, bsp_mnode_t *, chain, int, flags) |
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[8af3643] | 367 | syscall_3(int, flash_erase_range, volatile unsigned short *, flashptr, int, start, int, end); |
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| 368 | syscall_3(int, flash_write_range, volatile unsigned short *, flashptr, bsp_mnode_t *, chain, int, offset); |
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[d75023e] | 369 | |
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| 370 | /* |
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| 371 | * 'Extended BSP' routines |
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| 372 | * Should move to cpukit/score/cpu/m68k/cpu.c someday. |
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| 373 | */ |
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| 374 | |
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| 375 | rtems_status_code bspExtInit(void) { return RTEMS_SUCCESSFUL; } |
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| 376 | int BSP_enableVME_int_lvl(unsigned int level) { return 0; } |
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| 377 | int BSP_disableVME_int_lvl(unsigned int level) { return 0; } |
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| 378 | |
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| 379 | /* |
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[a81e4f1] | 380 | * 'VME' interrupt support |
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[402f4df] | 381 | * Interrupt vectors 192-255 are set aside for use by external logic which |
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| 382 | * drives IRQ1*. The actual interrupt source is read from the external |
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| 383 | * logic at FPGA_IRQ_INFO. The most-significant bit of the least-significant |
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| 384 | * byte read from this location is set as long as the external logic has |
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| 385 | * interrupts to be serviced. The least-significant six bits indicate the |
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| 386 | * interrupt source within the external logic and are used to select the |
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| 387 | * specified interupt handler. |
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[d75023e] | 388 | */ |
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[a7e6bc96] | 389 | #define NVECTOR 256 |
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[a81e4f1] | 390 | #define FPGA_VECTOR (64+1) /* IRQ1* pin connected to external FPGA */ |
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[402f4df] | 391 | #define FPGA_EPPAR MCF5282_EPORT_EPPAR_EPPA1_LEVEL |
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[a81e4f1] | 392 | #define FPGA_EPDDR MCF5282_EPORT_EPDDR_EPDD1 |
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| 393 | #define FPGA_EPIER MCF5282_EPORT_EPIER_EPIE1 |
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| 394 | #define FPGA_EPPDR MCF5282_EPORT_EPPDR_EPPD1 |
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| 395 | #define FPGA_IRQ_INFO *((vuint16 *)(0x31000000 + 0xfffffe)) |
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[a7e6bc96] | 396 | |
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[d75023e] | 397 | static struct handlerTab { |
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| 398 | BSP_VME_ISR_t func; |
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| 399 | void *arg; |
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[a7e6bc96] | 400 | } handlerTab[NVECTOR]; |
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[d75023e] | 401 | |
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| 402 | BSP_VME_ISR_t |
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| 403 | BSP_getVME_isr(unsigned long vector, void **pusrArg) |
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| 404 | { |
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[a7e6bc96] | 405 | if (vector >= NVECTOR) |
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[d75023e] | 406 | return (BSP_VME_ISR_t)NULL; |
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| 407 | if (pusrArg) |
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| 408 | *pusrArg = handlerTab[vector].arg; |
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| 409 | return handlerTab[vector].func; |
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| 410 | } |
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| 411 | |
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| 412 | static rtems_isr |
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[a7e6bc96] | 413 | trampoline (rtems_vector_number v) |
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[d75023e] | 414 | { |
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[a81e4f1] | 415 | /* |
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| 416 | * Handle FPGA interrupts until all have been consumed |
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| 417 | */ |
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| 418 | if (v == FPGA_VECTOR) { |
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[402f4df] | 419 | while (((v = FPGA_IRQ_INFO) & 0x80) != 0) { |
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[a81e4f1] | 420 | v = 192 + (v & 0x3f); |
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| 421 | if (handlerTab[v].func) |
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| 422 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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| 423 | else |
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| 424 | rtems_fatal_error_occurred(v); |
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| 425 | } |
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| 426 | } |
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| 427 | else if (handlerTab[v].func) |
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[d75023e] | 428 | (*handlerTab[v].func)(handlerTab[v].arg, (unsigned long)v); |
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| 429 | } |
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| 430 | |
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| 431 | int |
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| 432 | BSP_installVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 433 | { |
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| 434 | rtems_isr_entry old_handler; |
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[a81e4f1] | 435 | rtems_interrupt_level level; |
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[d75023e] | 436 | |
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[a81e4f1] | 437 | /* |
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| 438 | * Register the handler information |
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| 439 | */ |
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[a7e6bc96] | 440 | if (vector >= NVECTOR) |
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[d75023e] | 441 | return -1; |
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| 442 | handlerTab[vector].func = handler; |
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| 443 | handlerTab[vector].arg = usrArg; |
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[a81e4f1] | 444 | |
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| 445 | /* |
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| 446 | * If this is an external FPGA ('VME') vector set up the real IRQ. |
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| 447 | */ |
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| 448 | if ((vector >= 192) && (vector <= 255)) { |
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| 449 | int i; |
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| 450 | static volatile int setupDone; |
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| 451 | rtems_interrupt_disable(level); |
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| 452 | if (setupDone) { |
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| 453 | rtems_interrupt_enable(level); |
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| 454 | return 0; |
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| 455 | } |
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| 456 | MCF5282_EPORT_EPPAR &= ~FPGA_EPPAR; |
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| 457 | MCF5282_EPORT_EPDDR &= ~FPGA_EPDDR; |
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| 458 | MCF5282_EPORT_EPIER |= FPGA_EPIER; |
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[402f4df] | 459 | MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT1 | |
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| 460 | MCF5282_INTC_IMRL_MASKALL); |
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[a81e4f1] | 461 | setupDone = 1; |
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| 462 | i = BSP_installVME_isr(FPGA_VECTOR, NULL, NULL); |
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| 463 | rtems_interrupt_enable(level); |
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| 464 | return i; |
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| 465 | } |
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| 466 | |
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| 467 | /* |
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| 468 | * Make the connection between the interrupt and the local handler |
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| 469 | */ |
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[be129f69] | 470 | rtems_interrupt_catch(trampoline, vector, &old_handler); |
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[d75023e] | 471 | |
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| 472 | /* |
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[a7e6bc96] | 473 | * Find an unused level/priority if this is an on-chip (INTC0) |
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| 474 | * source and this is the first time the source is being used. |
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| 475 | * Interrupt sources 1 through 7 are fixed level/priority |
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[d75023e] | 476 | */ |
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| 477 | if ((vector >= 65) && (vector <= 127)) { |
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| 478 | int l, p; |
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[a7e6bc96] | 479 | int source = vector - 64; |
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| 480 | static unsigned char installed[8]; |
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[d75023e] | 481 | |
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[f3f4be7] | 482 | rtems_interrupt_disable(level); |
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| 483 | if (installed[source/8] & (1 << (source % 8))) { |
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| 484 | rtems_interrupt_enable(level); |
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[a7e6bc96] | 485 | return 0; |
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[f3f4be7] | 486 | } |
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[a7e6bc96] | 487 | installed[source/8] |= (1 << (source % 8)); |
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[f3f4be7] | 488 | rtems_interrupt_enable(level); |
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[d75023e] | 489 | for (l = 1 ; l < 7 ; l++) { |
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[c2ab8b0] | 490 | for (p = 0 ; p < 8 ; p++) { |
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[a7e6bc96] | 491 | if ((source < 8) |
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| 492 | || (bsp_allocate_interrupt(l,p) == RTEMS_SUCCESSFUL)) { |
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[8e712757] | 493 | if (source >= 8) |
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[a7e6bc96] | 494 | *(&MCF5282_INTC0_ICR1 + (source - 1)) = |
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[d75023e] | 495 | MCF5282_INTC_ICR_IL(l) | |
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| 496 | MCF5282_INTC_ICR_IP(p); |
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| 497 | rtems_interrupt_disable(level); |
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[a7e6bc96] | 498 | if (source >= 32) |
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| 499 | MCF5282_INTC0_IMRH &= ~(1 << (source - 32)); |
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[d75023e] | 500 | else |
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[a7e6bc96] | 501 | MCF5282_INTC0_IMRL &= ~((1 << source) | |
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[d75023e] | 502 | MCF5282_INTC_IMRL_MASKALL); |
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| 503 | rtems_interrupt_enable(level); |
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| 504 | return 0; |
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| 505 | } |
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| 506 | } |
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| 507 | } |
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[a7e6bc96] | 508 | return -1; |
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[d75023e] | 509 | } |
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[a7e6bc96] | 510 | return 0; |
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[d75023e] | 511 | } |
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| 512 | |
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| 513 | int |
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| 514 | BSP_removeVME_isr(unsigned long vector, BSP_VME_ISR_t handler, void *usrArg) |
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| 515 | { |
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[a7e6bc96] | 516 | if (vector >= NVECTOR) |
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[d75023e] | 517 | return -1; |
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| 518 | if ((handlerTab[vector].func != handler) |
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| 519 | || (handlerTab[vector].arg != usrArg)) |
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| 520 | return -1; |
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| 521 | handlerTab[vector].func = (BSP_VME_ISR_t)NULL; |
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| 522 | return 0; |
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| 523 | } |
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| 524 | |
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| 525 | int |
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| 526 | BSP_vme2local_adrs(unsigned am, unsigned long vmeaddr, unsigned long *plocaladdr) |
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| 527 | { |
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| 528 | unsigned long offset; |
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| 529 | |
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| 530 | switch (am) { |
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| 531 | default: return -1; |
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[008c4b5] | 532 | case VME_AM_SUP_SHORT_IO: offset = 0x31FF0000; break; /* A16/D16 */ |
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[d75023e] | 533 | case VME_AM_STD_SUP_DATA: offset = 0x30000000; break; /* A24/D16 */ |
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[008c4b5] | 534 | case VME_AM_EXT_SUP_DATA: offset = 0x31000000; break; /* A32/D32 */ |
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[d75023e] | 535 | } |
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| 536 | *plocaladdr = vmeaddr + offset; |
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| 537 | return 0; |
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| 538 | } |
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