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source: rtems/c/src/lib/libbsp/m68k/uC5282/network/network.c @ fa5dfe8

4.104.114.84.95

Last change on this file since fa5dfe8 was fa5dfe8, checked in by Eric Norum <WENorum@…>, on 01/31/05 at 19:04:33
Remove diagnostic printf.
Property mode set to `100644`
File size: 25.8 KB

Line
1	/*
2	* RTEMS/TCPIP driver for MCF5282 Fast Ethernet Controller
3	*
4	* TO DO: MII communications to set speed, full/half duplex, etc.
5	* TO DO: Check network stack code -- force longword alignment of all tx mbufs?
6	*/
7
8	#include <bsp.h>
9	#include <stdio.h>
10	#include <errno.h>
11	#include <stdarg.h>
12	#include <string.h>
13	#include <rtems.h>
14	#include <rtems/error.h>
15	#include <rtems/rtems_bsdnet.h>
16
17	#include <sys/param.h>
18	#include <sys/mbuf.h>
19	#include <sys/socket.h>
20	#include <sys/sockio.h>
21
22	#include <net/ethernet.h>
23	#include <net/if.h>
24
25	#include <netinet/in.h>
26	#include <netinet/if_ether.h>
27
28
29	/*
30	* Number of interfaces supported by this driver
31	*/
32	#define NIFACES 1
33
34	#define FEC_INTC0_TX_VECTOR (64+23)
35	#define FEC_INTC0_RX_VECTOR (64+27)
36
37	/*
38	* Default number of buffer descriptors set aside for this driver.
39	* The number of transmit buffer descriptors has to be quite large
40	* since a single frame often uses three or more buffer descriptors.
41	*/
42	#define RX_BUF_COUNT 32
43	#define TX_BUF_COUNT 20
44	#define TX_BD_PER_BUF 3
45
46	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
47
48	/*
49	* RTEMS event used by interrupt handler to signal daemons.
50	* This must not be the same event used by the TCP/IP task synchronization.
51	*/
52	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
53	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
54
55	/*
56	* RTEMS event used to start transmit daemon.
57	* This must not be the same as INTERRUPT_EVENT.
58	*/
59	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
60
61	/*
62	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
63	* Round off to nearest multiple of RBUF_ALIGN.
64	*/
65	#define MAX_MTU_SIZE 1518
66	#define RBUF_ALIGN 4
67	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
68
69	#if (MCLBYTES < RBUF_SIZE)
70	#error "Driver must have MCLBYTES > RBUF_SIZE"
71	#endif
72
73	typedef struct mcf5282BufferDescriptor_ {
74	volatile rtems_unsigned16 status;
75	rtems_unsigned16 length;
76	volatile void *buffer;
77	} mcf5282BufferDescriptor_t;
78
79	/*
80	* Per-device data
81	*/
82	struct mcf5282_enet_struct {
83	struct arpcom arpcom;
84	struct mbuf **rxMbuf;
85	struct mbuf **txMbuf;
86	int acceptBroadcast;
87	int rxBdCount;
88	int txBdCount;
89	int txBdHead;
90	int txBdTail;
91	int txBdActiveCount;
92	mcf5282BufferDescriptor_t *rxBdBase;
93	mcf5282BufferDescriptor_t *txBdBase;
94	rtems_id rxDaemonTid;
95	rtems_id txDaemonTid;
96
97	/*
98	* Statistics
99	*/
100	unsigned long rxInterrupts;
101	unsigned long txInterrupts;
102	unsigned long txRawWait;
103	unsigned long txRealign;
104	};
105	static struct mcf5282_enet_struct enet_driver[NIFACES];
106
107	static rtems_isr
108	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
109	{
110	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
111	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
112	enet_driver[0].rxInterrupts++;
113	rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
114	}
115
116	static rtems_isr
117	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
118	{
119	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
120	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
121	enet_driver[0].txInterrupts++;
122	rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
123	}
124
125	/*
126	* Allocate buffer descriptors
127	* Ensure 128-bit (16-byte) alignment
128	*/
129	static mcf5282BufferDescriptor_t *
130	mcf5282_bd_allocate(unsigned int count)
131	{
132	mcf5282BufferDescriptor_t *p;
133
134	p = malloc((count * sizeof(mcf5282BufferDescriptor_t)) + 15, 0, M_NOWAIT);
135	if (!p)
136	rtems_panic("FEC BD");
137	if ((int)p & 0xF)
138	p = (mcf5282BufferDescriptor_t )((char )p + (16 - ((int)p & 0xF)));
139	return p;
140	}
141
142	/*
143	* Retrieve MAC address from bootloader environment variable area.
144	* Parameter is interface number (0 or 1).
145	*/
146	static unsigned char *
147	gethwaddr(int a)
148	{
149	register long __res __asm__ ("%d2") = 12;
150	register long __a __asm__ ("%d1") = (long)a;
151	__asm__ __volatile__ ("trap #2" \
152	: "=g" (__res) \
153	: "0" (__res), "d" (__a) \
154	: "%d0");
155	return (unsigned char *)(__res);
156	}
157
158	static void
159	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
160	{
161	int i;
162	unsigned char *hwaddr;
163	rtems_status_code status;
164	rtems_isr_entry old_handler;
165	unsigned32 clock_speed = get_CPU_clock_speed();
166
167	/* extern struct rtems_bsdnet_ifconfig netdriver_config; */
168
169
170	/*
171	* Issue reset to FEC
172	*/
173	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
174	rtems_task_wake_after(1);
175	/*
176	* Configuration of I/O ports is done outside of this function
177	*/
178	#if 0
179	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
180	#endif
181
182	/*
183	* Set our physical address
184	*/
185	hwaddr = sc->arpcom.ac_enaddr;
186	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
187	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
188	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
189
190
191	/*
192	* Clear the hash table
193	*/
194	MCF5282_FEC_GAUR = 0;
195	MCF5282_FEC_GALR = 0;
196
197	/*
198	* Set up receive buffer size
199	*/
200	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
201
202	/*
203	* Allocate mbuf pointers
204	*/
205	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
206	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
207	if (!sc->rxMbuf \|\| !sc->txMbuf)
208	rtems_panic("No memory for mbuf pointers");
209
210	/*
211	* Set receiver and transmitter buffer descriptor bases
212	*/
213	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
214	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
215	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
216	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
217
218	/*
219	* Set up Receive Control Register:
220	* Not promiscuous
221	* MII mode
222	* Half duplex
223	* No loopback
224	*/
225	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
226	MCF5282_FEC_RCR_MII_MODE \|
227	MCF5282_FEC_RCR_DRT;
228
229	/*
230	* Set up Transmit Control Register:
231	* Half duplex
232	* No heartbeat
233	*/
234	MCF5282_FEC_TCR = 0;
235
236	/*
237	* Initialize statistic counters
238	*/
239	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
240	{
241	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
242	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
243	*vuip++ = 0;
244	}
245	MCF5282_FEC_MIBC = 0;
246
247	/*
248	* Set MII speed to <2.5 MHz
249	*/
250	if (clock_speed <= 25000000)
251	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x5);
252	else if (clock_speed <= 33000000)
253	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x7);
254	else if (clock_speed <= 40000000)
255	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x8);
256	else if (clock_speed <= 50000000)
257	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xA);
258	else if (clock_speed <= 66000000)
259	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xD);
260	else
261	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xF);
262
263	/*
264	* Set up receive buffer descriptors
265	*/
266	for (i = 0 ; i < sc->rxBdCount ; i++)
267	(sc->rxBdBase + i)->status = 0;
268
269	/*
270	* Set up transmit buffer descriptors
271	*/
272	for (i = 0 ; i < sc->txBdCount ; i++) {
273	sc->txBdBase[i].status = 0;
274	sc->txMbuf[i] = NULL;
275	}
276	sc->txBdHead = sc->txBdTail = 0;
277	sc->txBdActiveCount = 0;
278
279	/*
280	* Set up interrupts
281	*/
282	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
283	if (status != RTEMS_SUCCESSFUL)
284	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
285	rtems_status_text(status));
286	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
287	if (status != RTEMS_SUCCESSFUL)
288	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
289	rtems_status_text(status));
290	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
291	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
292	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
293	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
294	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
295	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
296	}
297
298	/*
299	* Soak up buffer descriptors that have been sent.
300	*/
301	static void
302	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
303	{
304	struct mbuf m, n;
305	volatile mcf5282BufferDescriptor_t *txBd;
306
307	for (;;) {
308	if (sc->txBdActiveCount == 0)
309	return;
310	txBd = sc->txBdBase + sc->txBdTail;
311	rtems_cache_invalidate_multiple_data_lines(txBd, sizeof *txBd);
312	if ((txBd->status & MCF5282_FEC_TxBD_R) != 0)
313	return;
314	m = sc->txMbuf[sc->txBdTail];
315	MFREE(m, n);
316	if (++sc->txBdTail == sc->txBdCount)
317	sc->txBdTail = 0;
318	sc->txBdActiveCount--;
319	}
320	}
321
322	static void
323	fec_rxDaemon (void *arg)
324	{
325	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
326	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
327	struct mbuf *m;
328	volatile rtems_unsigned16 status;
329	volatile mcf5282BufferDescriptor_t *rxBd;
330	int rxBdIndex;
331
332	/*
333	* Allocate space for incoming packets and start reception
334	*/
335	for (rxBdIndex = 0 ; ;) {
336	rxBd = sc->rxBdBase + rxBdIndex;
337	MGETHDR(m, M_WAIT, MT_DATA);
338	MCLGET(m, M_WAIT);
339	m->m_pkthdr.rcvif = ifp;
340	sc->rxMbuf[rxBdIndex] = m;
341	rxBd->buffer = mtod(m, void *);
342	rxBd->status = MCF5282_FEC_RxBD_E;
343	if (++rxBdIndex == sc->rxBdCount) {
344	rxBd->status \|= MCF5282_FEC_RxBD_W;
345	break;
346	}
347	}
348
349	/*
350	* Input packet handling loop
351	*/
352	/* Indicate we have some ready buffers available */
353	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
354
355	rxBdIndex = 0;
356	for (;;) {
357	rxBd = sc->rxBdBase + rxBdIndex;
358
359	/*
360	* Wait for packet if there's not one ready
361	*/
362	rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
363	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
364	int chkCount=0 ;
365	/*
366	* Clear old events.
367	*/
368	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
369
370	/*
371	* Wait for packet to arrive.
372	* Check the buffer descriptor before waiting for the event.
373	* This catches the case when a packet arrives between the
374	* `if' above, and the clearing of the RXF bit in the EIR.
375	*/
376	for (;;) {
377	rtems_event_set events;
378	int level;
379
380	rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
381	if (((status = rxBd->status) & MCF5282_FEC_RxBD_E) == 0)
382	break;
383
384	rtems_interrupt_disable(level);
385	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
386	rtems_interrupt_enable(level);
387	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
388	RTEMS_WAIT\|RTEMS_EVENT_ANY,
389	RTEMS_NO_TIMEOUT,
390	&events);
391	}
392	}
393
394	/*
395	* Check that packet is valid
396	*/
397	if (status & MCF5282_FEC_RxBD_L) {
398	/*
399	* Pass the packet up the chain.
400	* FIXME: Packet filtering hook could be done here.
401	*/
402	struct ether_header *eh;
403	int len = rxBd->length - sizeof(rtems_unsigned32);;
404
405	/*
406	* Invalidate the cache and push the packet up
407	* The cache is so small that it's more efficient to just
408	* invalidate the whole thing unless the packet is very small.
409	*/
410	m = sc->rxMbuf[rxBdIndex];
411	if (len < 128)
412	rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
413	else
414	rtems_cache_invalidate_entire_data();
415	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
416	eh = mtod(m, struct ether_header *);
417	m->m_data += sizeof(struct ether_header);
418	ether_input(ifp, eh, m);
419
420	/*
421	* Allocate a new mbuf
422	*/
423	MGETHDR(m, M_WAIT, MT_DATA);
424	MCLGET(m, M_WAIT);
425	m->m_pkthdr.rcvif = ifp;
426	sc->rxMbuf[rxBdIndex] = m;
427	rxBd->buffer = mtod(m, void *);
428	}
429
430	/*
431	* Reenable the buffer descriptor
432	*/
433	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
434	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
435
436	/*
437	* Move to next buffer descriptor
438	*/
439	if (++rxBdIndex == sc->rxBdCount)
440	rxBdIndex = 0;
441	}
442	}
443
444	static void
445	fec_sendpacket(struct ifnet ifp, struct mbuf m)
446	{
447	struct mcf5282_enet_struct *sc = ifp->if_softc;
448	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
449	rtems_unsigned16 status;
450	int nAdded;
451
452	/*
453	* Free up buffer descriptors
454	*/
455	fec_retire_tx_bd(sc);
456
457	/*
458	* Set up the transmit buffer descriptors.
459	* No need to pad out short packets since the
460	* hardware takes care of that automatically.
461	* No need to copy the packet to a contiguous buffer
462	* since the hardware is capable of scatter/gather DMA.
463	*/
464	nAdded = 0;
465	firstTxBd = sc->txBdBase + sc->txBdHead;
466
467	for (;;) {
468	/*
469	* Wait for buffer descriptor to become available
470	*/
471	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
472	/*
473	* Clear old events.
474	*/
475	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
476
477	/*
478	* Wait for buffer descriptor to become available.
479	* Check for buffer descriptors before waiting for the event.
480	* This catches the case when a buffer became available between
481	* the `if' above, and the clearing of the TXF bit in the EIR.
482	*/
483	fec_retire_tx_bd(sc);
484	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
485	rtems_event_set events;
486	int level;
487
488	rtems_interrupt_disable(level);
489	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
490	rtems_interrupt_enable(level);
491	sc->txRawWait++;
492	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
493	RTEMS_WAIT\|RTEMS_EVENT_ANY,
494	RTEMS_NO_TIMEOUT,
495	&events);
496	fec_retire_tx_bd(sc);
497	}
498	}
499
500	/*
501	* Don't set the READY flag on the first fragment
502	* until the whole packet has been readied.
503	*/
504	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
505
506	/*
507	* The IP fragmentation routine in ip_output
508	* can produce fragments with zero length.
509	*/
510	txBd = sc->txBdBase + sc->txBdHead;
511	if (m->m_len) {
512	char p = mtod(m, char );
513	/*
514	* Stupid FEC can't handle misaligned data!
515	* Given the way that mbuf's are layed out it should be
516	* safe to shuffle the data down like this.....
517	* Perhaps this code could be improved with a "Duff's Device".
518	*/
519	if ((int)p & 0x3) {
520	int l = m->m_len;
521	char *dest = p - ((int)p & 0x3);
522	unsigned16 o = (unsigned16 )dest, i = (unsigned16 )p;
523	while (l > 0) {
524	o++ = i++;
525	l -= sizeof(unsigned16);
526	}
527	p = dest;
528	sc->txRealign++;
529	}
530	txBd->buffer = p;
531	txBd->length = m->m_len;
532	sc->txMbuf[sc->txBdHead] = m;
533	nAdded++;
534	if (++sc->txBdHead == sc->txBdCount) {
535	status \|= MCF5282_FEC_TxBD_W;
536	sc->txBdHead = 0;
537	}
538	m = m->m_next;
539	}
540	else {
541	/*
542	* Just toss empty mbufs
543	*/
544	struct mbuf *n;
545	MFREE(m, n);
546	m = n;
547	}
548	if (m == NULL) {
549	if (nAdded) {
550	txBd->status = status \| MCF5282_FEC_TxBD_R
551	\| MCF5282_FEC_TxBD_L
552	\| MCF5282_FEC_TxBD_TC;
553	if (nAdded > 1)
554	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
555	MCF5282_FEC_TDAR = MCF5282_FEC_TDAR_X_DES_ACTIVE;
556	sc->txBdActiveCount += nAdded;
557	}
558	break;
559	}
560	txBd->status = status;
561	}
562	}
563
564	void
565	fec_txDaemon(void *arg)
566	{
567	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
568	struct ifnet *ifp = &sc->arpcom.ac_if;
569	struct mbuf *m;
570	rtems_event_set events;
571
572	for (;;) {
573	/*
574	* Wait for packet
575	*/
576	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
577	RTEMS_EVENT_ANY \| RTEMS_WAIT,
578	RTEMS_NO_TIMEOUT,
579	&events);
580
581	/*
582	* Send packets till queue is empty
583	*/
584	for (;;) {
585	/*
586	* Get the next mbuf chain to transmit.
587	*/
588	IF_DEQUEUE(&ifp->if_snd, m);
589	if (!m)
590	break;
591	fec_sendpacket(ifp, m);
592	}
593	ifp->if_flags &= ~IFF_OACTIVE;
594	}
595	}
596
597
598	/*
599	* Send packet (caller provides header).
600	*/
601	static void
602	mcf5282_enet_start(struct ifnet *ifp)
603	{
604	struct mcf5282_enet_struct *sc = ifp->if_softc;
605
606	rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
607	ifp->if_flags \|= IFF_OACTIVE;
608	}
609
610	static void
611	fec_init(void *arg)
612	{
613	struct mcf5282_enet_struct *sc = arg;
614	struct ifnet *ifp = &sc->arpcom.ac_if;
615
616	if (sc->txDaemonTid == 0) {
617	/*
618	* Set up hardware
619	*/
620	mcf5282_fec_initialize_hardware(sc);
621
622	/*
623	* Start driver tasks
624	*/
625	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
626	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
627	}
628
629	/*
630	* Set flags appropriately
631	*/
632	if (ifp->if_flags & IFF_PROMISC)
633	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
634	else
635	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
636
637	/*
638	* Tell the world that we're running.
639	*/
640	ifp->if_flags \|= IFF_RUNNING;
641
642	/*
643	* Enable receiver and transmitter
644	*/
645	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
646	}
647
648
649	static void
650	fec_stop(struct mcf5282_enet_struct *sc)
651	{
652	struct ifnet *ifp = &sc->arpcom.ac_if;
653
654	ifp->if_flags &= ~IFF_RUNNING;
655
656	/*
657	* Shut down receiver and transmitter
658	*/
659	MCF5282_FEC_ECR = 0x0;
660	}
661
662	/*
663	* Show interface statistics
664	*/
665	static void
666	enet_stats(struct mcf5282_enet_struct *sc)
667	{
668	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
669	printf("Rx Packet Count:%-10lu", MCF5282_FEC_RMON_R_PACKETS);
670	printf(" Rx Broadcast:%-10lu\n", MCF5282_FEC_RMON_R_BC_PKT);
671	printf(" Rx Multicast:%-10lu", MCF5282_FEC_RMON_R_MC_PKT);
672	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_R_CRC_ALIGN);
673	printf(" Rx Undersize:%-10lu\n", MCF5282_FEC_RMON_R_UNDERSIZE);
674	printf(" Rx Oversize:%-10lu", MCF5282_FEC_RMON_R_OVERSIZE);
675	printf(" Rx Fragment:%-10lu", MCF5282_FEC_RMON_R_FRAG);
676	printf(" Rx Jabber:%-10lu\n", MCF5282_FEC_RMON_R_JAB);
677	printf(" Rx 64:%-10lu", MCF5282_FEC_RMON_R_P64);
678	printf(" Rx 65-127:%-10lu", MCF5282_FEC_RMON_R_P65T0127);
679	printf(" Rx 128-255:%-10lu\n", MCF5282_FEC_RMON_R_P128TO255);
680	printf(" Rx 256-511:%-10lu", MCF5282_FEC_RMON_R_P256TO511);
681	printf(" Rx 511-1023:%-10lu", MCF5282_FEC_RMON_R_P512TO1023);
682	printf(" Rx 1024-2047:%-10lu\n", MCF5282_FEC_RMON_R_P1024TO2047);
683	printf(" Rx >=2048:%-10lu", MCF5282_FEC_RMON_R_GTE2048);
684	printf(" Rx Octets:%-10lu", MCF5282_FEC_RMON_R_OCTETS);
685	printf(" Rx Dropped:%-10lu\n", MCF5282_FEC_IEEE_R_DROP);
686	printf(" Rx frame OK:%-10lu", MCF5282_FEC_IEEE_R_FRAME_OK);
687	printf(" Rx CRC error:%-10lu", MCF5282_FEC_IEEE_R_CRC);
688	printf(" Rx Align error:%-10lu\n", MCF5282_FEC_IEEE_R_ALIGN);
689	printf(" FIFO Overflow:%-10lu", MCF5282_FEC_IEEE_R_MACERR);
690	printf("Rx Pause Frames:%-10lu", MCF5282_FEC_IEEE_R_FDXFC);
691	printf(" Rx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_R_OCTETS_OK);
692	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
693	printf("Tx Output Waits:%-10lu", sc->txRawWait);
694	printf("Tx Realignments:%-10lu\n", sc->txRealign);
695	printf(" Tx Unaccounted:%-10lu", MCF5282_FEC_RMON_T_DROP);
696	printf("Tx Packet Count:%-10lu", MCF5282_FEC_RMON_T_PACKETS);
697	printf(" Tx Broadcast:%-10lu\n", MCF5282_FEC_RMON_T_BC_PKT);
698	printf(" Tx Multicast:%-10lu", MCF5282_FEC_RMON_T_MC_PKT);
699	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_T_CRC_ALIGN);
700	printf(" Tx Undersize:%-10lu\n", MCF5282_FEC_RMON_T_UNDERSIZE);
701	printf(" Tx Oversize:%-10lu", MCF5282_FEC_RMON_T_OVERSIZE);
702	printf(" Tx Fragment:%-10lu", MCF5282_FEC_RMON_T_FRAG);
703	printf(" Tx Jabber:%-10lu\n", MCF5282_FEC_RMON_T_JAB);
704	printf(" Tx Collisions:%-10lu", MCF5282_FEC_RMON_T_COL);
705	printf(" Tx 64:%-10lu", MCF5282_FEC_RMON_T_P64);
706	printf(" Tx 65-127:%-10lu\n", MCF5282_FEC_RMON_T_P65TO127);
707	printf(" Tx 128-255:%-10lu", MCF5282_FEC_RMON_T_P128TO255);
708	printf(" Tx 256-511:%-10lu", MCF5282_FEC_RMON_T_P256TO511);
709	printf(" Tx 511-1023:%-10lu\n", MCF5282_FEC_RMON_T_P512TO1023);
710	printf(" Tx 1024-2047:%-10lu", MCF5282_FEC_RMON_T_P1024TO2047);
711	printf(" Tx >=2048:%-10lu", MCF5282_FEC_RMON_T_P_GTE2048);
712	printf(" Tx Octets:%-10lu\n", MCF5282_FEC_RMON_T_OCTETS);
713	printf(" Tx Dropped:%-10lu", MCF5282_FEC_IEEE_T_DROP);
714	printf(" Tx Frame OK:%-10lu", MCF5282_FEC_IEEE_T_FRAME_OK);
715	printf(" Tx 1 Collision:%-10lu\n", MCF5282_FEC_IEEE_T_1COL);
716	printf("Tx >1 Collision:%-10lu", MCF5282_FEC_IEEE_T_MCOL);
717	printf(" Tx Deferred:%-10lu", MCF5282_FEC_IEEE_T_DEF);
718	printf(" Late Collision:%-10lu\n", MCF5282_FEC_IEEE_T_LCOL);
719	printf(" Excessive Coll:%-10lu", MCF5282_FEC_IEEE_T_EXCOL);
720	printf(" FIFO Underrun:%-10lu", MCF5282_FEC_IEEE_T_MACERR);
721	printf(" Carrier Error:%-10lu\n", MCF5282_FEC_IEEE_T_CSERR);
722	printf(" Tx SQE Error:%-10lu", MCF5282_FEC_IEEE_T_SQE);
723	printf("Tx Pause Frames:%-10lu", MCF5282_FEC_IEEE_T_FDXFC);
724	printf(" Tx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_T_OCTETS_OK);
725	}
726
727	static int
728	fec_ioctl(struct ifnet *ifp, int command, caddr_t data)
729	{
730	struct mcf5282_enet_struct *sc = ifp->if_softc;
731	int error = 0;
732
733	switch (command) {
734	case SIOCGIFADDR:
735	case SIOCSIFADDR:
736	ether_ioctl(ifp, command, data);
737	break;
738
739	case SIOCSIFFLAGS:
740	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
741	case IFF_RUNNING:
742	fec_stop(sc);
743	break;
744
745	case IFF_UP:
746	fec_init(sc);
747	break;
748
749	case IFF_UP \| IFF_RUNNING:
750	fec_stop(sc);
751	fec_init(sc);
752	break;
753
754	default:
755	break;
756	}
757	break;
758
759	case SIO_RTEMS_SHOW_STATS:
760	enet_stats(sc);
761	break;
762
763	/*
764	* FIXME: All sorts of multicast commands need to be added here!
765	*/
766	default:
767	error = EINVAL;
768	break;
769	}
770	return error;
771	}
772
773	int
774	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
775	{
776	struct mcf5282_enet_struct *sc;
777	struct ifnet *ifp;
778	int mtu;
779	int unitNumber;
780	char *unitName;
781	unsigned char *hwaddr;
782
783	/*
784	* Parse driver name
785	*/
786	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
787	return 0;
788
789	/*
790	* Is driver free?
791	*/
792	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
793	printf("Bad FEC unit number.\n");
794	return 0;
795	}
796	sc = &enet_driver[unitNumber - 1];
797	ifp = &sc->arpcom.ac_if;
798	if (ifp->if_softc != NULL) {
799	printf("Driver already in use.\n");
800	return 0;
801	}
802
803	/*
804	* Process options
805	*/
806	if (config->hardware_address)
807	hwaddr = config->hardware_address;
808	else
809	hwaddr = gethwaddr(unitNumber - 1);
810	printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n",
811	unitName, unitNumber,
812	hwaddr[0], hwaddr[1], hwaddr[2],
813	hwaddr[3], hwaddr[4], hwaddr[5]);
814	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
815
816	if (config->mtu)
817	mtu = config->mtu;
818	else
819	mtu = ETHERMTU;
820	if (config->rbuf_count)
821	sc->rxBdCount = config->rbuf_count;
822	else
823	sc->rxBdCount = RX_BUF_COUNT;
824	if (config->xbuf_count)
825	sc->txBdCount = config->xbuf_count;
826	else
827	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
828
829	sc->acceptBroadcast = !config->ignore_broadcast;
830
831	/*
832	* Set up network interface values
833	*/
834	ifp->if_softc = sc;
835	ifp->if_unit = unitNumber;
836	ifp->if_name = unitName;
837	ifp->if_mtu = mtu;
838	ifp->if_init = fec_init;
839	ifp->if_ioctl = fec_ioctl;
840	ifp->if_start = mcf5282_enet_start;
841	ifp->if_output = ether_output;
842	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
843	if (ifp->if_snd.ifq_maxlen == 0)
844	ifp->if_snd.ifq_maxlen = ifqmaxlen;
845
846	/*
847	* Attach the interface
848	*/
849	if_attach(ifp);
850	ether_ifattach(ifp);
851	return 1;
852	};
853

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