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source: rtems/c/src/lib/libbsp/m68k/uC5282/network/network.c @ cdb717e

4.104.114.84.95

Last change on this file since cdb717e was cdb717e, checked in by Eric Norum <WENorum@…>, on 06/22/05 at 18:53:10
Minor tweak to make it easier to insert some code to test realignment.
Property mode set to `100644`
File size: 27.7 KB

Line
1	/*
2	* RTEMS/TCPIP driver for MCF5282 Fast Ethernet Controller
3	*/
4
5	#include <bsp.h>
6	#include <stdio.h>
7	#include <errno.h>
8	#include <stdarg.h>
9	#include <string.h>
10	#include <rtems.h>
11	#include <rtems/error.h>
12	#include <rtems/rtems_bsdnet.h>
13
14	#include <sys/param.h>
15	#include <sys/mbuf.h>
16	#include <sys/socket.h>
17	#include <sys/sockio.h>
18
19	#include <net/ethernet.h>
20	#include <net/if.h>
21
22	#include <netinet/in.h>
23	#include <netinet/if_ether.h>
24
25
26	/*
27	* Number of interfaces supported by this driver
28	*/
29	#define NIFACES 1
30
31	#define FEC_INTC0_TX_VECTOR (64+23)
32	#define FEC_INTC0_RX_VECTOR (64+27)
33
34	/*
35	* Default number of buffer descriptors set aside for this driver.
36	* The number of transmit buffer descriptors has to be quite large
37	* since a single frame often uses three or more buffer descriptors.
38	*/
39	#define RX_BUF_COUNT 32
40	#define TX_BUF_COUNT 20
41	#define TX_BD_PER_BUF 3
42
43	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
44
45	/*
46	* RTEMS event used by interrupt handler to signal daemons.
47	* This must not be the same event used by the TCP/IP task synchronization.
48	*/
49	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
50	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
51
52	/*
53	* RTEMS event used to start transmit daemon.
54	* This must not be the same as INTERRUPT_EVENT.
55	*/
56	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
57
58	/*
59	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
60	* Round off to nearest multiple of RBUF_ALIGN.
61	*/
62	#define MAX_MTU_SIZE 1518
63	#define RBUF_ALIGN 4
64	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
65
66	#if (MCLBYTES < RBUF_SIZE)
67	#error "Driver must have MCLBYTES > RBUF_SIZE"
68	#endif
69
70	typedef struct mcf5282BufferDescriptor_ {
71	volatile uint16_t status;
72	uint16_t length;
73	volatile void *buffer;
74	} mcf5282BufferDescriptor_t;
75
76	/*
77	* Per-device data
78	*/
79	struct mcf5282_enet_struct {
80	struct arpcom arpcom;
81	struct mbuf **rxMbuf;
82	struct mbuf **txMbuf;
83	int acceptBroadcast;
84	int rxBdCount;
85	int txBdCount;
86	int txBdHead;
87	int txBdTail;
88	int txBdActiveCount;
89	mcf5282BufferDescriptor_t *rxBdBase;
90	mcf5282BufferDescriptor_t *txBdBase;
91	rtems_id rxDaemonTid;
92	rtems_id txDaemonTid;
93
94	/*
95	* Statistics
96	*/
97	unsigned long rxInterrupts;
98	unsigned long txInterrupts;
99	unsigned long txRawWait;
100	unsigned long txRealign;
101	unsigned long txRealignDrop;
102	};
103	static struct mcf5282_enet_struct enet_driver[NIFACES];
104
105	static rtems_isr
106	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
107	{
108	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
109	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
110	enet_driver[0].rxInterrupts++;
111	rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
112	}
113
114	static rtems_isr
115	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
116	{
117	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
118	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
119	enet_driver[0].txInterrupts++;
120	rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
121	}
122
123	/*
124	* Allocate buffer descriptors from (non-cached) on-chip static RAM
125	* Ensure 128-bit (16-byte) alignment
126	*/
127	static mcf5282BufferDescriptor_t *
128	mcf5282_bd_allocate(unsigned int count)
129	{
130	extern char __SRAMBASE[];
131	static mcf5282BufferDescriptor_t bdp = (mcf5282BufferDescriptor_t )__SRAMBASE;
132	mcf5282BufferDescriptor_t *p = bdp;
133
134	bdp += count;
135	if ((int)bdp & 0xF)
136	bdp = (mcf5282BufferDescriptor_t )((char )bdp + (16 - ((int)bdp & 0xF)));
137	return p;
138	}
139
140	#if UNUSED
141	/*
142	* Read MII register
143	* Busy-waits, but transfer time should be short!
144	*/
145	static int
146	getMII(int phyNumber, int regNumber)
147	{
148	MCF5282_FEC_MMFR = (0x1 << 30) \|
149	(0x2 << 28) \|
150	(phyNumber << 23) \|
151	(regNumber << 18) \|
152	(0x2 << 16);
153	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
154	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
155	return MCF5282_FEC_MMFR & 0xFFFF;
156	}
157	#endif
158
159	/*
160	* Write MII register
161	* Busy-waits, but transfer time should be short!
162	*/
163	static void
164	setMII(int phyNumber, int regNumber, int value)
165	{
166	MCF5282_FEC_MMFR = (0x1 << 30) \|
167	(0x1 << 28) \|
168	(phyNumber << 23) \|
169	(regNumber << 18) \|
170	(0x2 << 16) \|
171	(value & 0xFFFF);
172	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
173	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
174	}
175
176	static void
177	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
178	{
179	int i;
180	const unsigned char *hwaddr;
181	rtems_status_code status;
182	rtems_isr_entry old_handler;
183	uint32_t clock_speed = bsp_get_CPU_clock_speed();
184
185	/*
186	* Issue reset to FEC
187	*/
188	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
189	rtems_task_wake_after(1);
190	MCF5282_FEC_ECR = 0;
191
192	/*
193	* Configuration of I/O ports is done outside of this function
194	*/
195	#if 0
196	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
197	#endif
198
199	/*
200	* Set our physical address
201	*/
202	hwaddr = sc->arpcom.ac_enaddr;
203	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
204	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
205	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
206
207
208	/*
209	* Clear the hash table
210	*/
211	MCF5282_FEC_GAUR = 0;
212	MCF5282_FEC_GALR = 0;
213
214	/*
215	* Set up receive buffer size
216	*/
217	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
218
219	/*
220	* Allocate mbuf pointers
221	*/
222	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
223	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
224	if (!sc->rxMbuf \|\| !sc->txMbuf)
225	rtems_panic("No memory for mbuf pointers");
226
227	/*
228	* Set receiver and transmitter buffer descriptor bases
229	*/
230	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
231	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
232	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
233	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
234
235	/*
236	* Set up Receive Control Register:
237	* Not promiscuous
238	* MII mode
239	* Full duplex
240	* No loopback
241	*/
242	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
243	MCF5282_FEC_RCR_MII_MODE;
244
245	/*
246	* Set up Transmit Control Register:
247	* Full duplex
248	* No heartbeat
249	*/
250	MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
251
252	/*
253	* Initialize statistic counters
254	*/
255	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
256	{
257	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
258	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
259	*vuip++ = 0;
260	}
261	MCF5282_FEC_MIBC = 0;
262
263	/*
264	* Set MII speed to <= 2.5 MHz
265	*/
266	i = (clock_speed + 5000000 - 1) / 5000000;
267	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
268
269	/*
270	* Set PHYS to 100 Mb/s, full duplex
271	*/
272	setMII(1, 0, 0x2100);
273
274	/*
275	* Set up receive buffer descriptors
276	*/
277	for (i = 0 ; i < sc->rxBdCount ; i++)
278	(sc->rxBdBase + i)->status = 0;
279
280	/*
281	* Set up transmit buffer descriptors
282	*/
283	for (i = 0 ; i < sc->txBdCount ; i++) {
284	sc->txBdBase[i].status = 0;
285	sc->txMbuf[i] = NULL;
286	}
287	sc->txBdHead = sc->txBdTail = 0;
288	sc->txBdActiveCount = 0;
289
290	/*
291	* Set up interrupts
292	*/
293	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
294	if (status != RTEMS_SUCCESSFUL)
295	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
296	rtems_status_text(status));
297	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
298	if (status != RTEMS_SUCCESSFUL)
299	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
300	rtems_status_text(status));
301	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY);
302	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
303	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
304	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
305	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY);
306	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
307	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
308	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
309	}
310
311	/*
312	* Soak up buffer descriptors that have been sent.
313	*/
314	static void
315	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
316	{
317	struct mbuf m, n;
318	uint16_t status;
319
320	while ((sc->txBdActiveCount != 0)
321	&& (((status = sc->txBdBase[sc->txBdTail].status) & MCF5282_FEC_TxBD_R) == 0)) {
322	if ((status & MCF5282_FEC_TxBD_TO1) == 0) {
323	m = sc->txMbuf[sc->txBdTail];
324	MFREE(m, n);
325	}
326	if (++sc->txBdTail == sc->txBdCount)
327	sc->txBdTail = 0;
328	sc->txBdActiveCount--;
329	}
330	}
331
332	static void
333	fec_rxDaemon (void *arg)
334	{
335	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
336	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
337	struct mbuf *m;
338	uint16_t status;
339	volatile mcf5282BufferDescriptor_t *rxBd;
340	int rxBdIndex;
341
342	/*
343	* Allocate space for incoming packets and start reception
344	*/
345	for (rxBdIndex = 0 ; ;) {
346	rxBd = sc->rxBdBase + rxBdIndex;
347	MGETHDR(m, M_WAIT, MT_DATA);
348	MCLGET(m, M_WAIT);
349	m->m_pkthdr.rcvif = ifp;
350	sc->rxMbuf[rxBdIndex] = m;
351	rxBd->buffer = mtod(m, void *);
352	rxBd->status = MCF5282_FEC_RxBD_E;
353	if (++rxBdIndex == sc->rxBdCount) {
354	rxBd->status \|= MCF5282_FEC_RxBD_W;
355	break;
356	}
357	}
358
359	/*
360	* Input packet handling loop
361	*/
362	MCF5282_FEC_RDAR = 0;
363
364	rxBdIndex = 0;
365	for (;;) {
366	rxBd = sc->rxBdBase + rxBdIndex;
367
368	/*
369	* Wait for packet if there's not one ready
370	*/
371	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
372	/*
373	* Clear old events.
374	*/
375	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
376
377	/*
378	* Wait for packet to arrive.
379	* Check the buffer descriptor before waiting for the event.
380	* This catches the case when a packet arrives between the
381	* `if' above, and the clearing of the RXF bit in the EIR.
382	*/
383	while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
384	rtems_event_set events;
385	int level;
386
387	rtems_interrupt_disable(level);
388	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
389	rtems_interrupt_enable(level);
390	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
391	RTEMS_WAIT\|RTEMS_EVENT_ANY,
392	RTEMS_NO_TIMEOUT,
393	&events);
394	}
395	}
396
397	/*
398	* Check that packet is valid
399	*/
400	if (status & MCF5282_FEC_RxBD_L) {
401	/*
402	* Pass the packet up the chain.
403	* FIXME: Packet filtering hook could be done here.
404	*/
405	struct ether_header *eh;
406	int len = rxBd->length - sizeof(uint32_t);;
407
408	m = sc->rxMbuf[rxBdIndex];
409	#ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE
410	/*
411	* Invalidate the cache. The cache is so small that it's
412	* more efficient to just invalidate the whole thing unless
413	* the packet is very small.
414	*/
415	if (len < 128)
416	rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
417	else
418	rtems_cache_invalidate_entire_data();
419	#endif
420	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
421	eh = mtod(m, struct ether_header *);
422	m->m_data += sizeof(struct ether_header);
423	ether_input(ifp, eh, m);
424
425	/*
426	* Allocate a new mbuf
427	*/
428	MGETHDR(m, M_WAIT, MT_DATA);
429	MCLGET(m, M_WAIT);
430	m->m_pkthdr.rcvif = ifp;
431	sc->rxMbuf[rxBdIndex] = m;
432	rxBd->buffer = mtod(m, void *);
433	}
434
435	/*
436	* Reenable the buffer descriptor
437	*/
438	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
439	MCF5282_FEC_RDAR = 0;
440
441	/*
442	* Move to next buffer descriptor
443	*/
444	if (++rxBdIndex == sc->rxBdCount)
445	rxBdIndex = 0;
446	}
447	}
448
449	static void
450	fec_sendpacket(struct ifnet ifp, struct mbuf m)
451	{
452	struct mcf5282_enet_struct *sc = ifp->if_softc;
453	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
454	uint16_t status;
455	int nAdded;
456
457	/*
458	* Free up buffer descriptors
459	*/
460	fec_retire_tx_bd(sc);
461
462	/*
463	* Set up the transmit buffer descriptors.
464	* No need to pad out short packets since the
465	* hardware takes care of that automatically.
466	* No need to copy the packet to a contiguous buffer
467	* since the hardware is capable of scatter/gather DMA.
468	*/
469	nAdded = 0;
470	firstTxBd = sc->txBdBase + sc->txBdHead;
471
472	while (m != NULL) {
473	/*
474	* Wait for buffer descriptor to become available
475	*/
476	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
477	/*
478	* Clear old events.
479	*/
480	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
481
482	/*
483	* Wait for buffer descriptor to become available.
484	* Check for buffer descriptors before waiting for the event.
485	* This catches the case when a buffer became available between
486	* the `if' above, and the clearing of the TXF bit in the EIR.
487	*/
488	fec_retire_tx_bd(sc);
489	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
490	rtems_event_set events;
491	int level;
492
493	rtems_interrupt_disable(level);
494	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
495	rtems_interrupt_enable(level);
496	sc->txRawWait++;
497	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
498	RTEMS_WAIT\|RTEMS_EVENT_ANY,
499	RTEMS_NO_TIMEOUT,
500	&events);
501	fec_retire_tx_bd(sc);
502	}
503	}
504
505	/*
506	* Don't set the READY flag on the first fragment
507	* until the whole packet has been readied.
508	*/
509	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
510
511	/*
512	* The IP fragmentation routine in ip_output
513	* can produce fragments with zero length.
514	*/
515	txBd = sc->txBdBase + sc->txBdHead;
516	if (m->m_len) {
517	char p = mtod(m, char );
518	int offset = (int)p & 0x3;
519	if (offset == 0) {
520	txBd->buffer = p;
521	txBd->length = m->m_len;
522	sc->txMbuf[sc->txBdHead] = m;
523	m = m->m_next;
524	}
525	else {
526	/*
527	* Stupid FEC can't handle misaligned data!
528	* Move offending bytes to a local buffer.
529	* Use buffer descriptor TO1 bit to indicate this.
530	*/
531	int nmove = 4 - offset;
532	char d = (char )&sc->txMbuf[sc->txBdHead];
533	status \|= MCF5282_FEC_TxBD_TO1;
534	sc->txRealign++;
535	if (nmove > m->m_len)
536	nmove = m->m_len;
537	m->m_data += nmove;
538	m->m_len -= nmove;
539	txBd->buffer = d;
540	txBd->length = nmove;
541	while (nmove--)
542	d++ = p++;
543	if (m->m_len == 0) {
544	struct mbuf *n;
545	sc->txRealignDrop++;
546	MFREE(m, n);
547	m = n;
548	}
549	}
550	nAdded++;
551	if (++sc->txBdHead == sc->txBdCount) {
552	status \|= MCF5282_FEC_TxBD_W;
553	sc->txBdHead = 0;
554	}
555	txBd->status = status;
556	}
557	else {
558	/*
559	* Toss empty mbufs.
560	*/
561	struct mbuf *n;
562	MFREE(m, n);
563	m = n;
564	}
565	}
566	if (nAdded) {
567	txBd->status = status \| MCF5282_FEC_TxBD_R
568	\| MCF5282_FEC_TxBD_L
569	\| MCF5282_FEC_TxBD_TC;
570	if (nAdded > 1)
571	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
572	MCF5282_FEC_TDAR = 0;
573	sc->txBdActiveCount += nAdded;
574	}
575	}
576
577	void
578	fec_txDaemon(void *arg)
579	{
580	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
581	struct ifnet *ifp = &sc->arpcom.ac_if;
582	struct mbuf *m;
583	rtems_event_set events;
584
585	for (;;) {
586	/*
587	* Wait for packet
588	*/
589	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
590	RTEMS_EVENT_ANY \| RTEMS_WAIT,
591	RTEMS_NO_TIMEOUT,
592	&events);
593
594	/*
595	* Send packets till queue is empty
596	*/
597	for (;;) {
598	/*
599	* Get the next mbuf chain to transmit.
600	*/
601	IF_DEQUEUE(&ifp->if_snd, m);
602	if (!m)
603	break;
604	fec_sendpacket(ifp, m);
605	}
606	ifp->if_flags &= ~IFF_OACTIVE;
607	}
608	}
609
610
611	/*
612	* Send packet (caller provides header).
613	*/
614	static void
615	mcf5282_enet_start(struct ifnet *ifp)
616	{
617	struct mcf5282_enet_struct *sc = ifp->if_softc;
618
619	rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
620	ifp->if_flags \|= IFF_OACTIVE;
621	}
622
623	static void
624	fec_init(void *arg)
625	{
626	struct mcf5282_enet_struct *sc = arg;
627	struct ifnet *ifp = &sc->arpcom.ac_if;
628
629	if (sc->txDaemonTid == 0) {
630	/*
631	* Set up hardware
632	*/
633	mcf5282_fec_initialize_hardware(sc);
634
635	/*
636	* Start driver tasks
637	*/
638	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
639	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
640	}
641
642	/*
643	* Set flags appropriately
644	*/
645	if (ifp->if_flags & IFF_PROMISC)
646	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
647	else
648	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
649
650	/*
651	* Tell the world that we're running.
652	*/
653	ifp->if_flags \|= IFF_RUNNING;
654
655	/*
656	* Enable receiver and transmitter
657	*/
658	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
659	}
660
661
662	static void
663	fec_stop(struct mcf5282_enet_struct *sc)
664	{
665	struct ifnet *ifp = &sc->arpcom.ac_if;
666
667	ifp->if_flags &= ~IFF_RUNNING;
668
669	/*
670	* Shut down receiver and transmitter
671	*/
672	MCF5282_FEC_ECR = 0x0;
673	}
674
675	/*
676	* Show interface statistics
677	*/
678	static void
679	enet_stats(struct mcf5282_enet_struct *sc)
680	{
681	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
682	printf("Rx Packet Count:%-10lu", MCF5282_FEC_RMON_R_PACKETS);
683	printf(" Rx Broadcast:%-10lu\n", MCF5282_FEC_RMON_R_BC_PKT);
684	printf(" Rx Multicast:%-10lu", MCF5282_FEC_RMON_R_MC_PKT);
685	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_R_CRC_ALIGN);
686	printf(" Rx Undersize:%-10lu\n", MCF5282_FEC_RMON_R_UNDERSIZE);
687	printf(" Rx Oversize:%-10lu", MCF5282_FEC_RMON_R_OVERSIZE);
688	printf(" Rx Fragment:%-10lu", MCF5282_FEC_RMON_R_FRAG);
689	printf(" Rx Jabber:%-10lu\n", MCF5282_FEC_RMON_R_JAB);
690	printf(" Rx 64:%-10lu", MCF5282_FEC_RMON_R_P64);
691	printf(" Rx 65-127:%-10lu", MCF5282_FEC_RMON_R_P65T0127);
692	printf(" Rx 128-255:%-10lu\n", MCF5282_FEC_RMON_R_P128TO255);
693	printf(" Rx 256-511:%-10lu", MCF5282_FEC_RMON_R_P256TO511);
694	printf(" Rx 511-1023:%-10lu", MCF5282_FEC_RMON_R_P512TO1023);
695	printf(" Rx 1024-2047:%-10lu\n", MCF5282_FEC_RMON_R_P1024TO2047);
696	printf(" Rx >=2048:%-10lu", MCF5282_FEC_RMON_R_GTE2048);
697	printf(" Rx Octets:%-10lu", MCF5282_FEC_RMON_R_OCTETS);
698	printf(" Rx Dropped:%-10lu\n", MCF5282_FEC_IEEE_R_DROP);
699	printf(" Rx frame OK:%-10lu", MCF5282_FEC_IEEE_R_FRAME_OK);
700	printf(" Rx CRC error:%-10lu", MCF5282_FEC_IEEE_R_CRC);
701	printf(" Rx Align error:%-10lu\n", MCF5282_FEC_IEEE_R_ALIGN);
702	printf(" FIFO Overflow:%-10lu", MCF5282_FEC_IEEE_R_MACERR);
703	printf("Rx Pause Frames:%-10lu", MCF5282_FEC_IEEE_R_FDXFC);
704	printf(" Rx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_R_OCTETS_OK);
705	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
706	printf("Tx Output Waits:%-10lu", sc->txRawWait);
707	printf("Tx mbuf realign:%-10lu\n", sc->txRealign);
708	printf("Tx realign drop:%-10lu", sc->txRealignDrop);
709	printf(" Tx Unaccounted:%-10lu", MCF5282_FEC_RMON_T_DROP);
710	printf("Tx Packet Count:%-10lu\n", MCF5282_FEC_RMON_T_PACKETS);
711	printf(" Tx Broadcast:%-10lu", MCF5282_FEC_RMON_T_BC_PKT);
712	printf(" Tx Multicast:%-10lu", MCF5282_FEC_RMON_T_MC_PKT);
713	printf("CRC/Align error:%-10lu\n", MCF5282_FEC_RMON_T_CRC_ALIGN);
714	printf(" Tx Undersize:%-10lu", MCF5282_FEC_RMON_T_UNDERSIZE);
715	printf(" Tx Oversize:%-10lu", MCF5282_FEC_RMON_T_OVERSIZE);
716	printf(" Tx Fragment:%-10lu\n", MCF5282_FEC_RMON_T_FRAG);
717	printf(" Tx Jabber:%-10lu", MCF5282_FEC_RMON_T_JAB);
718	printf(" Tx Collisions:%-10lu", MCF5282_FEC_RMON_T_COL);
719	printf(" Tx 64:%-10lu\n", MCF5282_FEC_RMON_T_P64);
720	printf(" Tx 65-127:%-10lu", MCF5282_FEC_RMON_T_P65TO127);
721	printf(" Tx 128-255:%-10lu", MCF5282_FEC_RMON_T_P128TO255);
722	printf(" Tx 256-511:%-10lu\n", MCF5282_FEC_RMON_T_P256TO511);
723	printf(" Tx 511-1023:%-10lu", MCF5282_FEC_RMON_T_P512TO1023);
724	printf(" Tx 1024-2047:%-10lu", MCF5282_FEC_RMON_T_P1024TO2047);
725	printf(" Tx >=2048:%-10lu\n", MCF5282_FEC_RMON_T_P_GTE2048);
726	printf(" Tx Octets:%-10lu", MCF5282_FEC_RMON_T_OCTETS);
727	printf(" Tx Dropped:%-10lu", MCF5282_FEC_IEEE_T_DROP);
728	printf(" Tx Frame OK:%-10lu\n", MCF5282_FEC_IEEE_T_FRAME_OK);
729	printf(" Tx 1 Collision:%-10lu", MCF5282_FEC_IEEE_T_1COL);
730	printf("Tx >1 Collision:%-10lu", MCF5282_FEC_IEEE_T_MCOL);
731	printf(" Tx Deferred:%-10lu\n", MCF5282_FEC_IEEE_T_DEF);
732	printf(" Late Collision:%-10lu", MCF5282_FEC_IEEE_T_LCOL);
733	printf(" Excessive Coll:%-10lu", MCF5282_FEC_IEEE_T_EXCOL);
734	printf(" FIFO Underrun:%-10lu\n", MCF5282_FEC_IEEE_T_MACERR);
735	printf(" Carrier Error:%-10lu", MCF5282_FEC_IEEE_T_CSERR);
736	printf(" Tx SQE Error:%-10lu", MCF5282_FEC_IEEE_T_SQE);
737	printf("Tx Pause Frames:%-10lu\n", MCF5282_FEC_IEEE_T_FDXFC);
738	printf(" Tx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_T_OCTETS_OK);
739	printf(" EIR:%8.8lx ", MCF5282_FEC_EIR);
740	printf("EIMR:%8.8lx ", MCF5282_FEC_EIMR);
741	printf("RDAR:%8.8lx ", MCF5282_FEC_RDAR);
742	printf("TDAR:%8.8lx\n", MCF5282_FEC_TDAR);
743	printf(" ECR:%8.8lx ", MCF5282_FEC_ECR);
744	printf(" RCR:%8.8lx ", MCF5282_FEC_RCR);
745	printf(" TCR:%8.8lx\n", MCF5282_FEC_TCR);
746	printf("FRBR:%8.8lx ", MCF5282_FEC_FRBR);
747	printf("FRSR:%8.8lx\n", MCF5282_FEC_FRSR);
748	if (sc->txBdActiveCount != 0) {
749	int i, n;
750	/*
751	* Yes, there are races here with adding and retiring descriptors,
752	* but this diagnostic is more for when things have backed up.
753	*/
754	printf("Transmit Buffer Descriptors (Tail %d, Head %d, Unretired %d):\n",
755	sc->txBdTail,
756	sc->txBdHead,
757	sc->txBdActiveCount);
758	i = sc->txBdTail;
759	for (n = 0 ; n < sc->txBdCount ; n++) {
760	if ((sc->txBdBase[i].status & MCF5282_FEC_TxBD_R) != 0)
761	printf(" %3d: status:%4.4x length:%-4d buffer:%p\n",
762	i,
763	sc->txBdBase[i].status,
764	sc->txBdBase[i].length,
765	sc->txBdBase[i].buffer);
766	if (++i == sc->txBdCount)
767	i = 0;
768	}
769	}
770	}
771
772	static int
773	fec_ioctl(struct ifnet *ifp, int command, caddr_t data)
774	{
775	struct mcf5282_enet_struct *sc = ifp->if_softc;
776	int error = 0;
777
778	switch (command) {
779	case SIOCGIFADDR:
780	case SIOCSIFADDR:
781	ether_ioctl(ifp, command, data);
782	break;
783
784	case SIOCSIFFLAGS:
785	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
786	case IFF_RUNNING:
787	fec_stop(sc);
788	break;
789
790	case IFF_UP:
791	fec_init(sc);
792	break;
793
794	case IFF_UP \| IFF_RUNNING:
795	fec_stop(sc);
796	fec_init(sc);
797	break;
798
799	default:
800	break;
801	}
802	break;
803
804	case SIO_RTEMS_SHOW_STATS:
805	enet_stats(sc);
806	break;
807
808	/*
809	* FIXME: All sorts of multicast commands need to be added here!
810	*/
811	default:
812	error = EINVAL;
813	break;
814	}
815	return error;
816	}
817
818	int
819	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
820	{
821	struct mcf5282_enet_struct *sc;
822	struct ifnet *ifp;
823	int mtu;
824	int unitNumber;
825	char *unitName;
826	unsigned char *hwaddr;
827
828	/*
829	* Parse driver name
830	*/
831	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
832	return 0;
833
834	/*
835	* Is driver free?
836	*/
837	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
838	printf("Bad FEC unit number.\n");
839	return 0;
840	}
841	sc = &enet_driver[unitNumber - 1];
842	ifp = &sc->arpcom.ac_if;
843	if (ifp->if_softc != NULL) {
844	printf("Driver already in use.\n");
845	return 0;
846	}
847
848	/*
849	* Process options
850	*/
851	if (config->hardware_address) {
852	hwaddr = config->hardware_address;
853	} else if ((hwaddr = bsp_gethwaddr(unitNumber - 1)) == NULL) {
854	/* Locally-administered address */
855	static const unsigned char defaultAddress[ETHER_ADDR_LEN] = {
856	0x06, 'R', 'T', 'E', 'M', 'S'};
857	printf ("WARNING -- No %s%d Ethernet address specified "
858	"-- Using default address.\n", unitName, unitNumber);
859	hwaddr = defaultAddress;
860	}
861	printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n",
862	unitName, unitNumber,
863	hwaddr[0], hwaddr[1], hwaddr[2],
864	hwaddr[3], hwaddr[4], hwaddr[5]);
865	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
866
867	if (config->mtu)
868	mtu = config->mtu;
869	else
870	mtu = ETHERMTU;
871	if (config->rbuf_count)
872	sc->rxBdCount = config->rbuf_count;
873	else
874	sc->rxBdCount = RX_BUF_COUNT;
875	if (config->xbuf_count)
876	sc->txBdCount = config->xbuf_count;
877	else
878	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
879
880	sc->acceptBroadcast = !config->ignore_broadcast;
881
882	/*
883	* Set up network interface values
884	*/
885	ifp->if_softc = sc;
886	ifp->if_unit = unitNumber;
887	ifp->if_name = unitName;
888	ifp->if_mtu = mtu;
889	ifp->if_init = fec_init;
890	ifp->if_ioctl = fec_ioctl;
891	ifp->if_start = mcf5282_enet_start;
892	ifp->if_output = ether_output;
893	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
894	if (ifp->if_snd.ifq_maxlen == 0)
895	ifp->if_snd.ifq_maxlen = ifqmaxlen;
896
897	/*
898	* Attach the interface
899	*/
900	if_attach(ifp);
901	ether_ifattach(ifp);
902	return 1;
903	};
904

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