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source: rtems/c/src/lib/libbsp/m68k/uC5282/network/network.c @ 518edef

4.104.114.84.95

Last change on this file since 518edef was 518edef, checked in by Eric Norum <WENorum@…>, on 01/31/05 at 19:03:41
Processor doesn't snoop FEC DMA so we must invalidate the cache appropriately.
Property mode set to `100644`
File size: 25.9 KB

Line
1	/*
2	* RTEMS/TCPIP driver for MCF5282 Fast Ethernet Controller
3	*
4	* TO DO: MII communications to set speed, full/half duplex, etc.
5	* TO DO: Check network stack code -- force longword alignment of all tx mbufs?
6	*/
7
8	#include <bsp.h>
9	#include <stdio.h>
10	#include <errno.h>
11	#include <stdarg.h>
12	#include <string.h>
13	#include <rtems.h>
14	#include <rtems/error.h>
15	#include <rtems/rtems_bsdnet.h>
16
17	#include <sys/param.h>
18	#include <sys/mbuf.h>
19	#include <sys/socket.h>
20	#include <sys/sockio.h>
21
22	#include <net/ethernet.h>
23	#include <net/if.h>
24
25	#include <netinet/in.h>
26	#include <netinet/if_ether.h>
27
28
29	/*
30	* Number of interfaces supported by this driver
31	*/
32	#define NIFACES 1
33
34	#define FEC_INTC0_TX_VECTOR (64+23)
35	#define FEC_INTC0_RX_VECTOR (64+27)
36
37	/*
38	* Default number of buffer descriptors set aside for this driver.
39	* The number of transmit buffer descriptors has to be quite large
40	* since a single frame often uses three or more buffer descriptors.
41	*/
42	#define RX_BUF_COUNT 32
43	#define TX_BUF_COUNT 20
44	#define TX_BD_PER_BUF 3
45
46	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
47
48	/*
49	* RTEMS event used by interrupt handler to signal daemons.
50	* This must not be the same event used by the TCP/IP task synchronization.
51	*/
52	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
53	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
54
55	/*
56	* RTEMS event used to start transmit daemon.
57	* This must not be the same as INTERRUPT_EVENT.
58	*/
59	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
60
61	/*
62	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
63	* Round off to nearest multiple of RBUF_ALIGN.
64	*/
65	#define MAX_MTU_SIZE 1518
66	#define RBUF_ALIGN 4
67	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
68
69	#if (MCLBYTES < RBUF_SIZE)
70	#error "Driver must have MCLBYTES > RBUF_SIZE"
71	#endif
72
73	typedef struct mcf5282BufferDescriptor_ {
74	volatile rtems_unsigned16 status;
75	rtems_unsigned16 length;
76	volatile void *buffer;
77	} mcf5282BufferDescriptor_t;
78
79	/*
80	* Per-device data
81	*/
82	struct mcf5282_enet_struct {
83	struct arpcom arpcom;
84	struct mbuf **rxMbuf;
85	struct mbuf **txMbuf;
86	int acceptBroadcast;
87	int rxBdCount;
88	int txBdCount;
89	int txBdHead;
90	int txBdTail;
91	int txBdActiveCount;
92	mcf5282BufferDescriptor_t *rxBdBase;
93	mcf5282BufferDescriptor_t *txBdBase;
94	rtems_id rxDaemonTid;
95	rtems_id txDaemonTid;
96
97	/*
98	* Statistics
99	*/
100	unsigned long rxInterrupts;
101	unsigned long txInterrupts;
102	unsigned long txRawWait;
103	unsigned long txRealign;
104	};
105	static struct mcf5282_enet_struct enet_driver[NIFACES];
106
107	static rtems_isr
108	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
109	{
110	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
111	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
112	enet_driver[0].rxInterrupts++;
113	rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
114	}
115
116	static rtems_isr
117	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
118	{
119	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
120	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
121	enet_driver[0].txInterrupts++;
122	rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
123	}
124
125	/*
126	* Allocate buffer descriptors
127	* Ensure 128-bit (16-byte) alignment
128	*/
129	static mcf5282BufferDescriptor_t *
130	mcf5282_bd_allocate(unsigned int count)
131	{
132	mcf5282BufferDescriptor_t *p;
133
134	p = malloc((count * sizeof(mcf5282BufferDescriptor_t)) + 15, 0, M_NOWAIT);
135	if (!p)
136	rtems_panic("FEC BD");
137	if ((int)p & 0xF)
138	p = (mcf5282BufferDescriptor_t )((char )p + (16 - ((int)p & 0xF)));
139	return p;
140	}
141
142	/*
143	* Retrieve MAC address from bootloader environment variable area.
144	* Parameter is interface number (0 or 1).
145	*/
146	static unsigned char *
147	gethwaddr(int a)
148	{
149	register long __res __asm__ ("%d2") = 12;
150	register long __a __asm__ ("%d1") = (long)a;
151	__asm__ __volatile__ ("trap #2" \
152	: "=g" (__res) \
153	: "0" (__res), "d" (__a) \
154	: "%d0");
155	return (unsigned char *)(__res);
156	}
157
158	static void
159	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
160	{
161	int i;
162	unsigned char *hwaddr;
163	rtems_status_code status;
164	rtems_isr_entry old_handler;
165	unsigned32 clock_speed = get_CPU_clock_speed();
166
167	/* extern struct rtems_bsdnet_ifconfig netdriver_config; */
168
169
170	/*
171	* Issue reset to FEC
172	*/
173	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
174	rtems_task_wake_after(1);
175	/*
176	* Configuration of I/O ports is done outside of this function
177	*/
178	#if 0
179	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
180	#endif
181
182	/*
183	* Set our physical address
184	*/
185	hwaddr = sc->arpcom.ac_enaddr;
186	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
187	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
188	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
189
190
191	/*
192	* Clear the hash table
193	*/
194	MCF5282_FEC_GAUR = 0;
195	MCF5282_FEC_GALR = 0;
196
197	/*
198	* Set up receive buffer size
199	*/
200	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
201
202	/*
203	* Allocate mbuf pointers
204	*/
205	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
206	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
207	if (!sc->rxMbuf \|\| !sc->txMbuf)
208	rtems_panic("No memory for mbuf pointers");
209
210	/*
211	* Set receiver and transmitter buffer descriptor bases
212	*/
213	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
214	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
215	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
216	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
217
218	/*
219	* Set up Receive Control Register:
220	* Not promiscuous
221	* MII mode
222	* Half duplex
223	* No loopback
224	*/
225	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
226	MCF5282_FEC_RCR_MII_MODE \|
227	MCF5282_FEC_RCR_DRT;
228
229	/*
230	* Set up Transmit Control Register:
231	* Half duplex
232	* No heartbeat
233	*/
234	MCF5282_FEC_TCR = 0;
235
236	/*
237	* Initialize statistic counters
238	*/
239	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
240	{
241	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
242	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
243	*vuip++ = 0;
244	}
245	MCF5282_FEC_MIBC = 0;
246
247	/*
248	* Set MII speed to <2.5 MHz
249	*/
250	if (clock_speed <= 25000000)
251	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x5);
252	else if (clock_speed <= 33000000)
253	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x7);
254	else if (clock_speed <= 40000000)
255	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0x8);
256	else if (clock_speed <= 50000000)
257	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xA);
258	else if (clock_speed <= 66000000)
259	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xD);
260	else
261	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(0xF);
262
263	/*
264	* Set up receive buffer descriptors
265	*/
266	for (i = 0 ; i < sc->rxBdCount ; i++)
267	(sc->rxBdBase + i)->status = 0;
268
269	/*
270	* Set up transmit buffer descriptors
271	*/
272	for (i = 0 ; i < sc->txBdCount ; i++) {
273	sc->txBdBase[i].status = 0;
274	sc->txMbuf[i] = NULL;
275	}
276	sc->txBdHead = sc->txBdTail = 0;
277	sc->txBdActiveCount = 0;
278
279	/*
280	* Set up interrupts
281	*/
282	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
283	if (status != RTEMS_SUCCESSFUL)
284	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
285	rtems_status_text(status));
286	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
287	if (status != RTEMS_SUCCESSFUL)
288	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
289	rtems_status_text(status));
290	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
291	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
292	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
293	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
294	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
295	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
296	}
297
298	/*
299	* Soak up buffer descriptors that have been sent.
300	*/
301	static void
302	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
303	{
304	struct mbuf m, n;
305	volatile mcf5282BufferDescriptor_t *txBd;
306
307	for (;;) {
308	if (sc->txBdActiveCount == 0)
309	return;
310	txBd = sc->txBdBase + sc->txBdTail;
311	rtems_cache_invalidate_multiple_data_lines(txBd, sizeof *txBd);
312	if ((txBd->status & MCF5282_FEC_TxBD_R) != 0)
313	return;
314	m = sc->txMbuf[sc->txBdTail];
315	MFREE(m, n);
316	if (++sc->txBdTail == sc->txBdCount)
317	sc->txBdTail = 0;
318	sc->txBdActiveCount--;
319	}
320	}
321
322	static void
323	fec_rxDaemon (void *arg)
324	{
325	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
326	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
327	struct mbuf *m;
328	volatile rtems_unsigned16 status;
329	volatile mcf5282BufferDescriptor_t *rxBd;
330	int rxBdIndex;
331
332	/*
333	* Allocate space for incoming packets and start reception
334	*/
335	for (rxBdIndex = 0 ; ;) {
336	rxBd = sc->rxBdBase + rxBdIndex;
337	MGETHDR(m, M_WAIT, MT_DATA);
338	MCLGET(m, M_WAIT);
339	m->m_pkthdr.rcvif = ifp;
340	sc->rxMbuf[rxBdIndex] = m;
341	rxBd->buffer = mtod(m, void *);
342	rxBd->status = MCF5282_FEC_RxBD_E;
343	if (++rxBdIndex == sc->rxBdCount) {
344	rxBd->status \|= MCF5282_FEC_RxBD_W;
345	break;
346	}
347	}
348
349	/*
350	* Input packet handling loop
351	*/
352	/* Indicate we have some ready buffers available */
353	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
354
355	rxBdIndex = 0;
356	for (;;) {
357	rxBd = sc->rxBdBase + rxBdIndex;
358
359	/*
360	* Wait for packet if there's not one ready
361	*/
362	rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
363	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
364	int chkCount=0 ;
365	/*
366	* Clear old events.
367	*/
368	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
369
370	/*
371	* Wait for packet to arrive.
372	* Check the buffer descriptor before waiting for the event.
373	* This catches the case when a packet arrives between the
374	* `if' above, and the clearing of the RXF bit in the EIR.
375	*/
376	for (;;) {
377	rtems_event_set events;
378	int level;
379
380	rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
381	if (((status = rxBd->status) & MCF5282_FEC_RxBD_E) == 0)
382	break;
383
384	if(chkCount++)printf("ACK -- CACHE WOES\n");
385	rtems_interrupt_disable(level);
386	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
387	rtems_interrupt_enable(level);
388	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
389	RTEMS_WAIT\|RTEMS_EVENT_ANY,
390	RTEMS_NO_TIMEOUT,
391	&events);
392	}
393	}
394
395	/*
396	* Check that packet is valid
397	*/
398	if (status & MCF5282_FEC_RxBD_L) {
399	/*
400	* Pass the packet up the chain.
401	* FIXME: Packet filtering hook could be done here.
402	*/
403	struct ether_header *eh;
404	int len = rxBd->length - sizeof(rtems_unsigned32);;
405
406	/*
407	* Invalidate the cache and push the packet up
408	* The cache is so small that it's more efficient to just
409	* invalidate the whole thing unless the packet is very small.
410	*/
411	m = sc->rxMbuf[rxBdIndex];
412	if (len < 128)
413	rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
414	else
415	rtems_cache_invalidate_entire_data();
416	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
417	eh = mtod(m, struct ether_header *);
418	m->m_data += sizeof(struct ether_header);
419	ether_input(ifp, eh, m);
420
421	/*
422	* Allocate a new mbuf
423	*/
424	MGETHDR(m, M_WAIT, MT_DATA);
425	MCLGET(m, M_WAIT);
426	m->m_pkthdr.rcvif = ifp;
427	sc->rxMbuf[rxBdIndex] = m;
428	rxBd->buffer = mtod(m, void *);
429	}
430
431	/*
432	* Reenable the buffer descriptor
433	*/
434	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
435	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
436
437	/*
438	* Move to next buffer descriptor
439	*/
440	if (++rxBdIndex == sc->rxBdCount)
441	rxBdIndex = 0;
442	}
443	}
444
445	static void
446	fec_sendpacket(struct ifnet ifp, struct mbuf m)
447	{
448	struct mcf5282_enet_struct *sc = ifp->if_softc;
449	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
450	rtems_unsigned16 status;
451	int nAdded;
452
453	/*
454	* Free up buffer descriptors
455	*/
456	fec_retire_tx_bd(sc);
457
458	/*
459	* Set up the transmit buffer descriptors.
460	* No need to pad out short packets since the
461	* hardware takes care of that automatically.
462	* No need to copy the packet to a contiguous buffer
463	* since the hardware is capable of scatter/gather DMA.
464	*/
465	nAdded = 0;
466	firstTxBd = sc->txBdBase + sc->txBdHead;
467
468	for (;;) {
469	/*
470	* Wait for buffer descriptor to become available
471	*/
472	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
473	/*
474	* Clear old events.
475	*/
476	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
477
478	/*
479	* Wait for buffer descriptor to become available.
480	* Check for buffer descriptors before waiting for the event.
481	* This catches the case when a buffer became available between
482	* the `if' above, and the clearing of the TXF bit in the EIR.
483	*/
484	fec_retire_tx_bd(sc);
485	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
486	rtems_event_set events;
487	int level;
488
489	rtems_interrupt_disable(level);
490	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
491	rtems_interrupt_enable(level);
492	sc->txRawWait++;
493	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
494	RTEMS_WAIT\|RTEMS_EVENT_ANY,
495	RTEMS_NO_TIMEOUT,
496	&events);
497	fec_retire_tx_bd(sc);
498	}
499	}
500
501	/*
502	* Don't set the READY flag on the first fragment
503	* until the whole packet has been readied.
504	*/
505	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
506
507	/*
508	* The IP fragmentation routine in ip_output
509	* can produce fragments with zero length.
510	*/
511	txBd = sc->txBdBase + sc->txBdHead;
512	if (m->m_len) {
513	char p = mtod(m, char );
514	/*
515	* Stupid FEC can't handle misaligned data!
516	* Given the way that mbuf's are layed out it should be
517	* safe to shuffle the data down like this.....
518	* Perhaps this code could be improved with a "Duff's Device".
519	*/
520	if ((int)p & 0x3) {
521	int l = m->m_len;
522	char *dest = p - ((int)p & 0x3);
523	unsigned16 o = (unsigned16 )dest, i = (unsigned16 )p;
524	while (l > 0) {
525	o++ = i++;
526	l -= sizeof(unsigned16);
527	}
528	p = dest;
529	sc->txRealign++;
530	}
531	txBd->buffer = p;
532	txBd->length = m->m_len;
533	sc->txMbuf[sc->txBdHead] = m;
534	nAdded++;
535	if (++sc->txBdHead == sc->txBdCount) {
536	status \|= MCF5282_FEC_TxBD_W;
537	sc->txBdHead = 0;
538	}
539	m = m->m_next;
540	}
541	else {
542	/*
543	* Just toss empty mbufs
544	*/
545	struct mbuf *n;
546	MFREE(m, n);
547	m = n;
548	}
549	if (m == NULL) {
550	if (nAdded) {
551	txBd->status = status \| MCF5282_FEC_TxBD_R
552	\| MCF5282_FEC_TxBD_L
553	\| MCF5282_FEC_TxBD_TC;
554	if (nAdded > 1)
555	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
556	MCF5282_FEC_TDAR = MCF5282_FEC_TDAR_X_DES_ACTIVE;
557	sc->txBdActiveCount += nAdded;
558	}
559	break;
560	}
561	txBd->status = status;
562	}
563	}
564
565	void
566	fec_txDaemon(void *arg)
567	{
568	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
569	struct ifnet *ifp = &sc->arpcom.ac_if;
570	struct mbuf *m;
571	rtems_event_set events;
572
573	for (;;) {
574	/*
575	* Wait for packet
576	*/
577	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
578	RTEMS_EVENT_ANY \| RTEMS_WAIT,
579	RTEMS_NO_TIMEOUT,
580	&events);
581
582	/*
583	* Send packets till queue is empty
584	*/
585	for (;;) {
586	/*
587	* Get the next mbuf chain to transmit.
588	*/
589	IF_DEQUEUE(&ifp->if_snd, m);
590	if (!m)
591	break;
592	fec_sendpacket(ifp, m);
593	}
594	ifp->if_flags &= ~IFF_OACTIVE;
595	}
596	}
597
598
599	/*
600	* Send packet (caller provides header).
601	*/
602	static void
603	mcf5282_enet_start(struct ifnet *ifp)
604	{
605	struct mcf5282_enet_struct *sc = ifp->if_softc;
606
607	rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
608	ifp->if_flags \|= IFF_OACTIVE;
609	}
610
611	static void
612	fec_init(void *arg)
613	{
614	struct mcf5282_enet_struct *sc = arg;
615	struct ifnet *ifp = &sc->arpcom.ac_if;
616
617	if (sc->txDaemonTid == 0) {
618	/*
619	* Set up hardware
620	*/
621	mcf5282_fec_initialize_hardware(sc);
622
623	/*
624	* Start driver tasks
625	*/
626	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
627	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
628	}
629
630	/*
631	* Set flags appropriately
632	*/
633	if (ifp->if_flags & IFF_PROMISC)
634	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
635	else
636	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
637
638	/*
639	* Tell the world that we're running.
640	*/
641	ifp->if_flags \|= IFF_RUNNING;
642
643	/*
644	* Enable receiver and transmitter
645	*/
646	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
647	}
648
649
650	static void
651	fec_stop(struct mcf5282_enet_struct *sc)
652	{
653	struct ifnet *ifp = &sc->arpcom.ac_if;
654
655	ifp->if_flags &= ~IFF_RUNNING;
656
657	/*
658	* Shut down receiver and transmitter
659	*/
660	MCF5282_FEC_ECR = 0x0;
661	}
662
663	/*
664	* Show interface statistics
665	*/
666	static void
667	enet_stats(struct mcf5282_enet_struct *sc)
668	{
669	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
670	printf("Rx Packet Count:%-10lu", MCF5282_FEC_RMON_R_PACKETS);
671	printf(" Rx Broadcast:%-10lu\n", MCF5282_FEC_RMON_R_BC_PKT);
672	printf(" Rx Multicast:%-10lu", MCF5282_FEC_RMON_R_MC_PKT);
673	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_R_CRC_ALIGN);
674	printf(" Rx Undersize:%-10lu\n", MCF5282_FEC_RMON_R_UNDERSIZE);
675	printf(" Rx Oversize:%-10lu", MCF5282_FEC_RMON_R_OVERSIZE);
676	printf(" Rx Fragment:%-10lu", MCF5282_FEC_RMON_R_FRAG);
677	printf(" Rx Jabber:%-10lu\n", MCF5282_FEC_RMON_R_JAB);
678	printf(" Rx 64:%-10lu", MCF5282_FEC_RMON_R_P64);
679	printf(" Rx 65-127:%-10lu", MCF5282_FEC_RMON_R_P65T0127);
680	printf(" Rx 128-255:%-10lu\n", MCF5282_FEC_RMON_R_P128TO255);
681	printf(" Rx 256-511:%-10lu", MCF5282_FEC_RMON_R_P256TO511);
682	printf(" Rx 511-1023:%-10lu", MCF5282_FEC_RMON_R_P512TO1023);
683	printf(" Rx 1024-2047:%-10lu\n", MCF5282_FEC_RMON_R_P1024TO2047);
684	printf(" Rx >=2048:%-10lu", MCF5282_FEC_RMON_R_GTE2048);
685	printf(" Rx Octets:%-10lu", MCF5282_FEC_RMON_R_OCTETS);
686	printf(" Rx Dropped:%-10lu\n", MCF5282_FEC_IEEE_R_DROP);
687	printf(" Rx frame OK:%-10lu", MCF5282_FEC_IEEE_R_FRAME_OK);
688	printf(" Rx CRC error:%-10lu", MCF5282_FEC_IEEE_R_CRC);
689	printf(" Rx Align error:%-10lu\n", MCF5282_FEC_IEEE_R_ALIGN);
690	printf(" FIFO Overflow:%-10lu", MCF5282_FEC_IEEE_R_MACERR);
691	printf("Rx Pause Frames:%-10lu", MCF5282_FEC_IEEE_R_FDXFC);
692	printf(" Rx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_R_OCTETS_OK);
693	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
694	printf("Tx Output Waits:%-10lu", sc->txRawWait);
695	printf("Tx Realignments:%-10lu\n", sc->txRealign);
696	printf(" Tx Unaccounted:%-10lu", MCF5282_FEC_RMON_T_DROP);
697	printf("Tx Packet Count:%-10lu", MCF5282_FEC_RMON_T_PACKETS);
698	printf(" Tx Broadcast:%-10lu\n", MCF5282_FEC_RMON_T_BC_PKT);
699	printf(" Tx Multicast:%-10lu", MCF5282_FEC_RMON_T_MC_PKT);
700	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_T_CRC_ALIGN);
701	printf(" Tx Undersize:%-10lu\n", MCF5282_FEC_RMON_T_UNDERSIZE);
702	printf(" Tx Oversize:%-10lu", MCF5282_FEC_RMON_T_OVERSIZE);
703	printf(" Tx Fragment:%-10lu", MCF5282_FEC_RMON_T_FRAG);
704	printf(" Tx Jabber:%-10lu\n", MCF5282_FEC_RMON_T_JAB);
705	printf(" Tx Collisions:%-10lu", MCF5282_FEC_RMON_T_COL);
706	printf(" Tx 64:%-10lu", MCF5282_FEC_RMON_T_P64);
707	printf(" Tx 65-127:%-10lu\n", MCF5282_FEC_RMON_T_P65TO127);
708	printf(" Tx 128-255:%-10lu", MCF5282_FEC_RMON_T_P128TO255);
709	printf(" Tx 256-511:%-10lu", MCF5282_FEC_RMON_T_P256TO511);
710	printf(" Tx 511-1023:%-10lu\n", MCF5282_FEC_RMON_T_P512TO1023);
711	printf(" Tx 1024-2047:%-10lu", MCF5282_FEC_RMON_T_P1024TO2047);
712	printf(" Tx >=2048:%-10lu", MCF5282_FEC_RMON_T_P_GTE2048);
713	printf(" Tx Octets:%-10lu\n", MCF5282_FEC_RMON_T_OCTETS);
714	printf(" Tx Dropped:%-10lu", MCF5282_FEC_IEEE_T_DROP);
715	printf(" Tx Frame OK:%-10lu", MCF5282_FEC_IEEE_T_FRAME_OK);
716	printf(" Tx 1 Collision:%-10lu\n", MCF5282_FEC_IEEE_T_1COL);
717	printf("Tx >1 Collision:%-10lu", MCF5282_FEC_IEEE_T_MCOL);
718	printf(" Tx Deferred:%-10lu", MCF5282_FEC_IEEE_T_DEF);
719	printf(" Late Collision:%-10lu\n", MCF5282_FEC_IEEE_T_LCOL);
720	printf(" Excessive Coll:%-10lu", MCF5282_FEC_IEEE_T_EXCOL);
721	printf(" FIFO Underrun:%-10lu", MCF5282_FEC_IEEE_T_MACERR);
722	printf(" Carrier Error:%-10lu\n", MCF5282_FEC_IEEE_T_CSERR);
723	printf(" Tx SQE Error:%-10lu", MCF5282_FEC_IEEE_T_SQE);
724	printf("Tx Pause Frames:%-10lu", MCF5282_FEC_IEEE_T_FDXFC);
725	printf(" Tx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_T_OCTETS_OK);
726	}
727
728	static int
729	fec_ioctl(struct ifnet *ifp, int command, caddr_t data)
730	{
731	struct mcf5282_enet_struct *sc = ifp->if_softc;
732	int error = 0;
733
734	switch (command) {
735	case SIOCGIFADDR:
736	case SIOCSIFADDR:
737	ether_ioctl(ifp, command, data);
738	break;
739
740	case SIOCSIFFLAGS:
741	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
742	case IFF_RUNNING:
743	fec_stop(sc);
744	break;
745
746	case IFF_UP:
747	fec_init(sc);
748	break;
749
750	case IFF_UP \| IFF_RUNNING:
751	fec_stop(sc);
752	fec_init(sc);
753	break;
754
755	default:
756	break;
757	}
758	break;
759
760	case SIO_RTEMS_SHOW_STATS:
761	enet_stats(sc);
762	break;
763
764	/*
765	* FIXME: All sorts of multicast commands need to be added here!
766	*/
767	default:
768	error = EINVAL;
769	break;
770	}
771	return error;
772	}
773
774	int
775	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
776	{
777	struct mcf5282_enet_struct *sc;
778	struct ifnet *ifp;
779	int mtu;
780	int unitNumber;
781	char *unitName;
782	unsigned char *hwaddr;
783
784	/*
785	* Parse driver name
786	*/
787	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
788	return 0;
789
790	/*
791	* Is driver free?
792	*/
793	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
794	printf("Bad FECC unit number.\n");
795	return 0;
796	}
797	sc = &enet_driver[unitNumber - 1];
798	ifp = &sc->arpcom.ac_if;
799	if (ifp->if_softc != NULL) {
800	printf("Driver already in use.\n");
801	return 0;
802	}
803
804	/*
805	* Process options
806	*/
807	if (config->hardware_address)
808	hwaddr = config->hardware_address;
809	else
810	hwaddr = gethwaddr(unitNumber - 1);
811	printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n",
812	unitName, unitNumber,
813	hwaddr[0], hwaddr[1], hwaddr[2],
814	hwaddr[3], hwaddr[4], hwaddr[5]);
815	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
816
817	if (config->mtu)
818	mtu = config->mtu;
819	else
820	mtu = ETHERMTU;
821	if (config->rbuf_count)
822	sc->rxBdCount = config->rbuf_count;
823	else
824	sc->rxBdCount = RX_BUF_COUNT;
825	if (config->xbuf_count)
826	sc->txBdCount = config->xbuf_count;
827	else
828	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
829
830	sc->acceptBroadcast = !config->ignore_broadcast;
831
832	/*
833	* Set up network interface values
834	*/
835	ifp->if_softc = sc;
836	ifp->if_unit = unitNumber;
837	ifp->if_name = unitName;
838	ifp->if_mtu = mtu;
839	ifp->if_init = fec_init;
840	ifp->if_ioctl = fec_ioctl;
841	ifp->if_start = mcf5282_enet_start;
842	ifp->if_output = ether_output;
843	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
844	if (ifp->if_snd.ifq_maxlen == 0)
845	ifp->if_snd.ifq_maxlen = ifqmaxlen;
846
847	/*
848	* Attach the interface
849	*/
850	if_attach(ifp);
851	ether_ifattach(ifp);
852	return 1;
853	};
854

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