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source: rtems/c/src/lib/libbsp/m68k/uC5282/network/network.c @ 50269c46

4.104.114.84.95

Last change on this file since 50269c46 was 0b2c943, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/04/05 at 08:46:43

2005-02-04 Ralf Corsepius <ralf.corsepius@…>

console/console.c, include/bsp.h, network/network.c, startup/bspstart.c: Remove obsolete fixed size types.

Property mode set to 100644

File size: 26.0 KB

Line
1	/*
2	* RTEMS/TCPIP driver for MCF5282 Fast Ethernet Controller
3	*
4	* TO DO: Check network stack code -- force longword alignment of all tx mbufs?
5	*/
6
7	#include <bsp.h>
8	#include <stdio.h>
9	#include <errno.h>
10	#include <stdarg.h>
11	#include <string.h>
12	#include <rtems.h>
13	#include <rtems/error.h>
14	#include <rtems/rtems_bsdnet.h>
15
16	#include <sys/param.h>
17	#include <sys/mbuf.h>
18	#include <sys/socket.h>
19	#include <sys/sockio.h>
20
21	#include <net/ethernet.h>
22	#include <net/if.h>
23
24	#include <netinet/in.h>
25	#include <netinet/if_ether.h>
26
27
28	/*
29	* Number of interfaces supported by this driver
30	*/
31	#define NIFACES 1
32
33	#define FEC_INTC0_TX_VECTOR (64+23)
34	#define FEC_INTC0_RX_VECTOR (64+27)
35
36	/*
37	* Default number of buffer descriptors set aside for this driver.
38	* The number of transmit buffer descriptors has to be quite large
39	* since a single frame often uses three or more buffer descriptors.
40	*/
41	#define RX_BUF_COUNT 32
42	#define TX_BUF_COUNT 20
43	#define TX_BD_PER_BUF 3
44
45	#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
46
47	/*
48	* RTEMS event used by interrupt handler to signal daemons.
49	* This must not be the same event used by the TCP/IP task synchronization.
50	*/
51	#define TX_INTERRUPT_EVENT RTEMS_EVENT_1
52	#define RX_INTERRUPT_EVENT RTEMS_EVENT_1
53
54	/*
55	* RTEMS event used to start transmit daemon.
56	* This must not be the same as INTERRUPT_EVENT.
57	*/
58	#define START_TRANSMIT_EVENT RTEMS_EVENT_2
59
60	/*
61	* Receive buffer size -- Allow for a full ethernet packet plus CRC (1518).
62	* Round off to nearest multiple of RBUF_ALIGN.
63	*/
64	#define MAX_MTU_SIZE 1518
65	#define RBUF_ALIGN 4
66	#define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN)
67
68	#if (MCLBYTES < RBUF_SIZE)
69	#error "Driver must have MCLBYTES > RBUF_SIZE"
70	#endif
71
72	typedef struct mcf5282BufferDescriptor_ {
73	volatile uint16_t status;
74	uint16_t length;
75	volatile void *buffer;
76	} mcf5282BufferDescriptor_t;
77
78	/*
79	* Per-device data
80	*/
81	struct mcf5282_enet_struct {
82	struct arpcom arpcom;
83	struct mbuf **rxMbuf;
84	struct mbuf **txMbuf;
85	int acceptBroadcast;
86	int rxBdCount;
87	int txBdCount;
88	int txBdHead;
89	int txBdTail;
90	int txBdActiveCount;
91	mcf5282BufferDescriptor_t *rxBdBase;
92	mcf5282BufferDescriptor_t *txBdBase;
93	rtems_id rxDaemonTid;
94	rtems_id txDaemonTid;
95
96	/*
97	* Statistics
98	*/
99	unsigned long rxInterrupts;
100	unsigned long txInterrupts;
101	unsigned long txRawWait;
102	unsigned long txRealign;
103	};
104	static struct mcf5282_enet_struct enet_driver[NIFACES];
105
106	static rtems_isr
107	mcf5282_fec_rx_interrupt_handler( rtems_vector_number v )
108	{
109	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
110	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF;
111	enet_driver[0].rxInterrupts++;
112	rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT);
113	}
114
115	static rtems_isr
116	mcf5282_fec_tx_interrupt_handler( rtems_vector_number v )
117	{
118	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
119	MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF;
120	enet_driver[0].txInterrupts++;
121	rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT);
122	}
123
124	/*
125	* Allocate buffer descriptors from (non-cached) on-chip static RAM
126	* Ensure 128-bit (16-byte) alignment
127	*/
128	static mcf5282BufferDescriptor_t *
129	mcf5282_bd_allocate(unsigned int count)
130	{
131	extern char __SRAMBASE[];
132	static mcf5282BufferDescriptor_t bdp = (mcf5282BufferDescriptor_t )__SRAMBASE;
133	mcf5282BufferDescriptor_t *p = bdp;
134
135	bdp += count;
136	if ((int)bdp & 0xF)
137	bdp = (mcf5282BufferDescriptor_t )((char )bdp + (16 - ((int)bdp & 0xF)));
138	return p;
139	}
140
141	#if UNUSED
142	/*
143	* Read MII register
144	* Busy-waits, but transfer time should be short!
145	*/
146	static int
147	getMII(int phyNumber, int regNumber)
148	{
149	MCF5282_FEC_MMFR = (0x1 << 30) \|
150	(0x2 << 28) \|
151	(phyNumber << 23) \|
152	(regNumber << 18) \|
153	(0x2 << 16);
154	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
155	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
156	return MCF5282_FEC_MMFR & 0xFFFF;
157	}
158	#endif
159
160	/*
161	* Write MII register
162	* Busy-waits, but transfer time should be short!
163	*/
164	static void
165	setMII(int phyNumber, int regNumber, int value)
166	{
167	MCF5282_FEC_MMFR = (0x1 << 30) \|
168	(0x1 << 28) \|
169	(phyNumber << 23) \|
170	(regNumber << 18) \|
171	(0x2 << 16) \|
172	(value & 0xFFFF);
173	while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0);
174	MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII;
175	}
176
177	static void
178	mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc)
179	{
180	int i;
181	const unsigned char *hwaddr;
182	rtems_status_code status;
183	rtems_isr_entry old_handler;
184	uint32_t clock_speed = bsp_get_CPU_clock_speed();
185
186	/*
187	* Issue reset to FEC
188	*/
189	MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET;
190	rtems_task_wake_after(1);
191	MCF5282_FEC_ECR = 0;
192
193	/*
194	* Configuration of I/O ports is done outside of this function
195	*/
196	#if 0
197	imm->gpio.pbcnt \|= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */
198	#endif
199
200	/*
201	* Set our physical address
202	*/
203	hwaddr = sc->arpcom.ac_enaddr;
204	MCF5282_FEC_PALR = (hwaddr[0] << 24) \| (hwaddr[1] << 16) \|
205	(hwaddr[2] << 8) \| (hwaddr[3] << 0);
206	MCF5282_FEC_PAUR = (hwaddr[4] << 24) \| (hwaddr[5] << 16);
207
208
209	/*
210	* Clear the hash table
211	*/
212	MCF5282_FEC_GAUR = 0;
213	MCF5282_FEC_GALR = 0;
214
215	/*
216	* Set up receive buffer size
217	*/
218	MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */
219
220	/*
221	* Allocate mbuf pointers
222	*/
223	sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT);
224	sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT);
225	if (!sc->rxMbuf \|\| !sc->txMbuf)
226	rtems_panic("No memory for mbuf pointers");
227
228	/*
229	* Set receiver and transmitter buffer descriptor bases
230	*/
231	sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount);
232	sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount);
233	MCF5282_FEC_ERDSR = (int)sc->rxBdBase;
234	MCF5282_FEC_ETDSR = (int)sc->txBdBase;
235
236	/*
237	* Set up Receive Control Register:
238	* Not promiscuous
239	* MII mode
240	* Full duplex
241	* No loopback
242	*/
243	MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) \|
244	MCF5282_FEC_RCR_MII_MODE;
245
246	/*
247	* Set up Transmit Control Register:
248	* Full duplex
249	* No heartbeat
250	*/
251	MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN;
252
253	/*
254	* Initialize statistic counters
255	*/
256	MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE;
257	{
258	vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP;
259	while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK)
260	*vuip++ = 0;
261	}
262	MCF5282_FEC_MIBC = 0;
263
264	/*
265	* Set MII speed to <= 2.5 MHz
266	*/
267	i = (clock_speed + 5000000 - 1) / 5000000;
268	MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i);
269
270	/*
271	* Set PHYS to 100 Mb/s, full duplex
272	*/
273	setMII(1, 0, 0x2100);
274
275	/*
276	* Set up receive buffer descriptors
277	*/
278	for (i = 0 ; i < sc->rxBdCount ; i++)
279	(sc->rxBdBase + i)->status = 0;
280
281	/*
282	* Set up transmit buffer descriptors
283	*/
284	for (i = 0 ; i < sc->txBdCount ; i++) {
285	sc->txBdBase[i].status = 0;
286	sc->txMbuf[i] = NULL;
287	}
288	sc->txBdHead = sc->txBdTail = 0;
289	sc->txBdActiveCount = 0;
290
291	/*
292	* Set up interrupts
293	*/
294	status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler );
295	if (status != RTEMS_SUCCESSFUL)
296	rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n",
297	rtems_status_text(status));
298	status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler);
299	if (status != RTEMS_SUCCESSFUL)
300	rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n",
301	rtems_status_text(status));
302	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY);
303	MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
304	MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY);
305	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 \| MCF5282_INTC_IMRL_MASKALL);
306	bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY);
307	MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) \|
308	MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY);
309	MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 \| MCF5282_INTC_IMRL_MASKALL);
310	}
311
312	/*
313	* Soak up buffer descriptors that have been sent.
314	*/
315	static void
316	fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc )
317	{
318	struct mbuf m, n;
319
320	while ((sc->txBdActiveCount != 0)
321	&& ((sc->txBdBase[sc->txBdTail].status & MCF5282_FEC_TxBD_R) == 0)) {
322	m = sc->txMbuf[sc->txBdTail];
323	MFREE(m, n);
324	if (++sc->txBdTail == sc->txBdCount)
325	sc->txBdTail = 0;
326	sc->txBdActiveCount--;
327	}
328	}
329
330	static void
331	fec_rxDaemon (void *arg)
332	{
333	volatile struct mcf5282_enet_struct sc = (volatile struct mcf5282_enet_struct )arg;
334	struct ifnet ifp = (struct ifnet )&sc->arpcom.ac_if;
335	struct mbuf *m;
336	volatile uint16_t status;
337	volatile mcf5282BufferDescriptor_t *rxBd;
338	int rxBdIndex;
339
340	/*
341	* Allocate space for incoming packets and start reception
342	*/
343	for (rxBdIndex = 0 ; ;) {
344	rxBd = sc->rxBdBase + rxBdIndex;
345	MGETHDR(m, M_WAIT, MT_DATA);
346	MCLGET(m, M_WAIT);
347	m->m_pkthdr.rcvif = ifp;
348	sc->rxMbuf[rxBdIndex] = m;
349	rxBd->buffer = mtod(m, void *);
350	rxBd->status = MCF5282_FEC_RxBD_E;
351	if (++rxBdIndex == sc->rxBdCount) {
352	rxBd->status \|= MCF5282_FEC_RxBD_W;
353	break;
354	}
355	}
356
357	/*
358	* Input packet handling loop
359	*/
360	/* Indicate we have some ready buffers available */
361	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
362
363	rxBdIndex = 0;
364	for (;;) {
365	rxBd = sc->rxBdBase + rxBdIndex;
366
367	/*
368	* Wait for packet if there's not one ready
369	*/
370	if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
371	/*
372	* Clear old events.
373	*/
374	MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF;
375
376	/*
377	* Wait for packet to arrive.
378	* Check the buffer descriptor before waiting for the event.
379	* This catches the case when a packet arrives between the
380	* `if' above, and the clearing of the RXF bit in the EIR.
381	*/
382	while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
383	rtems_event_set events;
384	int level;
385
386	rtems_interrupt_disable(level);
387	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_RXF;
388	rtems_interrupt_enable(level);
389	rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT,
390	RTEMS_WAIT\|RTEMS_EVENT_ANY,
391	RTEMS_NO_TIMEOUT,
392	&events);
393	}
394	}
395
396	/*
397	* Check that packet is valid
398	*/
399	if (status & MCF5282_FEC_RxBD_L) {
400	/*
401	* Pass the packet up the chain.
402	* FIXME: Packet filtering hook could be done here.
403	*/
404	struct ether_header *eh;
405	int len = rxBd->length - sizeof(uint32_t);;
406
407	/*
408	* Invalidate the cache and push the packet up.
409	* The cache is so small that it's more efficient to just
410	* invalidate the whole thing unless the packet is very small.
411	*/
412	m = sc->rxMbuf[rxBdIndex];
413	if (len < 128)
414	rtems_cache_invalidate_multiple_data_lines(m->m_data, len);
415	else
416	rtems_cache_invalidate_entire_data();
417	m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header);
418	eh = mtod(m, struct ether_header *);
419	m->m_data += sizeof(struct ether_header);
420	ether_input(ifp, eh, m);
421
422	/*
423	* Allocate a new mbuf
424	*/
425	MGETHDR(m, M_WAIT, MT_DATA);
426	MCLGET(m, M_WAIT);
427	m->m_pkthdr.rcvif = ifp;
428	sc->rxMbuf[rxBdIndex] = m;
429	rxBd->buffer = mtod(m, void *);
430	}
431
432	/*
433	* Reenable the buffer descriptor
434	*/
435	rxBd->status = (status & MCF5282_FEC_RxBD_W) \| MCF5282_FEC_RxBD_E;
436	MCF5282_FEC_RDAR = MCF5282_FEC_RDAR_R_DES_ACTIVE;
437
438	/*
439	* Move to next buffer descriptor
440	*/
441	if (++rxBdIndex == sc->rxBdCount)
442	rxBdIndex = 0;
443	}
444	}
445
446	static void
447	fec_sendpacket(struct ifnet ifp, struct mbuf m)
448	{
449	struct mcf5282_enet_struct *sc = ifp->if_softc;
450	volatile mcf5282BufferDescriptor_t firstTxBd, txBd;
451	uint16_t status;
452	int nAdded;
453
454	/*
455	* Free up buffer descriptors
456	*/
457	fec_retire_tx_bd(sc);
458
459	/*
460	* Set up the transmit buffer descriptors.
461	* No need to pad out short packets since the
462	* hardware takes care of that automatically.
463	* No need to copy the packet to a contiguous buffer
464	* since the hardware is capable of scatter/gather DMA.
465	*/
466	nAdded = 0;
467	firstTxBd = sc->txBdBase + sc->txBdHead;
468
469	for (;;) {
470	/*
471	* Wait for buffer descriptor to become available
472	*/
473	if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
474	/*
475	* Clear old events.
476	*/
477	MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF;
478
479	/*
480	* Wait for buffer descriptor to become available.
481	* Check for buffer descriptors before waiting for the event.
482	* This catches the case when a buffer became available between
483	* the `if' above, and the clearing of the TXF bit in the EIR.
484	*/
485	fec_retire_tx_bd(sc);
486	while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) {
487	rtems_event_set events;
488	int level;
489
490	rtems_interrupt_disable(level);
491	MCF5282_FEC_EIMR \|= MCF5282_FEC_EIMR_TXF;
492	rtems_interrupt_enable(level);
493	sc->txRawWait++;
494	rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT,
495	RTEMS_WAIT\|RTEMS_EVENT_ANY,
496	RTEMS_NO_TIMEOUT,
497	&events);
498	fec_retire_tx_bd(sc);
499	}
500	}
501
502	/*
503	* Don't set the READY flag on the first fragment
504	* until the whole packet has been readied.
505	*/
506	status = nAdded ? MCF5282_FEC_TxBD_R : 0;
507
508	/*
509	* The IP fragmentation routine in ip_output
510	* can produce fragments with zero length.
511	*/
512	txBd = sc->txBdBase + sc->txBdHead;
513	if (m->m_len) {
514	char p = mtod(m, char );
515	/*
516	* Stupid FEC can't handle misaligned data!
517	* Given the way that mbuf's are layed out it should be
518	* safe to shuffle the data down like this.....
519	* Perhaps this code could be improved with a "Duff's Device".
520	*/
521	if ((int)p & 0x3) {
522	int l = m->m_len;
523	char *dest = p - ((int)p & 0x3);
524	uint16_t o = (uint16_t )dest, i = (uint16_t )p;
525	while (l > 0) {
526	o++ = i++;
527	l -= sizeof(uint16_t);
528	}
529	p = dest;
530	sc->txRealign++;
531	}
532	txBd->buffer = p;
533	txBd->length = m->m_len;
534	sc->txMbuf[sc->txBdHead] = m;
535	nAdded++;
536	if (++sc->txBdHead == sc->txBdCount) {
537	status \|= MCF5282_FEC_TxBD_W;
538	sc->txBdHead = 0;
539	}
540	m = m->m_next;
541	}
542	else {
543	/*
544	* Just toss empty mbufs
545	*/
546	struct mbuf *n;
547	MFREE(m, n);
548	m = n;
549	}
550	if (m == NULL) {
551	if (nAdded) {
552	txBd->status = status \| MCF5282_FEC_TxBD_R
553	\| MCF5282_FEC_TxBD_L
554	\| MCF5282_FEC_TxBD_TC;
555	if (nAdded > 1)
556	firstTxBd->status \|= MCF5282_FEC_TxBD_R;
557	MCF5282_FEC_TDAR = MCF5282_FEC_TDAR_X_DES_ACTIVE;
558	sc->txBdActiveCount += nAdded;
559	}
560	break;
561	}
562	txBd->status = status;
563	}
564	}
565
566	void
567	fec_txDaemon(void *arg)
568	{
569	struct mcf5282_enet_struct sc = (struct mcf5282_enet_struct )arg;
570	struct ifnet *ifp = &sc->arpcom.ac_if;
571	struct mbuf *m;
572	rtems_event_set events;
573
574	for (;;) {
575	/*
576	* Wait for packet
577	*/
578	rtems_bsdnet_event_receive(START_TRANSMIT_EVENT,
579	RTEMS_EVENT_ANY \| RTEMS_WAIT,
580	RTEMS_NO_TIMEOUT,
581	&events);
582
583	/*
584	* Send packets till queue is empty
585	*/
586	for (;;) {
587	/*
588	* Get the next mbuf chain to transmit.
589	*/
590	IF_DEQUEUE(&ifp->if_snd, m);
591	if (!m)
592	break;
593	fec_sendpacket(ifp, m);
594	}
595	ifp->if_flags &= ~IFF_OACTIVE;
596	}
597	}
598
599
600	/*
601	* Send packet (caller provides header).
602	*/
603	static void
604	mcf5282_enet_start(struct ifnet *ifp)
605	{
606	struct mcf5282_enet_struct *sc = ifp->if_softc;
607
608	rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT);
609	ifp->if_flags \|= IFF_OACTIVE;
610	}
611
612	static void
613	fec_init(void *arg)
614	{
615	struct mcf5282_enet_struct *sc = arg;
616	struct ifnet *ifp = &sc->arpcom.ac_if;
617
618	if (sc->txDaemonTid == 0) {
619	/*
620	* Set up hardware
621	*/
622	mcf5282_fec_initialize_hardware(sc);
623
624	/*
625	* Start driver tasks
626	*/
627	sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc);
628	sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc);
629	}
630
631	/*
632	* Set flags appropriately
633	*/
634	if (ifp->if_flags & IFF_PROMISC)
635	MCF5282_FEC_RCR \|= MCF5282_FEC_RCR_PROM;
636	else
637	MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM;
638
639	/*
640	* Tell the world that we're running.
641	*/
642	ifp->if_flags \|= IFF_RUNNING;
643
644	/*
645	* Enable receiver and transmitter
646	*/
647	MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN;
648	}
649
650
651	static void
652	fec_stop(struct mcf5282_enet_struct *sc)
653	{
654	struct ifnet *ifp = &sc->arpcom.ac_if;
655
656	ifp->if_flags &= ~IFF_RUNNING;
657
658	/*
659	* Shut down receiver and transmitter
660	*/
661	MCF5282_FEC_ECR = 0x0;
662	}
663
664	/*
665	* Show interface statistics
666	*/
667	static void
668	enet_stats(struct mcf5282_enet_struct *sc)
669	{
670	printf(" Rx Interrupts:%-10lu", sc->rxInterrupts);
671	printf("Rx Packet Count:%-10lu", MCF5282_FEC_RMON_R_PACKETS);
672	printf(" Rx Broadcast:%-10lu\n", MCF5282_FEC_RMON_R_BC_PKT);
673	printf(" Rx Multicast:%-10lu", MCF5282_FEC_RMON_R_MC_PKT);
674	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_R_CRC_ALIGN);
675	printf(" Rx Undersize:%-10lu\n", MCF5282_FEC_RMON_R_UNDERSIZE);
676	printf(" Rx Oversize:%-10lu", MCF5282_FEC_RMON_R_OVERSIZE);
677	printf(" Rx Fragment:%-10lu", MCF5282_FEC_RMON_R_FRAG);
678	printf(" Rx Jabber:%-10lu\n", MCF5282_FEC_RMON_R_JAB);
679	printf(" Rx 64:%-10lu", MCF5282_FEC_RMON_R_P64);
680	printf(" Rx 65-127:%-10lu", MCF5282_FEC_RMON_R_P65T0127);
681	printf(" Rx 128-255:%-10lu\n", MCF5282_FEC_RMON_R_P128TO255);
682	printf(" Rx 256-511:%-10lu", MCF5282_FEC_RMON_R_P256TO511);
683	printf(" Rx 511-1023:%-10lu", MCF5282_FEC_RMON_R_P512TO1023);
684	printf(" Rx 1024-2047:%-10lu\n", MCF5282_FEC_RMON_R_P1024TO2047);
685	printf(" Rx >=2048:%-10lu", MCF5282_FEC_RMON_R_GTE2048);
686	printf(" Rx Octets:%-10lu", MCF5282_FEC_RMON_R_OCTETS);
687	printf(" Rx Dropped:%-10lu\n", MCF5282_FEC_IEEE_R_DROP);
688	printf(" Rx frame OK:%-10lu", MCF5282_FEC_IEEE_R_FRAME_OK);
689	printf(" Rx CRC error:%-10lu", MCF5282_FEC_IEEE_R_CRC);
690	printf(" Rx Align error:%-10lu\n", MCF5282_FEC_IEEE_R_ALIGN);
691	printf(" FIFO Overflow:%-10lu", MCF5282_FEC_IEEE_R_MACERR);
692	printf("Rx Pause Frames:%-10lu", MCF5282_FEC_IEEE_R_FDXFC);
693	printf(" Rx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_R_OCTETS_OK);
694	printf(" Tx Interrupts:%-10lu", sc->txInterrupts);
695	printf("Tx Output Waits:%-10lu", sc->txRawWait);
696	printf("Tx Realignments:%-10lu\n", sc->txRealign);
697	printf(" Tx Unaccounted:%-10lu", MCF5282_FEC_RMON_T_DROP);
698	printf("Tx Packet Count:%-10lu", MCF5282_FEC_RMON_T_PACKETS);
699	printf(" Tx Broadcast:%-10lu\n", MCF5282_FEC_RMON_T_BC_PKT);
700	printf(" Tx Multicast:%-10lu", MCF5282_FEC_RMON_T_MC_PKT);
701	printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_T_CRC_ALIGN);
702	printf(" Tx Undersize:%-10lu\n", MCF5282_FEC_RMON_T_UNDERSIZE);
703	printf(" Tx Oversize:%-10lu", MCF5282_FEC_RMON_T_OVERSIZE);
704	printf(" Tx Fragment:%-10lu", MCF5282_FEC_RMON_T_FRAG);
705	printf(" Tx Jabber:%-10lu\n", MCF5282_FEC_RMON_T_JAB);
706	printf(" Tx Collisions:%-10lu", MCF5282_FEC_RMON_T_COL);
707	printf(" Tx 64:%-10lu", MCF5282_FEC_RMON_T_P64);
708	printf(" Tx 65-127:%-10lu\n", MCF5282_FEC_RMON_T_P65TO127);
709	printf(" Tx 128-255:%-10lu", MCF5282_FEC_RMON_T_P128TO255);
710	printf(" Tx 256-511:%-10lu", MCF5282_FEC_RMON_T_P256TO511);
711	printf(" Tx 511-1023:%-10lu\n", MCF5282_FEC_RMON_T_P512TO1023);
712	printf(" Tx 1024-2047:%-10lu", MCF5282_FEC_RMON_T_P1024TO2047);
713	printf(" Tx >=2048:%-10lu", MCF5282_FEC_RMON_T_P_GTE2048);
714	printf(" Tx Octets:%-10lu\n", MCF5282_FEC_RMON_T_OCTETS);
715	printf(" Tx Dropped:%-10lu", MCF5282_FEC_IEEE_T_DROP);
716	printf(" Tx Frame OK:%-10lu", MCF5282_FEC_IEEE_T_FRAME_OK);
717	printf(" Tx 1 Collision:%-10lu\n", MCF5282_FEC_IEEE_T_1COL);
718	printf("Tx >1 Collision:%-10lu", MCF5282_FEC_IEEE_T_MCOL);
719	printf(" Tx Deferred:%-10lu", MCF5282_FEC_IEEE_T_DEF);
720	printf(" Late Collision:%-10lu\n", MCF5282_FEC_IEEE_T_LCOL);
721	printf(" Excessive Coll:%-10lu", MCF5282_FEC_IEEE_T_EXCOL);
722	printf(" FIFO Underrun:%-10lu", MCF5282_FEC_IEEE_T_MACERR);
723	printf(" Carrier Error:%-10lu\n", MCF5282_FEC_IEEE_T_CSERR);
724	printf(" Tx SQE Error:%-10lu", MCF5282_FEC_IEEE_T_SQE);
725	printf("Tx Pause Frames:%-10lu", MCF5282_FEC_IEEE_T_FDXFC);
726	printf(" Tx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_T_OCTETS_OK);
727	}
728
729	static int
730	fec_ioctl(struct ifnet *ifp, int command, caddr_t data)
731	{
732	struct mcf5282_enet_struct *sc = ifp->if_softc;
733	int error = 0;
734
735	switch (command) {
736	case SIOCGIFADDR:
737	case SIOCSIFADDR:
738	ether_ioctl(ifp, command, data);
739	break;
740
741	case SIOCSIFFLAGS:
742	switch (ifp->if_flags & (IFF_UP \| IFF_RUNNING)) {
743	case IFF_RUNNING:
744	fec_stop(sc);
745	break;
746
747	case IFF_UP:
748	fec_init(sc);
749	break;
750
751	case IFF_UP \| IFF_RUNNING:
752	fec_stop(sc);
753	fec_init(sc);
754	break;
755
756	default:
757	break;
758	}
759	break;
760
761	case SIO_RTEMS_SHOW_STATS:
762	enet_stats(sc);
763	break;
764
765	/*
766	* FIXME: All sorts of multicast commands need to be added here!
767	*/
768	default:
769	error = EINVAL;
770	break;
771	}
772	return error;
773	}
774
775	int
776	rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching )
777	{
778	struct mcf5282_enet_struct *sc;
779	struct ifnet *ifp;
780	int mtu;
781	int unitNumber;
782	char *unitName;
783	unsigned char *hwaddr;
784
785	/*
786	* Parse driver name
787	*/
788	if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0)
789	return 0;
790
791	/*
792	* Is driver free?
793	*/
794	if ((unitNumber <= 0) \|\| (unitNumber > NIFACES)) {
795	printf("Bad FEC unit number.\n");
796	return 0;
797	}
798	sc = &enet_driver[unitNumber - 1];
799	ifp = &sc->arpcom.ac_if;
800	if (ifp->if_softc != NULL) {
801	printf("Driver already in use.\n");
802	return 0;
803	}
804
805	/*
806	* Process options
807	*/
808	if (config->hardware_address) {
809	hwaddr = config->hardware_address;
810	}
811	else if ((hwaddr = uC5282_gethwaddr(unitNumber - 1)) == NULL) {
812	/* Locally-administered address */
813	static const char defaultAddress[ETHER_ADDR_LEN] = {
814	0x06, 'R', 'T', 'E', 'M', 'S'};
815	printf ("WARNING -- No %s%d Ethernet address specified -- Using default address.\n",
816	unitName, unitNumber);
817	hwaddr = defaultAddress;
818	}
819	printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n",
820	unitName, unitNumber,
821	hwaddr[0], hwaddr[1], hwaddr[2],
822	hwaddr[3], hwaddr[4], hwaddr[5]);
823	memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
824
825	if (config->mtu)
826	mtu = config->mtu;
827	else
828	mtu = ETHERMTU;
829	if (config->rbuf_count)
830	sc->rxBdCount = config->rbuf_count;
831	else
832	sc->rxBdCount = RX_BUF_COUNT;
833	if (config->xbuf_count)
834	sc->txBdCount = config->xbuf_count;
835	else
836	sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF;
837
838	sc->acceptBroadcast = !config->ignore_broadcast;
839
840	/*
841	* Set up network interface values
842	*/
843	ifp->if_softc = sc;
844	ifp->if_unit = unitNumber;
845	ifp->if_name = unitName;
846	ifp->if_mtu = mtu;
847	ifp->if_init = fec_init;
848	ifp->if_ioctl = fec_ioctl;
849	ifp->if_start = mcf5282_enet_start;
850	ifp->if_output = ether_output;
851	ifp->if_flags = IFF_BROADCAST \| IFF_SIMPLEX;
852	if (ifp->if_snd.ifq_maxlen == 0)
853	ifp->if_snd.ifq_maxlen = ifqmaxlen;
854
855	/*
856	* Attach the interface
857	*/
858	if_attach(ifp);
859	ether_ifattach(ifp);
860	return 1;
861	};
862

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