[572484f] | 1 | /* |
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[81291a0] | 2 | * RTEMS driver for MCF5282 Fast Ethernet Controller |
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[12b36efe] | 3 | * |
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| 4 | * Author: W. Eric Norum <norume@aps.anl.gov> |
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| 5 | * |
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| 6 | * COPYRIGHT (c) 2005. |
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| 7 | * On-Line Applications Research Corporation (OAR). |
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| 8 | * |
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| 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[688696e4] | 11 | * http://www.rtems.com/license/LICENSE. |
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[572484f] | 12 | */ |
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| 13 | |
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| 14 | #include <bsp.h> |
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| 15 | #include <stdio.h> |
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| 16 | #include <errno.h> |
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| 17 | #include <stdarg.h> |
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| 18 | #include <string.h> |
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[518edef] | 19 | #include <rtems.h> |
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[572484f] | 20 | #include <rtems/error.h> |
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| 21 | #include <rtems/rtems_bsdnet.h> |
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| 22 | |
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| 23 | #include <sys/param.h> |
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| 24 | #include <sys/mbuf.h> |
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| 25 | #include <sys/socket.h> |
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| 26 | #include <sys/sockio.h> |
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| 27 | |
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| 28 | #include <net/ethernet.h> |
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| 29 | #include <net/if.h> |
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| 30 | |
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| 31 | #include <netinet/in.h> |
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| 32 | #include <netinet/if_ether.h> |
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| 33 | |
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| 34 | |
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| 35 | /* |
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| 36 | * Number of interfaces supported by this driver |
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| 37 | */ |
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| 38 | #define NIFACES 1 |
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| 39 | |
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| 40 | #define FEC_INTC0_TX_VECTOR (64+23) |
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| 41 | #define FEC_INTC0_RX_VECTOR (64+27) |
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[81291a0] | 42 | #define MII_VECTOR (64+7) /* IRQ7* pin connected to external transceiver */ |
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| 43 | #define MII_EPPAR MCF5282_EPORT_EPPAR_EPPA7_LEVEL |
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| 44 | #define MII_EPDDR MCF5282_EPORT_EPDDR_EPDD7 |
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| 45 | #define MII_EPIER MCF5282_EPORT_EPIER_EPIE7 |
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| 46 | #define MII_EPPDR MCF5282_EPORT_EPPDR_EPPD7 |
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[572484f] | 47 | |
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| 48 | /* |
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| 49 | * Default number of buffer descriptors set aside for this driver. |
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| 50 | * The number of transmit buffer descriptors has to be quite large |
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| 51 | * since a single frame often uses three or more buffer descriptors. |
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| 52 | */ |
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| 53 | #define RX_BUF_COUNT 32 |
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| 54 | #define TX_BUF_COUNT 20 |
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| 55 | #define TX_BD_PER_BUF 3 |
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| 56 | |
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| 57 | #define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255") |
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| 58 | |
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| 59 | /* |
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| 60 | * RTEMS event used by interrupt handler to signal daemons. |
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| 61 | * This must *not* be the same event used by the TCP/IP task synchronization. |
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| 62 | */ |
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| 63 | #define TX_INTERRUPT_EVENT RTEMS_EVENT_1 |
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| 64 | #define RX_INTERRUPT_EVENT RTEMS_EVENT_1 |
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| 65 | |
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| 66 | /* |
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| 67 | * RTEMS event used to start transmit daemon. |
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| 68 | * This must not be the same as INTERRUPT_EVENT. |
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| 69 | */ |
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| 70 | #define START_TRANSMIT_EVENT RTEMS_EVENT_2 |
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| 71 | |
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| 72 | /* |
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| 73 | * Receive buffer size -- Allow for a full ethernet packet plus CRC (1518). |
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| 74 | * Round off to nearest multiple of RBUF_ALIGN. |
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| 75 | */ |
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| 76 | #define MAX_MTU_SIZE 1518 |
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| 77 | #define RBUF_ALIGN 4 |
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| 78 | #define RBUF_SIZE ((MAX_MTU_SIZE + RBUF_ALIGN) & ~RBUF_ALIGN) |
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| 79 | |
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| 80 | #if (MCLBYTES < RBUF_SIZE) |
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| 81 | #error "Driver must have MCLBYTES > RBUF_SIZE" |
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| 82 | #endif |
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| 83 | |
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| 84 | typedef struct mcf5282BufferDescriptor_ { |
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[b6cfe2f6] | 85 | volatile uint16_t status; |
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[0b2c943] | 86 | uint16_t length; |
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[b6cfe2f6] | 87 | volatile void *buffer; |
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[572484f] | 88 | } mcf5282BufferDescriptor_t; |
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| 89 | |
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| 90 | /* |
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| 91 | * Per-device data |
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| 92 | */ |
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| 93 | struct mcf5282_enet_struct { |
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| 94 | struct arpcom arpcom; |
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| 95 | struct mbuf **rxMbuf; |
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| 96 | struct mbuf **txMbuf; |
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| 97 | int acceptBroadcast; |
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| 98 | int rxBdCount; |
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| 99 | int txBdCount; |
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| 100 | int txBdHead; |
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| 101 | int txBdTail; |
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| 102 | int txBdActiveCount; |
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| 103 | mcf5282BufferDescriptor_t *rxBdBase; |
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| 104 | mcf5282BufferDescriptor_t *txBdBase; |
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| 105 | rtems_id rxDaemonTid; |
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| 106 | rtems_id txDaemonTid; |
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| 107 | |
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| 108 | /* |
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| 109 | * Statistics |
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| 110 | */ |
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| 111 | unsigned long rxInterrupts; |
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| 112 | unsigned long txInterrupts; |
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[81291a0] | 113 | unsigned long miiInterrupts; |
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[572484f] | 114 | unsigned long txRawWait; |
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| 115 | unsigned long txRealign; |
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[f077cc96] | 116 | unsigned long txRealignDrop; |
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[21dd4cf8] | 117 | |
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| 118 | /* |
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| 119 | * Link parameters |
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| 120 | */ |
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[9797991] | 121 | enum { link_auto, link_100Full, link_10Half } link; |
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| 122 | uint16_t mii_cr; |
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[81291a0] | 123 | uint16_t mii_sr2; |
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[572484f] | 124 | }; |
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| 125 | static struct mcf5282_enet_struct enet_driver[NIFACES]; |
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| 126 | |
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[81291a0] | 127 | /* |
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| 128 | * Read MII register |
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| 129 | * Busy-waits, but transfer time should be short! |
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| 130 | */ |
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| 131 | static int |
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| 132 | getMII(int phyNumber, int regNumber) |
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| 133 | { |
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| 134 | MCF5282_FEC_MMFR = (0x1 << 30) | |
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| 135 | (0x2 << 28) | |
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| 136 | (phyNumber << 23) | |
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| 137 | (regNumber << 18) | |
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| 138 | (0x2 << 16); |
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| 139 | while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0); |
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| 140 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII; |
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| 141 | return MCF5282_FEC_MMFR & 0xFFFF; |
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| 142 | } |
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| 143 | |
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| 144 | /* |
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| 145 | * Write MII register |
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| 146 | * Busy-waits, but transfer time should be short! |
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| 147 | */ |
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| 148 | static void |
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| 149 | setMII(int phyNumber, int regNumber, int value) |
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| 150 | { |
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| 151 | MCF5282_FEC_MMFR = (0x1 << 30) | |
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| 152 | (0x1 << 28) | |
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| 153 | (phyNumber << 23) | |
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| 154 | (regNumber << 18) | |
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| 155 | (0x2 << 16) | |
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| 156 | (value & 0xFFFF); |
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| 157 | while ((MCF5282_FEC_EIR & MCF5282_FEC_EIR_MII) == 0); |
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| 158 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_MII; |
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| 159 | } |
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| 160 | |
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[572484f] | 161 | static rtems_isr |
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| 162 | mcf5282_fec_rx_interrupt_handler( rtems_vector_number v ) |
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| 163 | { |
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| 164 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF; |
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| 165 | MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_RXF; |
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| 166 | enet_driver[0].rxInterrupts++; |
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| 167 | rtems_event_send(enet_driver[0].rxDaemonTid, RX_INTERRUPT_EVENT); |
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| 168 | } |
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| 169 | |
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| 170 | static rtems_isr |
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| 171 | mcf5282_fec_tx_interrupt_handler( rtems_vector_number v ) |
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| 172 | { |
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| 173 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF; |
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| 174 | MCF5282_FEC_EIMR &= ~MCF5282_FEC_EIMR_TXF; |
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| 175 | enet_driver[0].txInterrupts++; |
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| 176 | rtems_event_send(enet_driver[0].txDaemonTid, TX_INTERRUPT_EVENT); |
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| 177 | } |
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| 178 | |
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[81291a0] | 179 | static rtems_isr |
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| 180 | mcf5282_mii_interrupt_handler( rtems_vector_number v ) |
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| 181 | { |
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| 182 | uint16 sr2; |
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| 183 | |
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| 184 | enet_driver[0].miiInterrupts++; |
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| 185 | getMII(1, 19); /* Read and clear interrupt status bits */ |
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| 186 | enet_driver[0].mii_sr2 = sr2 = getMII(1, 17); |
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| 187 | if (((sr2 & 0x200) != 0) |
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| 188 | && ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) == 0)) |
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| 189 | MCF5282_FEC_TCR |= MCF5282_FEC_TCR_FDEN; |
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| 190 | else if (((sr2 & 0x200) == 0) |
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| 191 | && ((MCF5282_FEC_TCR & MCF5282_FEC_TCR_FDEN) != 0)) |
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| 192 | MCF5282_FEC_TCR &= ~MCF5282_FEC_TCR_FDEN; |
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| 193 | } |
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| 194 | |
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[572484f] | 195 | /* |
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[7c7184a] | 196 | * Allocate buffer descriptors from (non-cached) on-chip static RAM |
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[518edef] | 197 | * Ensure 128-bit (16-byte) alignment |
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[be5b08a] | 198 | * Allow some space at the beginning for other diagnostic counters |
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[572484f] | 199 | */ |
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[518edef] | 200 | static mcf5282BufferDescriptor_t * |
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[572484f] | 201 | mcf5282_bd_allocate(unsigned int count) |
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| 202 | { |
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[7c7184a] | 203 | extern char __SRAMBASE[]; |
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[be5b08a] | 204 | static mcf5282BufferDescriptor_t *bdp = (mcf5282BufferDescriptor_t *)(__SRAMBASE+16); |
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[7c7184a] | 205 | mcf5282BufferDescriptor_t *p = bdp; |
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[518edef] | 206 | |
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[7c7184a] | 207 | bdp += count; |
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| 208 | if ((int)bdp & 0xF) |
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| 209 | bdp = (mcf5282BufferDescriptor_t *)((char *)bdp + (16 - ((int)bdp & 0xF))); |
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[572484f] | 210 | return p; |
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| 211 | } |
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| 212 | |
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| 213 | static void |
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| 214 | mcf5282_fec_initialize_hardware(struct mcf5282_enet_struct *sc) |
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| 215 | { |
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| 216 | int i; |
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[98653c6] | 217 | const unsigned char *hwaddr; |
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[572484f] | 218 | rtems_status_code status; |
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| 219 | rtems_isr_entry old_handler; |
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[0b2c943] | 220 | uint32_t clock_speed = bsp_get_CPU_clock_speed(); |
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[572484f] | 221 | |
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| 222 | /* |
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| 223 | * Issue reset to FEC |
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| 224 | */ |
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| 225 | MCF5282_FEC_ECR = MCF5282_FEC_ECR_RESET; |
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[81291a0] | 226 | rtems_task_wake_after(2); |
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[98653c6] | 227 | MCF5282_FEC_ECR = 0; |
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| 228 | |
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[572484f] | 229 | /* |
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| 230 | * Configuration of I/O ports is done outside of this function |
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| 231 | */ |
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| 232 | #if 0 |
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| 233 | imm->gpio.pbcnt |= MCF5282_GPIO_PBCNT_SET_FEC; /* Set up port b FEC pins */ |
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| 234 | #endif |
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| 235 | |
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| 236 | /* |
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| 237 | * Set our physical address |
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| 238 | */ |
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| 239 | hwaddr = sc->arpcom.ac_enaddr; |
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| 240 | MCF5282_FEC_PALR = (hwaddr[0] << 24) | (hwaddr[1] << 16) | |
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| 241 | (hwaddr[2] << 8) | (hwaddr[3] << 0); |
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| 242 | MCF5282_FEC_PAUR = (hwaddr[4] << 24) | (hwaddr[5] << 16); |
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| 243 | |
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| 244 | |
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| 245 | /* |
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| 246 | * Clear the hash table |
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| 247 | */ |
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| 248 | MCF5282_FEC_GAUR = 0; |
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| 249 | MCF5282_FEC_GALR = 0; |
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| 250 | |
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| 251 | /* |
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| 252 | * Set up receive buffer size |
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| 253 | */ |
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| 254 | MCF5282_FEC_EMRBR = 1520; /* Standard Ethernet */ |
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| 255 | |
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| 256 | /* |
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| 257 | * Allocate mbuf pointers |
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| 258 | */ |
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| 259 | sc->rxMbuf = malloc(sc->rxBdCount * sizeof *sc->rxMbuf, M_MBUF, M_NOWAIT); |
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| 260 | sc->txMbuf = malloc(sc->txBdCount * sizeof *sc->txMbuf, M_MBUF, M_NOWAIT); |
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| 261 | if (!sc->rxMbuf || !sc->txMbuf) |
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| 262 | rtems_panic("No memory for mbuf pointers"); |
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| 263 | |
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| 264 | /* |
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| 265 | * Set receiver and transmitter buffer descriptor bases |
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| 266 | */ |
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| 267 | sc->rxBdBase = mcf5282_bd_allocate(sc->rxBdCount); |
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| 268 | sc->txBdBase = mcf5282_bd_allocate(sc->txBdCount); |
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| 269 | MCF5282_FEC_ERDSR = (int)sc->rxBdBase; |
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| 270 | MCF5282_FEC_ETDSR = (int)sc->txBdBase; |
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| 271 | |
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| 272 | /* |
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| 273 | * Set up Receive Control Register: |
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| 274 | * Not promiscuous |
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| 275 | * MII mode |
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[98653c6] | 276 | * Full duplex |
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[572484f] | 277 | * No loopback |
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| 278 | */ |
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| 279 | MCF5282_FEC_RCR = MCF5282_FEC_RCR_MAX_FL(MAX_MTU_SIZE) | |
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[98653c6] | 280 | MCF5282_FEC_RCR_MII_MODE; |
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[572484f] | 281 | |
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| 282 | /* |
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| 283 | * Set up Transmit Control Register: |
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[9797991] | 284 | * Full or half duplex |
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[572484f] | 285 | * No heartbeat |
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| 286 | */ |
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[9797991] | 287 | if (sc->link == link_10Half) |
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| 288 | MCF5282_FEC_TCR = 0; |
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| 289 | else |
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[98653c6] | 290 | MCF5282_FEC_TCR = MCF5282_FEC_TCR_FDEN; |
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[572484f] | 291 | |
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| 292 | /* |
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| 293 | * Initialize statistic counters |
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| 294 | */ |
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| 295 | MCF5282_FEC_MIBC = MCF5282_FEC_MIBC_MIB_DISABLE; |
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| 296 | { |
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| 297 | vuint32 *vuip = &MCF5282_FEC_RMON_T_DROP; |
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| 298 | while (vuip <= &MCF5282_FEC_IEEE_R_OCTETS_OK) |
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| 299 | *vuip++ = 0; |
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| 300 | } |
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| 301 | MCF5282_FEC_MIBC = 0; |
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| 302 | |
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| 303 | /* |
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[98653c6] | 304 | * Set MII speed to <= 2.5 MHz |
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| 305 | */ |
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| 306 | i = (clock_speed + 5000000 - 1) / 5000000; |
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| 307 | MCF5282_FEC_MSCR = MCF5282_FEC_MSCR_MII_SPEED(i); |
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| 308 | |
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| 309 | /* |
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[81291a0] | 310 | * Set PHYS |
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[1066597] | 311 | * LED1 receive status, LED2 link status, LEDs stretched |
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[81291a0] | 312 | * Advertise 100 Mb/s, full-duplex, IEEE-802.3 |
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| 313 | * Turn off auto-negotiate |
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[9797991] | 314 | * Clear status |
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[572484f] | 315 | */ |
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[1066597] | 316 | setMII(1, 20, 0x24F2); |
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[81291a0] | 317 | setMII(1, 4, 0x0181); |
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[9797991] | 318 | setMII(1, 0, 0x0); |
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[81291a0] | 319 | rtems_task_wake_after(2); |
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| 320 | sc->mii_sr2 = getMII(1, 17); |
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[9797991] | 321 | switch (sc->link) { |
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| 322 | case link_auto: |
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| 323 | /* |
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| 324 | * Enable speed-change, duplex-change and link-status-change interrupts |
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| 325 | * Enable auto-negotiate (start at 100/FULL) |
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| 326 | */ |
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[81291a0] | 327 | setMII(1, 18, 0x0072); |
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[21dd4cf8] | 328 | setMII(1, 0, 0x3100); |
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[9797991] | 329 | break; |
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| 330 | |
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| 331 | case link_10Half: |
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| 332 | /* |
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| 333 | * Force 10/HALF |
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| 334 | */ |
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| 335 | setMII(1, 0, 0x0); |
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| 336 | break; |
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| 337 | |
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| 338 | case link_100Full: |
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| 339 | /* |
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| 340 | * Force 100/FULL |
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| 341 | */ |
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| 342 | setMII(1, 0, 0x2100); |
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| 343 | break; |
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| 344 | } |
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| 345 | sc->mii_cr = getMII(1, 0); |
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[572484f] | 346 | |
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| 347 | /* |
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| 348 | * Set up receive buffer descriptors |
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| 349 | */ |
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| 350 | for (i = 0 ; i < sc->rxBdCount ; i++) |
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| 351 | (sc->rxBdBase + i)->status = 0; |
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| 352 | |
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| 353 | /* |
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| 354 | * Set up transmit buffer descriptors |
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| 355 | */ |
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| 356 | for (i = 0 ; i < sc->txBdCount ; i++) { |
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| 357 | sc->txBdBase[i].status = 0; |
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| 358 | sc->txMbuf[i] = NULL; |
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| 359 | } |
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| 360 | sc->txBdHead = sc->txBdTail = 0; |
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| 361 | sc->txBdActiveCount = 0; |
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| 362 | |
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| 363 | /* |
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| 364 | * Set up interrupts |
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| 365 | */ |
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| 366 | status = rtems_interrupt_catch( mcf5282_fec_tx_interrupt_handler, FEC_INTC0_TX_VECTOR, &old_handler ); |
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| 367 | if (status != RTEMS_SUCCESSFUL) |
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| 368 | rtems_panic ("Can't attach MCF5282 FEC TX interrupt handler: %s\n", |
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[81291a0] | 369 | rtems_status_text(status)); |
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[5b6111b] | 370 | bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_TX_PRIORITY); |
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[572484f] | 371 | MCF5282_INTC0_ICR23 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | |
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| 372 | MCF5282_INTC_ICR_IP(FEC_IRQ_TX_PRIORITY); |
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| 373 | MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT23 | MCF5282_INTC_IMRL_MASKALL); |
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[81291a0] | 374 | |
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| 375 | status = rtems_interrupt_catch(mcf5282_fec_rx_interrupt_handler, FEC_INTC0_RX_VECTOR, &old_handler); |
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| 376 | if (status != RTEMS_SUCCESSFUL) |
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| 377 | rtems_panic ("Can't attach MCF5282 FEC RX interrupt handler: %s\n", |
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| 378 | rtems_status_text(status)); |
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[5b6111b] | 379 | bsp_allocate_interrupt(FEC_IRQ_LEVEL, FEC_IRQ_RX_PRIORITY); |
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[572484f] | 380 | MCF5282_INTC0_ICR27 = MCF5282_INTC_ICR_IL(FEC_IRQ_LEVEL) | |
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| 381 | MCF5282_INTC_ICR_IP(FEC_IRQ_RX_PRIORITY); |
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| 382 | MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT27 | MCF5282_INTC_IMRL_MASKALL); |
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[81291a0] | 383 | |
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| 384 | status = rtems_interrupt_catch(mcf5282_mii_interrupt_handler, MII_VECTOR, &old_handler); |
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| 385 | if (status != RTEMS_SUCCESSFUL) |
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| 386 | rtems_panic ("Can't attach MCF5282 FEC MII interrupt handler: %s\n", |
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| 387 | rtems_status_text(status)); |
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| 388 | MCF5282_EPORT_EPPAR &= ~MII_EPPAR; |
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| 389 | MCF5282_EPORT_EPDDR &= ~MII_EPDDR; |
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| 390 | MCF5282_EPORT_EPIER |= MII_EPIER; |
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| 391 | MCF5282_INTC0_IMRL &= ~(MCF5282_INTC_IMRL_INT7 | MCF5282_INTC_IMRL_MASKALL); |
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[572484f] | 392 | } |
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| 393 | |
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| 394 | /* |
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| 395 | * Soak up buffer descriptors that have been sent. |
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| 396 | */ |
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| 397 | static void |
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| 398 | fec_retire_tx_bd(volatile struct mcf5282_enet_struct *sc ) |
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| 399 | { |
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| 400 | struct mbuf *m, *n; |
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[f077cc96] | 401 | uint16_t status; |
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[572484f] | 402 | |
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[7c7184a] | 403 | while ((sc->txBdActiveCount != 0) |
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[f077cc96] | 404 | && (((status = sc->txBdBase[sc->txBdTail].status) & MCF5282_FEC_TxBD_R) == 0)) { |
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| 405 | if ((status & MCF5282_FEC_TxBD_TO1) == 0) { |
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| 406 | m = sc->txMbuf[sc->txBdTail]; |
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| 407 | MFREE(m, n); |
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| 408 | } |
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[572484f] | 409 | if (++sc->txBdTail == sc->txBdCount) |
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| 410 | sc->txBdTail = 0; |
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| 411 | sc->txBdActiveCount--; |
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| 412 | } |
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| 413 | } |
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| 414 | |
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| 415 | static void |
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| 416 | fec_rxDaemon (void *arg) |
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| 417 | { |
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| 418 | volatile struct mcf5282_enet_struct *sc = (volatile struct mcf5282_enet_struct *)arg; |
---|
| 419 | struct ifnet *ifp = (struct ifnet* )&sc->arpcom.ac_if; |
---|
| 420 | struct mbuf *m; |
---|
[f077cc96] | 421 | uint16_t status; |
---|
[572484f] | 422 | volatile mcf5282BufferDescriptor_t *rxBd; |
---|
| 423 | int rxBdIndex; |
---|
| 424 | |
---|
| 425 | /* |
---|
| 426 | * Allocate space for incoming packets and start reception |
---|
| 427 | */ |
---|
| 428 | for (rxBdIndex = 0 ; ;) { |
---|
| 429 | rxBd = sc->rxBdBase + rxBdIndex; |
---|
| 430 | MGETHDR(m, M_WAIT, MT_DATA); |
---|
| 431 | MCLGET(m, M_WAIT); |
---|
| 432 | m->m_pkthdr.rcvif = ifp; |
---|
| 433 | sc->rxMbuf[rxBdIndex] = m; |
---|
| 434 | rxBd->buffer = mtod(m, void *); |
---|
| 435 | rxBd->status = MCF5282_FEC_RxBD_E; |
---|
| 436 | if (++rxBdIndex == sc->rxBdCount) { |
---|
| 437 | rxBd->status |= MCF5282_FEC_RxBD_W; |
---|
| 438 | break; |
---|
| 439 | } |
---|
| 440 | } |
---|
| 441 | |
---|
| 442 | /* |
---|
| 443 | * Input packet handling loop |
---|
| 444 | */ |
---|
[27111a79] | 445 | MCF5282_FEC_RDAR = 0; |
---|
[572484f] | 446 | |
---|
| 447 | rxBdIndex = 0; |
---|
| 448 | for (;;) { |
---|
| 449 | rxBd = sc->rxBdBase + rxBdIndex; |
---|
| 450 | |
---|
| 451 | /* |
---|
| 452 | * Wait for packet if there's not one ready |
---|
| 453 | */ |
---|
| 454 | if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) { |
---|
| 455 | /* |
---|
| 456 | * Clear old events. |
---|
| 457 | */ |
---|
| 458 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_RXF; |
---|
| 459 | |
---|
| 460 | /* |
---|
| 461 | * Wait for packet to arrive. |
---|
| 462 | * Check the buffer descriptor before waiting for the event. |
---|
| 463 | * This catches the case when a packet arrives between the |
---|
| 464 | * `if' above, and the clearing of the RXF bit in the EIR. |
---|
| 465 | */ |
---|
[7c7184a] | 466 | while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) { |
---|
[572484f] | 467 | rtems_event_set events; |
---|
| 468 | int level; |
---|
| 469 | |
---|
| 470 | rtems_interrupt_disable(level); |
---|
| 471 | MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_RXF; |
---|
| 472 | rtems_interrupt_enable(level); |
---|
| 473 | rtems_bsdnet_event_receive (RX_INTERRUPT_EVENT, |
---|
| 474 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
| 475 | RTEMS_NO_TIMEOUT, |
---|
| 476 | &events); |
---|
| 477 | } |
---|
| 478 | } |
---|
| 479 | |
---|
| 480 | /* |
---|
| 481 | * Check that packet is valid |
---|
| 482 | */ |
---|
| 483 | if (status & MCF5282_FEC_RxBD_L) { |
---|
| 484 | /* |
---|
| 485 | * Pass the packet up the chain. |
---|
| 486 | * FIXME: Packet filtering hook could be done here. |
---|
| 487 | */ |
---|
| 488 | struct ether_header *eh; |
---|
[0b2c943] | 489 | int len = rxBd->length - sizeof(uint32_t);; |
---|
[572484f] | 490 | |
---|
[ac9bbe7] | 491 | m = sc->rxMbuf[rxBdIndex]; |
---|
| 492 | #ifdef RTEMS_MCF5282_BSP_ENABLE_DATA_CACHE |
---|
[572484f] | 493 | /* |
---|
[ac9bbe7] | 494 | * Invalidate the cache. The cache is so small that it's |
---|
| 495 | * more efficient to just invalidate the whole thing unless |
---|
| 496 | * the packet is very small. |
---|
[572484f] | 497 | */ |
---|
[518edef] | 498 | if (len < 128) |
---|
| 499 | rtems_cache_invalidate_multiple_data_lines(m->m_data, len); |
---|
| 500 | else |
---|
| 501 | rtems_cache_invalidate_entire_data(); |
---|
[ac9bbe7] | 502 | #endif |
---|
[518edef] | 503 | m->m_len = m->m_pkthdr.len = len - sizeof(struct ether_header); |
---|
[572484f] | 504 | eh = mtod(m, struct ether_header *); |
---|
| 505 | m->m_data += sizeof(struct ether_header); |
---|
| 506 | ether_input(ifp, eh, m); |
---|
| 507 | |
---|
| 508 | /* |
---|
| 509 | * Allocate a new mbuf |
---|
| 510 | */ |
---|
| 511 | MGETHDR(m, M_WAIT, MT_DATA); |
---|
| 512 | MCLGET(m, M_WAIT); |
---|
| 513 | m->m_pkthdr.rcvif = ifp; |
---|
| 514 | sc->rxMbuf[rxBdIndex] = m; |
---|
| 515 | rxBd->buffer = mtod(m, void *); |
---|
| 516 | } |
---|
| 517 | |
---|
| 518 | /* |
---|
| 519 | * Reenable the buffer descriptor |
---|
| 520 | */ |
---|
| 521 | rxBd->status = (status & MCF5282_FEC_RxBD_W) | MCF5282_FEC_RxBD_E; |
---|
[b6cfe2f6] | 522 | MCF5282_FEC_RDAR = 0; |
---|
[572484f] | 523 | |
---|
| 524 | /* |
---|
| 525 | * Move to next buffer descriptor |
---|
| 526 | */ |
---|
| 527 | if (++rxBdIndex == sc->rxBdCount) |
---|
| 528 | rxBdIndex = 0; |
---|
| 529 | } |
---|
| 530 | } |
---|
| 531 | |
---|
| 532 | static void |
---|
| 533 | fec_sendpacket(struct ifnet *ifp, struct mbuf *m) |
---|
| 534 | { |
---|
| 535 | struct mcf5282_enet_struct *sc = ifp->if_softc; |
---|
| 536 | volatile mcf5282BufferDescriptor_t *firstTxBd, *txBd; |
---|
[0b2c943] | 537 | uint16_t status; |
---|
[572484f] | 538 | int nAdded; |
---|
| 539 | |
---|
| 540 | /* |
---|
| 541 | * Free up buffer descriptors |
---|
| 542 | */ |
---|
| 543 | fec_retire_tx_bd(sc); |
---|
| 544 | |
---|
| 545 | /* |
---|
| 546 | * Set up the transmit buffer descriptors. |
---|
| 547 | * No need to pad out short packets since the |
---|
| 548 | * hardware takes care of that automatically. |
---|
| 549 | * No need to copy the packet to a contiguous buffer |
---|
| 550 | * since the hardware is capable of scatter/gather DMA. |
---|
| 551 | */ |
---|
| 552 | nAdded = 0; |
---|
| 553 | firstTxBd = sc->txBdBase + sc->txBdHead; |
---|
| 554 | |
---|
[f077cc96] | 555 | while (m != NULL) { |
---|
[572484f] | 556 | /* |
---|
| 557 | * Wait for buffer descriptor to become available |
---|
| 558 | */ |
---|
| 559 | if ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { |
---|
| 560 | /* |
---|
| 561 | * Clear old events. |
---|
| 562 | */ |
---|
| 563 | MCF5282_FEC_EIR = MCF5282_FEC_EIR_TXF; |
---|
| 564 | |
---|
| 565 | /* |
---|
| 566 | * Wait for buffer descriptor to become available. |
---|
| 567 | * Check for buffer descriptors before waiting for the event. |
---|
| 568 | * This catches the case when a buffer became available between |
---|
| 569 | * the `if' above, and the clearing of the TXF bit in the EIR. |
---|
| 570 | */ |
---|
| 571 | fec_retire_tx_bd(sc); |
---|
| 572 | while ((sc->txBdActiveCount + nAdded) == sc->txBdCount) { |
---|
| 573 | rtems_event_set events; |
---|
| 574 | int level; |
---|
| 575 | |
---|
| 576 | rtems_interrupt_disable(level); |
---|
| 577 | MCF5282_FEC_EIMR |= MCF5282_FEC_EIMR_TXF; |
---|
| 578 | rtems_interrupt_enable(level); |
---|
| 579 | sc->txRawWait++; |
---|
| 580 | rtems_bsdnet_event_receive(TX_INTERRUPT_EVENT, |
---|
| 581 | RTEMS_WAIT|RTEMS_EVENT_ANY, |
---|
| 582 | RTEMS_NO_TIMEOUT, |
---|
| 583 | &events); |
---|
| 584 | fec_retire_tx_bd(sc); |
---|
| 585 | } |
---|
| 586 | } |
---|
| 587 | |
---|
| 588 | /* |
---|
| 589 | * Don't set the READY flag on the first fragment |
---|
| 590 | * until the whole packet has been readied. |
---|
| 591 | */ |
---|
| 592 | status = nAdded ? MCF5282_FEC_TxBD_R : 0; |
---|
| 593 | |
---|
| 594 | /* |
---|
| 595 | * The IP fragmentation routine in ip_output |
---|
| 596 | * can produce fragments with zero length. |
---|
| 597 | */ |
---|
| 598 | txBd = sc->txBdBase + sc->txBdHead; |
---|
| 599 | if (m->m_len) { |
---|
| 600 | char *p = mtod(m, char *); |
---|
[cdb717e] | 601 | int offset = (int)p & 0x3; |
---|
| 602 | if (offset == 0) { |
---|
[f077cc96] | 603 | txBd->buffer = p; |
---|
| 604 | txBd->length = m->m_len; |
---|
| 605 | sc->txMbuf[sc->txBdHead] = m; |
---|
| 606 | m = m->m_next; |
---|
| 607 | } |
---|
| 608 | else { |
---|
| 609 | /* |
---|
| 610 | * Stupid FEC can't handle misaligned data! |
---|
| 611 | * Move offending bytes to a local buffer. |
---|
| 612 | * Use buffer descriptor TO1 bit to indicate this. |
---|
| 613 | */ |
---|
| 614 | int nmove = 4 - offset; |
---|
| 615 | char *d = (char *)&sc->txMbuf[sc->txBdHead]; |
---|
| 616 | status |= MCF5282_FEC_TxBD_TO1; |
---|
[572484f] | 617 | sc->txRealign++; |
---|
[f077cc96] | 618 | if (nmove > m->m_len) |
---|
| 619 | nmove = m->m_len; |
---|
| 620 | m->m_data += nmove; |
---|
| 621 | m->m_len -= nmove; |
---|
| 622 | txBd->buffer = d; |
---|
| 623 | txBd->length = nmove; |
---|
| 624 | while (nmove--) |
---|
| 625 | *d++ = *p++; |
---|
| 626 | if (m->m_len == 0) { |
---|
| 627 | struct mbuf *n; |
---|
| 628 | sc->txRealignDrop++; |
---|
| 629 | MFREE(m, n); |
---|
| 630 | m = n; |
---|
| 631 | } |
---|
[572484f] | 632 | } |
---|
| 633 | nAdded++; |
---|
| 634 | if (++sc->txBdHead == sc->txBdCount) { |
---|
| 635 | status |= MCF5282_FEC_TxBD_W; |
---|
| 636 | sc->txBdHead = 0; |
---|
| 637 | } |
---|
[f077cc96] | 638 | txBd->status = status; |
---|
[572484f] | 639 | } |
---|
| 640 | else { |
---|
| 641 | /* |
---|
[f077cc96] | 642 | * Toss empty mbufs. |
---|
[572484f] | 643 | */ |
---|
| 644 | struct mbuf *n; |
---|
| 645 | MFREE(m, n); |
---|
| 646 | m = n; |
---|
| 647 | } |
---|
| 648 | } |
---|
[f077cc96] | 649 | if (nAdded) { |
---|
| 650 | txBd->status = status | MCF5282_FEC_TxBD_R |
---|
| 651 | | MCF5282_FEC_TxBD_L |
---|
| 652 | | MCF5282_FEC_TxBD_TC; |
---|
| 653 | if (nAdded > 1) |
---|
| 654 | firstTxBd->status |= MCF5282_FEC_TxBD_R; |
---|
| 655 | MCF5282_FEC_TDAR = 0; |
---|
| 656 | sc->txBdActiveCount += nAdded; |
---|
| 657 | } |
---|
[572484f] | 658 | } |
---|
| 659 | |
---|
| 660 | void |
---|
| 661 | fec_txDaemon(void *arg) |
---|
| 662 | { |
---|
| 663 | struct mcf5282_enet_struct *sc = (struct mcf5282_enet_struct *)arg; |
---|
| 664 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 665 | struct mbuf *m; |
---|
| 666 | rtems_event_set events; |
---|
| 667 | |
---|
| 668 | for (;;) { |
---|
| 669 | /* |
---|
| 670 | * Wait for packet |
---|
| 671 | */ |
---|
| 672 | rtems_bsdnet_event_receive(START_TRANSMIT_EVENT, |
---|
| 673 | RTEMS_EVENT_ANY | RTEMS_WAIT, |
---|
| 674 | RTEMS_NO_TIMEOUT, |
---|
| 675 | &events); |
---|
| 676 | |
---|
| 677 | /* |
---|
| 678 | * Send packets till queue is empty |
---|
| 679 | */ |
---|
| 680 | for (;;) { |
---|
| 681 | /* |
---|
| 682 | * Get the next mbuf chain to transmit. |
---|
| 683 | */ |
---|
| 684 | IF_DEQUEUE(&ifp->if_snd, m); |
---|
| 685 | if (!m) |
---|
| 686 | break; |
---|
| 687 | fec_sendpacket(ifp, m); |
---|
| 688 | } |
---|
| 689 | ifp->if_flags &= ~IFF_OACTIVE; |
---|
| 690 | } |
---|
| 691 | } |
---|
| 692 | |
---|
| 693 | |
---|
| 694 | /* |
---|
| 695 | * Send packet (caller provides header). |
---|
| 696 | */ |
---|
| 697 | static void |
---|
| 698 | mcf5282_enet_start(struct ifnet *ifp) |
---|
| 699 | { |
---|
| 700 | struct mcf5282_enet_struct *sc = ifp->if_softc; |
---|
| 701 | |
---|
| 702 | rtems_event_send(sc->txDaemonTid, START_TRANSMIT_EVENT); |
---|
| 703 | ifp->if_flags |= IFF_OACTIVE; |
---|
| 704 | } |
---|
| 705 | |
---|
| 706 | static void |
---|
| 707 | fec_init(void *arg) |
---|
| 708 | { |
---|
| 709 | struct mcf5282_enet_struct *sc = arg; |
---|
| 710 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 711 | |
---|
| 712 | if (sc->txDaemonTid == 0) { |
---|
| 713 | /* |
---|
| 714 | * Set up hardware |
---|
| 715 | */ |
---|
| 716 | mcf5282_fec_initialize_hardware(sc); |
---|
| 717 | |
---|
| 718 | /* |
---|
| 719 | * Start driver tasks |
---|
| 720 | */ |
---|
| 721 | sc->txDaemonTid = rtems_bsdnet_newproc("FECtx", 4096, fec_txDaemon, sc); |
---|
| 722 | sc->rxDaemonTid = rtems_bsdnet_newproc("FECrx", 4096, fec_rxDaemon, sc); |
---|
| 723 | } |
---|
| 724 | |
---|
| 725 | /* |
---|
| 726 | * Set flags appropriately |
---|
| 727 | */ |
---|
| 728 | if (ifp->if_flags & IFF_PROMISC) |
---|
| 729 | MCF5282_FEC_RCR |= MCF5282_FEC_RCR_PROM; |
---|
| 730 | else |
---|
| 731 | MCF5282_FEC_RCR &= ~MCF5282_FEC_RCR_PROM; |
---|
| 732 | |
---|
| 733 | /* |
---|
| 734 | * Tell the world that we're running. |
---|
| 735 | */ |
---|
| 736 | ifp->if_flags |= IFF_RUNNING; |
---|
| 737 | |
---|
| 738 | /* |
---|
| 739 | * Enable receiver and transmitter |
---|
| 740 | */ |
---|
| 741 | MCF5282_FEC_ECR = MCF5282_FEC_ECR_ETHER_EN; |
---|
| 742 | } |
---|
| 743 | |
---|
| 744 | |
---|
| 745 | static void |
---|
| 746 | fec_stop(struct mcf5282_enet_struct *sc) |
---|
| 747 | { |
---|
| 748 | struct ifnet *ifp = &sc->arpcom.ac_if; |
---|
| 749 | |
---|
| 750 | ifp->if_flags &= ~IFF_RUNNING; |
---|
| 751 | |
---|
| 752 | /* |
---|
| 753 | * Shut down receiver and transmitter |
---|
| 754 | */ |
---|
| 755 | MCF5282_FEC_ECR = 0x0; |
---|
| 756 | } |
---|
| 757 | |
---|
| 758 | /* |
---|
| 759 | * Show interface statistics |
---|
| 760 | */ |
---|
| 761 | static void |
---|
| 762 | enet_stats(struct mcf5282_enet_struct *sc) |
---|
| 763 | { |
---|
| 764 | printf(" Rx Interrupts:%-10lu", sc->rxInterrupts); |
---|
| 765 | printf("Rx Packet Count:%-10lu", MCF5282_FEC_RMON_R_PACKETS); |
---|
| 766 | printf(" Rx Broadcast:%-10lu\n", MCF5282_FEC_RMON_R_BC_PKT); |
---|
| 767 | printf(" Rx Multicast:%-10lu", MCF5282_FEC_RMON_R_MC_PKT); |
---|
| 768 | printf("CRC/Align error:%-10lu", MCF5282_FEC_RMON_R_CRC_ALIGN); |
---|
| 769 | printf(" Rx Undersize:%-10lu\n", MCF5282_FEC_RMON_R_UNDERSIZE); |
---|
| 770 | printf(" Rx Oversize:%-10lu", MCF5282_FEC_RMON_R_OVERSIZE); |
---|
| 771 | printf(" Rx Fragment:%-10lu", MCF5282_FEC_RMON_R_FRAG); |
---|
| 772 | printf(" Rx Jabber:%-10lu\n", MCF5282_FEC_RMON_R_JAB); |
---|
| 773 | printf(" Rx 64:%-10lu", MCF5282_FEC_RMON_R_P64); |
---|
| 774 | printf(" Rx 65-127:%-10lu", MCF5282_FEC_RMON_R_P65T0127); |
---|
| 775 | printf(" Rx 128-255:%-10lu\n", MCF5282_FEC_RMON_R_P128TO255); |
---|
| 776 | printf(" Rx 256-511:%-10lu", MCF5282_FEC_RMON_R_P256TO511); |
---|
| 777 | printf(" Rx 511-1023:%-10lu", MCF5282_FEC_RMON_R_P512TO1023); |
---|
| 778 | printf(" Rx 1024-2047:%-10lu\n", MCF5282_FEC_RMON_R_P1024TO2047); |
---|
| 779 | printf(" Rx >=2048:%-10lu", MCF5282_FEC_RMON_R_GTE2048); |
---|
| 780 | printf(" Rx Octets:%-10lu", MCF5282_FEC_RMON_R_OCTETS); |
---|
| 781 | printf(" Rx Dropped:%-10lu\n", MCF5282_FEC_IEEE_R_DROP); |
---|
| 782 | printf(" Rx frame OK:%-10lu", MCF5282_FEC_IEEE_R_FRAME_OK); |
---|
| 783 | printf(" Rx CRC error:%-10lu", MCF5282_FEC_IEEE_R_CRC); |
---|
| 784 | printf(" Rx Align error:%-10lu\n", MCF5282_FEC_IEEE_R_ALIGN); |
---|
| 785 | printf(" FIFO Overflow:%-10lu", MCF5282_FEC_IEEE_R_MACERR); |
---|
| 786 | printf("Rx Pause Frames:%-10lu", MCF5282_FEC_IEEE_R_FDXFC); |
---|
| 787 | printf(" Rx Octets OK:%-10lu\n", MCF5282_FEC_IEEE_R_OCTETS_OK); |
---|
| 788 | printf(" Tx Interrupts:%-10lu", sc->txInterrupts); |
---|
| 789 | printf("Tx Output Waits:%-10lu", sc->txRawWait); |
---|
[f077cc96] | 790 | printf("Tx mbuf realign:%-10lu\n", sc->txRealign); |
---|
| 791 | printf("Tx realign drop:%-10lu", sc->txRealignDrop); |
---|
| 792 | printf(" Tx Unaccounted:%-10lu", MCF5282_FEC_RMON_T_DROP); |
---|
| 793 | printf("Tx Packet Count:%-10lu\n", MCF5282_FEC_RMON_T_PACKETS); |
---|
[3adc6c13] | 794 | printf(" Tx Broadcast:%-10lu", MCF5282_FEC_RMON_T_BC_PKT); |
---|
[f077cc96] | 795 | printf(" Tx Multicast:%-10lu", MCF5282_FEC_RMON_T_MC_PKT); |
---|
| 796 | printf("CRC/Align error:%-10lu\n", MCF5282_FEC_RMON_T_CRC_ALIGN); |
---|
[3adc6c13] | 797 | printf(" Tx Undersize:%-10lu", MCF5282_FEC_RMON_T_UNDERSIZE); |
---|
[f077cc96] | 798 | printf(" Tx Oversize:%-10lu", MCF5282_FEC_RMON_T_OVERSIZE); |
---|
| 799 | printf(" Tx Fragment:%-10lu\n", MCF5282_FEC_RMON_T_FRAG); |
---|
[3adc6c13] | 800 | printf(" Tx Jabber:%-10lu", MCF5282_FEC_RMON_T_JAB); |
---|
[f077cc96] | 801 | printf(" Tx Collisions:%-10lu", MCF5282_FEC_RMON_T_COL); |
---|
| 802 | printf(" Tx 64:%-10lu\n", MCF5282_FEC_RMON_T_P64); |
---|
[3adc6c13] | 803 | printf(" Tx 65-127:%-10lu", MCF5282_FEC_RMON_T_P65TO127); |
---|
[f077cc96] | 804 | printf(" Tx 128-255:%-10lu", MCF5282_FEC_RMON_T_P128TO255); |
---|
| 805 | printf(" Tx 256-511:%-10lu\n", MCF5282_FEC_RMON_T_P256TO511); |
---|
[3adc6c13] | 806 | printf(" Tx 511-1023:%-10lu", MCF5282_FEC_RMON_T_P512TO1023); |
---|
[f077cc96] | 807 | printf(" Tx 1024-2047:%-10lu", MCF5282_FEC_RMON_T_P1024TO2047); |
---|
| 808 | printf(" Tx >=2048:%-10lu\n", MCF5282_FEC_RMON_T_P_GTE2048); |
---|
[3adc6c13] | 809 | printf(" Tx Octets:%-10lu", MCF5282_FEC_RMON_T_OCTETS); |
---|
[f077cc96] | 810 | printf(" Tx Dropped:%-10lu", MCF5282_FEC_IEEE_T_DROP); |
---|
| 811 | printf(" Tx Frame OK:%-10lu\n", MCF5282_FEC_IEEE_T_FRAME_OK); |
---|
[3adc6c13] | 812 | printf(" Tx 1 Collision:%-10lu", MCF5282_FEC_IEEE_T_1COL); |
---|
[f077cc96] | 813 | printf("Tx >1 Collision:%-10lu", MCF5282_FEC_IEEE_T_MCOL); |
---|
| 814 | printf(" Tx Deferred:%-10lu\n", MCF5282_FEC_IEEE_T_DEF); |
---|
[3adc6c13] | 815 | printf(" Late Collision:%-10lu", MCF5282_FEC_IEEE_T_LCOL); |
---|
[f077cc96] | 816 | printf(" Excessive Coll:%-10lu", MCF5282_FEC_IEEE_T_EXCOL); |
---|
| 817 | printf(" FIFO Underrun:%-10lu\n", MCF5282_FEC_IEEE_T_MACERR); |
---|
[3adc6c13] | 818 | printf(" Carrier Error:%-10lu", MCF5282_FEC_IEEE_T_CSERR); |
---|
[f077cc96] | 819 | printf(" Tx SQE Error:%-10lu", MCF5282_FEC_IEEE_T_SQE); |
---|
| 820 | printf("Tx Pause Frames:%-10lu\n", MCF5282_FEC_IEEE_T_FDXFC); |
---|
[81291a0] | 821 | printf(" Tx Octets OK:%-10lu", MCF5282_FEC_IEEE_T_OCTETS_OK); |
---|
| 822 | printf(" MII interrupts:%-10lu\n", sc->miiInterrupts); |
---|
| 823 | if ((sc->mii_sr2 & 0x400) == 0) { |
---|
| 824 | printf("LINK DOWN!\n"); |
---|
| 825 | } |
---|
| 826 | else { |
---|
[9797991] | 827 | int speed; |
---|
| 828 | int full; |
---|
| 829 | int fixed; |
---|
| 830 | if (sc->mii_cr & 0x1000) { |
---|
| 831 | fixed = 0; |
---|
| 832 | speed = sc->mii_sr2 & 0x4000 ? 100 : 10; |
---|
| 833 | full = sc->mii_sr2 & 0x200 ? 1 : 0; |
---|
| 834 | } |
---|
| 835 | else { |
---|
| 836 | fixed = 1; |
---|
| 837 | speed = sc->mii_cr & 0x2000 ? 100 : 10; |
---|
| 838 | full = sc->mii_cr & 0x100 ? "full" : "half"; |
---|
| 839 | } |
---|
| 840 | printf("Link %s %d Mb/s, %s-duplex.\n", |
---|
| 841 | fixed ? "fixed" : "auto-negotiate", |
---|
| 842 | speed, |
---|
| 843 | full ? "full" : "half"); |
---|
[81291a0] | 844 | } |
---|
[27111a79] | 845 | printf(" EIR:%8.8lx ", MCF5282_FEC_EIR); |
---|
| 846 | printf("EIMR:%8.8lx ", MCF5282_FEC_EIMR); |
---|
| 847 | printf("RDAR:%8.8lx ", MCF5282_FEC_RDAR); |
---|
| 848 | printf("TDAR:%8.8lx\n", MCF5282_FEC_TDAR); |
---|
| 849 | printf(" ECR:%8.8lx ", MCF5282_FEC_ECR); |
---|
| 850 | printf(" RCR:%8.8lx ", MCF5282_FEC_RCR); |
---|
| 851 | printf(" TCR:%8.8lx\n", MCF5282_FEC_TCR); |
---|
| 852 | printf("FRBR:%8.8lx ", MCF5282_FEC_FRBR); |
---|
| 853 | printf("FRSR:%8.8lx\n", MCF5282_FEC_FRSR); |
---|
[b6cfe2f6] | 854 | if (sc->txBdActiveCount != 0) { |
---|
| 855 | int i, n; |
---|
| 856 | /* |
---|
| 857 | * Yes, there are races here with adding and retiring descriptors, |
---|
| 858 | * but this diagnostic is more for when things have backed up. |
---|
| 859 | */ |
---|
[f077cc96] | 860 | printf("Transmit Buffer Descriptors (Tail %d, Head %d, Unretired %d):\n", |
---|
[b6cfe2f6] | 861 | sc->txBdTail, |
---|
| 862 | sc->txBdHead, |
---|
| 863 | sc->txBdActiveCount); |
---|
| 864 | i = sc->txBdTail; |
---|
| 865 | for (n = 0 ; n < sc->txBdCount ; n++) { |
---|
| 866 | if ((sc->txBdBase[i].status & MCF5282_FEC_TxBD_R) != 0) |
---|
| 867 | printf(" %3d: status:%4.4x length:%-4d buffer:%p\n", |
---|
| 868 | i, |
---|
| 869 | sc->txBdBase[i].status, |
---|
| 870 | sc->txBdBase[i].length, |
---|
| 871 | sc->txBdBase[i].buffer); |
---|
| 872 | if (++i == sc->txBdCount) |
---|
| 873 | i = 0; |
---|
| 874 | } |
---|
| 875 | } |
---|
[572484f] | 876 | } |
---|
| 877 | |
---|
| 878 | static int |
---|
| 879 | fec_ioctl(struct ifnet *ifp, int command, caddr_t data) |
---|
| 880 | { |
---|
| 881 | struct mcf5282_enet_struct *sc = ifp->if_softc; |
---|
| 882 | int error = 0; |
---|
| 883 | |
---|
| 884 | switch (command) { |
---|
| 885 | case SIOCGIFADDR: |
---|
| 886 | case SIOCSIFADDR: |
---|
| 887 | ether_ioctl(ifp, command, data); |
---|
| 888 | break; |
---|
| 889 | |
---|
| 890 | case SIOCSIFFLAGS: |
---|
| 891 | switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) { |
---|
| 892 | case IFF_RUNNING: |
---|
| 893 | fec_stop(sc); |
---|
| 894 | break; |
---|
| 895 | |
---|
| 896 | case IFF_UP: |
---|
| 897 | fec_init(sc); |
---|
| 898 | break; |
---|
| 899 | |
---|
| 900 | case IFF_UP | IFF_RUNNING: |
---|
| 901 | fec_stop(sc); |
---|
| 902 | fec_init(sc); |
---|
| 903 | break; |
---|
| 904 | |
---|
| 905 | default: |
---|
| 906 | break; |
---|
| 907 | } |
---|
| 908 | break; |
---|
| 909 | |
---|
| 910 | case SIO_RTEMS_SHOW_STATS: |
---|
| 911 | enet_stats(sc); |
---|
| 912 | break; |
---|
| 913 | |
---|
| 914 | /* |
---|
| 915 | * FIXME: All sorts of multicast commands need to be added here! |
---|
| 916 | */ |
---|
| 917 | default: |
---|
| 918 | error = EINVAL; |
---|
| 919 | break; |
---|
| 920 | } |
---|
| 921 | return error; |
---|
| 922 | } |
---|
| 923 | |
---|
| 924 | int |
---|
| 925 | rtems_fec_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching ) |
---|
| 926 | { |
---|
| 927 | struct mcf5282_enet_struct *sc; |
---|
| 928 | struct ifnet *ifp; |
---|
| 929 | int mtu; |
---|
| 930 | int unitNumber; |
---|
| 931 | char *unitName; |
---|
| 932 | unsigned char *hwaddr; |
---|
[21dd4cf8] | 933 | const char *env; |
---|
[572484f] | 934 | |
---|
| 935 | /* |
---|
| 936 | * Parse driver name |
---|
| 937 | */ |
---|
| 938 | if ((unitNumber = rtems_bsdnet_parse_driver_name (config, &unitName)) < 0) |
---|
| 939 | return 0; |
---|
| 940 | |
---|
| 941 | /* |
---|
| 942 | * Is driver free? |
---|
| 943 | */ |
---|
| 944 | if ((unitNumber <= 0) || (unitNumber > NIFACES)) { |
---|
[fa5dfe8] | 945 | printf("Bad FEC unit number.\n"); |
---|
[572484f] | 946 | return 0; |
---|
| 947 | } |
---|
| 948 | sc = &enet_driver[unitNumber - 1]; |
---|
| 949 | ifp = &sc->arpcom.ac_if; |
---|
| 950 | if (ifp->if_softc != NULL) { |
---|
| 951 | printf("Driver already in use.\n"); |
---|
| 952 | return 0; |
---|
| 953 | } |
---|
| 954 | |
---|
| 955 | /* |
---|
| 956 | * Process options |
---|
| 957 | */ |
---|
[dd2f891] | 958 | if (config->hardware_address) { |
---|
[572484f] | 959 | hwaddr = config->hardware_address; |
---|
[6191ee4] | 960 | } else if ((hwaddr = bsp_gethwaddr(unitNumber - 1)) == NULL) { |
---|
[dd2f891] | 961 | /* Locally-administered address */ |
---|
[6191ee4] | 962 | static const unsigned char defaultAddress[ETHER_ADDR_LEN] = { |
---|
| 963 | 0x06, 'R', 'T', 'E', 'M', 'S'}; |
---|
| 964 | printf ("WARNING -- No %s%d Ethernet address specified " |
---|
| 965 | "-- Using default address.\n", unitName, unitNumber); |
---|
[dd2f891] | 966 | hwaddr = defaultAddress; |
---|
| 967 | } |
---|
[572484f] | 968 | printf("%s%d: Ethernet address: %02x:%02x:%02x:%02x:%02x:%02x\n", |
---|
| 969 | unitName, unitNumber, |
---|
| 970 | hwaddr[0], hwaddr[1], hwaddr[2], |
---|
| 971 | hwaddr[3], hwaddr[4], hwaddr[5]); |
---|
| 972 | memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN); |
---|
| 973 | |
---|
| 974 | if (config->mtu) |
---|
| 975 | mtu = config->mtu; |
---|
| 976 | else |
---|
| 977 | mtu = ETHERMTU; |
---|
| 978 | if (config->rbuf_count) |
---|
| 979 | sc->rxBdCount = config->rbuf_count; |
---|
| 980 | else |
---|
| 981 | sc->rxBdCount = RX_BUF_COUNT; |
---|
| 982 | if (config->xbuf_count) |
---|
| 983 | sc->txBdCount = config->xbuf_count; |
---|
| 984 | else |
---|
| 985 | sc->txBdCount = TX_BUF_COUNT * TX_BD_PER_BUF; |
---|
| 986 | |
---|
| 987 | sc->acceptBroadcast = !config->ignore_broadcast; |
---|
| 988 | |
---|
| 989 | /* |
---|
| 990 | * Set up network interface values |
---|
| 991 | */ |
---|
| 992 | ifp->if_softc = sc; |
---|
| 993 | ifp->if_unit = unitNumber; |
---|
| 994 | ifp->if_name = unitName; |
---|
| 995 | ifp->if_mtu = mtu; |
---|
| 996 | ifp->if_init = fec_init; |
---|
| 997 | ifp->if_ioctl = fec_ioctl; |
---|
| 998 | ifp->if_start = mcf5282_enet_start; |
---|
| 999 | ifp->if_output = ether_output; |
---|
| 1000 | ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX; |
---|
| 1001 | if (ifp->if_snd.ifq_maxlen == 0) |
---|
| 1002 | ifp->if_snd.ifq_maxlen = ifqmaxlen; |
---|
| 1003 | |
---|
[21dd4cf8] | 1004 | /* |
---|
| 1005 | * Check for environment overrides |
---|
| 1006 | */ |
---|
| 1007 | if (((env = bsp_getbenv("IPADDR0_100FULL")) != NULL) |
---|
| 1008 | && ((*env == 'y') || (*env == 'Y'))) |
---|
[9797991] | 1009 | sc->link = link_100Full; |
---|
| 1010 | else if (((env = bsp_getbenv("IPADDR0_10HALF")) != NULL) |
---|
| 1011 | && ((*env == 'y') || (*env == 'Y'))) |
---|
| 1012 | sc->link = link_10Half; |
---|
| 1013 | else |
---|
| 1014 | sc->link = link_auto; |
---|
[21dd4cf8] | 1015 | |
---|
[572484f] | 1016 | /* |
---|
| 1017 | * Attach the interface |
---|
| 1018 | */ |
---|
| 1019 | if_attach(ifp); |
---|
| 1020 | ether_ifattach(ifp); |
---|
| 1021 | return 1; |
---|
| 1022 | }; |
---|