1 | /* |
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2 | * Use the last periodic interval timer (PIT3) as the system clock. |
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3 | * |
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4 | * Author: W. Eric Norum <norume@aps.anl.gov> |
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5 | * |
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6 | * COPYRIGHT (c) 2005. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.OARcorp.com/rtems/license.html. |
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12 | * |
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13 | * $Id$ |
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14 | */ |
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15 | |
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16 | #include <rtems.h> |
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17 | #include <bsp.h> |
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18 | #include <mcf5282/mcf5282.h> |
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19 | |
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20 | /* |
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21 | * Use INTC0 base |
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22 | */ |
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23 | #define CLOCK_VECTOR (64+58) |
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24 | |
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25 | /* |
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26 | * CPU load counters |
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27 | * Place in static RAM so updates don't hit the SDRAM |
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28 | */ |
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29 | extern int __SRAMBASE[]; |
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30 | #define IDLE_COUNTER __SRAMBASE[0] |
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31 | #define FILTERED_IDLE __SRAMBASE[1] |
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32 | #define MAX_IDLE_COUNT __SRAMBASE[2] |
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33 | #define FILTER_SHIFT 6 |
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34 | |
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35 | /* |
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36 | * Periodic interval timer interrupt handler |
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37 | */ |
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38 | #define Clock_driver_support_at_tick() \ |
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39 | do { \ |
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40 | int idle = IDLE_COUNTER; \ |
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41 | IDLE_COUNTER = 0; \ |
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42 | if (idle > MAX_IDLE_COUNT) \ |
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43 | MAX_IDLE_COUNT = idle; \ |
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44 | FILTERED_IDLE = idle + FILTERED_IDLE - (FILTERED_IDLE>>FILTER_SHIFT);\ |
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45 | MCF5282_PIT3_PCSR |= MCF5282_PIT_PCSR_PIF; \ |
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46 | } while (0) |
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47 | |
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48 | /* |
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49 | * Attach clock interrupt handler |
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50 | */ |
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51 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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52 | do { \ |
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53 | _old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \ |
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54 | } while(0) |
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55 | |
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56 | /* |
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57 | * Turn off the clock |
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58 | */ |
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59 | #define Clock_driver_support_shutdown_hardware() \ |
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60 | do { \ |
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61 | MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ |
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62 | } while(0) |
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63 | |
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64 | /* |
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65 | * Set up the clock hardware |
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66 | * |
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67 | * Prescale so that it counts in microseconds |
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68 | * System clock frequency better be 2**n (1<=n<=16) MHz! |
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69 | */ |
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70 | #define Clock_driver_support_initialize_hardware() \ |
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71 | do { \ |
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72 | int level; \ |
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73 | int preScaleCode = -2; \ |
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74 | int preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; \ |
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75 | while (preScaleDivisor) { \ |
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76 | preScaleDivisor >>= 1; \ |
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77 | preScaleCode++; \ |
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78 | } \ |
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79 | IDLE_COUNTER = 0; \ |
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80 | FILTERED_IDLE = 0; \ |
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81 | MAX_IDLE_COUNT = 0; \ |
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82 | bsp_allocate_interrupt(PIT3_IRQ_LEVEL, PIT3_IRQ_PRIORITY); \ |
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83 | MCF5282_INTC0_ICR58 = MCF5282_INTC_ICR_IL(PIT3_IRQ_LEVEL) | \ |
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84 | MCF5282_INTC_ICR_IP(PIT3_IRQ_PRIORITY); \ |
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85 | rtems_interrupt_disable( level ); \ |
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86 | MCF5282_INTC0_IMRH &= ~MCF5282_INTC_IMRH_INT58; \ |
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87 | MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ |
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88 | rtems_interrupt_enable( level ); \ |
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89 | MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ |
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90 | MCF5282_PIT_PCSR_OVW | \ |
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91 | MCF5282_PIT_PCSR_PIE | \ |
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92 | MCF5282_PIT_PCSR_RLD; \ |
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93 | MCF5282_PIT3_PMR = BSP_Configuration.microseconds_per_tick - 1; \ |
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94 | MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ |
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95 | MCF5282_PIT_PCSR_PIE | \ |
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96 | MCF5282_PIT_PCSR_RLD | \ |
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97 | MCF5282_PIT_PCSR_EN; \ |
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98 | } while (0) |
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99 | |
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100 | /* |
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101 | * Provide our own version of the idle task |
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102 | */ |
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103 | void _BSP_Thread_Idle_body(void) |
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104 | { |
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105 | for(;;) |
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106 | asm volatile ("addq.l #1,__SRAMBASE"); /* Atomic increment */ |
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107 | } |
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108 | |
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109 | int rtems_bsp_cpu_load_percentage(void) |
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110 | { |
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111 | return 100 - ((100 * (FILTERED_IDLE >> FILTER_SHIFT)) / MAX_IDLE_COUNT); |
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112 | } |
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113 | |
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114 | #include "../../../shared/clockdrv_shell.c" |
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