1 | /* |
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2 | * Use the last periodic interval timer (PIT3) as the system clock. |
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3 | * |
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4 | * Author: W. Eric Norum <norume@aps.anl.gov> |
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5 | * |
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6 | * COPYRIGHT (c) 2005. |
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7 | * On-Line Applications Research Corporation (OAR). |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.com/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #include <rtems.h> |
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15 | #include <bsp.h> |
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16 | #include <mcf5282/mcf5282.h> |
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17 | |
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18 | /* |
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19 | * Use INTC0 base |
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20 | */ |
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21 | #define CLOCK_VECTOR (64+58) |
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22 | |
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23 | /* |
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24 | * CPU load counters |
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25 | * Place in static RAM so updates don't hit the SDRAM |
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26 | */ |
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27 | #define IDLE_COUNTER __SRAMBASE.idle_counter |
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28 | #define FILTERED_IDLE __SRAMBASE.filtered_idle |
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29 | #define MAX_IDLE_COUNT __SRAMBASE.max_idle_count |
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30 | #define PITC_PER_TICK __SRAMBASE.pitc_per_tick |
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31 | #define NSEC_PER_PITC __SRAMBASE.nsec_per_pitc |
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32 | #define FILTER_SHIFT 6 |
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33 | |
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34 | static uint32_t bsp_clock_nanoseconds_since_last_tick(void) |
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35 | { |
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36 | int i = MCF5282_PIT3_PCNTR; |
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37 | if (MCF5282_PIT3_PCSR & MCF5282_PIT_PCSR_PIF) |
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38 | i = MCF5282_PIT3_PCNTR - PITC_PER_TICK; |
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39 | return (PITC_PER_TICK - i) * NSEC_PER_PITC; |
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40 | } |
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41 | |
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42 | #define Clock_driver_nanoseconds_since_last_tick \ |
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43 | bsp_clock_nanoseconds_since_last_tick |
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44 | |
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45 | /* |
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46 | * Periodic interval timer interrupt handler |
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47 | */ |
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48 | #define Clock_driver_support_at_tick() \ |
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49 | do { \ |
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50 | unsigned idle = IDLE_COUNTER; \ |
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51 | IDLE_COUNTER = 0; \ |
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52 | if (idle > MAX_IDLE_COUNT) \ |
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53 | MAX_IDLE_COUNT = idle; \ |
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54 | FILTERED_IDLE = idle + FILTERED_IDLE - (FILTERED_IDLE>>FILTER_SHIFT);\ |
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55 | MCF5282_PIT3_PCSR |= MCF5282_PIT_PCSR_PIF; \ |
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56 | } while (0) |
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57 | |
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58 | /* |
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59 | * Attach clock interrupt handler |
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60 | */ |
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61 | #define Clock_driver_support_install_isr( _new, _old ) \ |
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62 | do { \ |
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63 | _old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \ |
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64 | } while(0) |
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65 | |
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66 | /* |
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67 | * Turn off the clock |
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68 | */ |
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69 | #define Clock_driver_support_shutdown_hardware() \ |
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70 | do { \ |
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71 | MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ |
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72 | } while(0) |
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73 | |
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74 | /* |
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75 | * Set up the clock hardware |
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76 | * |
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77 | * f_pit = f_clk / 2^(preScaleCode+1) / N = 1/(us_per_tick/us_per_s) |
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78 | * |
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79 | * N = f_clk / 2^(preScaleCode+1) * us_per_tick / us_per_s |
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80 | * |
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81 | * ns_per_pit_clk = ns_per_s / (f_clk / 2^(preScaleCode+1)) |
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82 | * = ns_per_s * 2^(preScaleCode+1) / f_clk; |
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83 | */ |
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84 | #define Clock_driver_support_initialize_hardware() \ |
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85 | do { \ |
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86 | unsigned long long N; \ |
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87 | int level; \ |
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88 | int preScaleCode = 0; \ |
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89 | N = bsp_get_CPU_clock_speed(); \ |
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90 | N *= rtems_configuration_get_microseconds_per_tick(); \ |
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91 | N /= 2*1000000; /* min_prescale * us_per_s */ \ |
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92 | while ( N > 0x10000 ) { \ |
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93 | preScaleCode++; \ |
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94 | N >>= 1; \ |
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95 | } \ |
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96 | PITC_PER_TICK = N; \ |
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97 | N = 2000000000ULL << preScaleCode; \ |
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98 | N /= bsp_get_CPU_clock_speed(); \ |
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99 | NSEC_PER_PITC = N; \ |
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100 | IDLE_COUNTER = 0; \ |
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101 | FILTERED_IDLE = 0; \ |
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102 | MAX_IDLE_COUNT = 0; \ |
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103 | bsp_allocate_interrupt(PIT3_IRQ_LEVEL, PIT3_IRQ_PRIORITY); \ |
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104 | MCF5282_INTC0_ICR58 = MCF5282_INTC_ICR_IL(PIT3_IRQ_LEVEL) | \ |
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105 | MCF5282_INTC_ICR_IP(PIT3_IRQ_PRIORITY); \ |
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106 | rtems_interrupt_disable( level ); \ |
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107 | MCF5282_INTC0_IMRH &= ~MCF5282_INTC_IMRH_INT58; \ |
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108 | MCF5282_PIT3_PCSR &= ~MCF5282_PIT_PCSR_EN; \ |
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109 | rtems_interrupt_enable( level ); \ |
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110 | MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ |
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111 | MCF5282_PIT_PCSR_OVW | \ |
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112 | MCF5282_PIT_PCSR_PIE | \ |
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113 | MCF5282_PIT_PCSR_RLD; \ |
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114 | MCF5282_PIT3_PMR = PITC_PER_TICK - 1; \ |
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115 | MCF5282_PIT3_PCSR = MCF5282_PIT_PCSR_PRE(preScaleCode) | \ |
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116 | MCF5282_PIT_PCSR_PIE | \ |
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117 | MCF5282_PIT_PCSR_RLD | \ |
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118 | MCF5282_PIT_PCSR_EN; \ |
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119 | } while (0) |
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120 | |
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121 | /* |
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122 | * Provide our own version of the idle task |
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123 | */ |
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124 | Thread bsp_idle_thread(uint32_t ignored) |
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125 | { |
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126 | /* Atomic increment */ |
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127 | for(;;) |
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128 | __asm__ volatile ("addq.l #1,%0"::"m"(IDLE_COUNTER)); |
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129 | } |
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130 | |
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131 | int rtems_bsp_cpu_load_percentage(void) |
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132 | { |
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133 | return MAX_IDLE_COUNT ? |
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134 | (100 - ((100 * (FILTERED_IDLE >> FILTER_SHIFT)) / MAX_IDLE_COUNT)) : |
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135 | 0; |
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136 | } |
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137 | |
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138 | #include "../../../shared/clockdrv_shell.h" |
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