[ac7d5ef0] | 1 | /* entry.s |
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| 2 | * |
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| 3 | * This file contains the entry point for the application. |
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| 4 | * The name of this entry point is compiler dependent. |
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| 5 | * It jumps to the BSP which is responsible for performing |
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| 6 | * all initialization. |
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| 7 | * |
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[08311cc3] | 8 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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[98e4ebf5] | 11 | * The license and distribution terms for this file may be |
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| 12 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 13 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 14 | * |
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| 15 | * $Id$ |
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| 16 | */ |
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| 17 | |
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| 18 | #include "asm.h" |
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| 19 | |
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[906577f4] | 20 | #if (M68K_COLDFIRE_ARCH == 0) /* All ColdFire BSPs must provide their own start vector */ |
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| 21 | |
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[ac7d5ef0] | 22 | BEGIN_CODE |
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| 23 | | Default entry points for: |
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| 24 | PUBLIC (start) | GNU |
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| 25 | PUBLIC (M68Kvec) | Vector Table |
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| 26 | |
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| 27 | SYM (start): |
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[7e19c72b] | 28 | SYM (M68Kvec): | standard location for vectors |
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[ac7d5ef0] | 29 | nop | for linkers with problem |
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| 30 | | location zero |
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| 31 | jmp SYM (start_around) |
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| 32 | |
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| 33 | /* |
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| 34 | * We can use the following space as our vector table |
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| 35 | * if the CPU has a VBR or we can save vector table in it |
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| 36 | * if the CPU does not. |
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| 37 | */ |
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| 38 | |
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| 39 | .space 4088 | to avoid initial intr stack |
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| 40 | | from 135BUG on MVME13? |
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| 41 | | and start code at 0x4000 |
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| 42 | SYM (vectors): |
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| 43 | .space 1016 | reserve space for rest of vectors |
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| 44 | |
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| 45 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 46 | SYM (lowintstack): |
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| 47 | .space 4092 | reserve for interrupt stack |
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| 48 | SYM (hiintstack): |
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| 49 | .space 4 | end of interrupt stack |
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| 50 | #endif |
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| 51 | |
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| 52 | PUBLIC (start_around) |
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| 53 | SYM (start_around): |
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| 54 | move.w sr, SYM (initial_sr) |
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[7e19c72b] | 55 | oriw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! |
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[ac7d5ef0] | 56 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 57 | movec isp,a0 |
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| 58 | move.l a0, SYM (initial_isp) |
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[9898425] | 59 | movec usp,a0 |
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[ac7d5ef0] | 60 | move.l a0, SYM (initial_usp) |
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[9898425] | 61 | movec msp,a0 |
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| 62 | move.l a0, SYM (initial_msp) |
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| 63 | #else |
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[ac7d5ef0] | 64 | move.l a7, SYM (initial_msp) |
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[9898425] | 65 | #endif |
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[ac7d5ef0] | 66 | |
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| 67 | | |
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| 68 | | zero out uninitialized data area |
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| 69 | | |
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| 70 | zerobss: |
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[9b2c969] | 71 | moveal # SYM (_clear_end),a0 | find end of .bss |
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| 72 | moveal # SYM (_clear_start),a1 | find beginning of .bss |
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[ac7d5ef0] | 73 | movel #0,d0 |
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| 74 | |
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[7e19c72b] | 75 | loop: movel #0,a1@+ | to zero out uninitialized |
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[ac7d5ef0] | 76 | cmpal a0,a1 |
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| 77 | jlt loop | loop until _end reached |
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| 78 | |
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[69537ca9] | 79 | movel # SYM (_stack_init),d0 | d0 = stop of stack |
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[7e19c72b] | 80 | movw #0x3700,sr | SUPV MODE,INTERRUPTS OFF!!! |
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| 81 | movel d0,a7 | set master stack pointer |
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| 82 | movel d0,a6 | set base pointer |
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[ac7d5ef0] | 83 | |
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| 84 | /* |
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[e2a2ec60] | 85 | * RTEMS should maintain a separate interrupt stack on CPUs |
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[ac7d5ef0] | 86 | * without one in hardware. This is currently not supported |
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| 87 | * on versions of the m68k without a HW intr stack. |
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| 88 | */ |
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| 89 | |
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| 90 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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[7e19c72b] | 91 | lea SYM (hiintstack),a0 | a0 = high end of intr stack |
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[ac7d5ef0] | 92 | movec a0,isp | set interrupt stack |
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| 93 | #endif |
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[df49c60] | 94 | pea env | push environp |
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| 95 | pea arg | push argv |
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[3a4ae6c] | 96 | movel #0,a7@- | push argc |
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| 97 | |
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[e2a2ec60] | 98 | jsr SYM (boot_card) |
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[3a4ae6c] | 99 | addl #12,a7 |
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| 100 | |
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[ac7d5ef0] | 101 | #if ( M68K_HAS_SEPARATE_STACKS == 1 ) |
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| 102 | move.l SYM (initial_isp),a0 |
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| 103 | movec a0,isp |
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| 104 | move.l SYM (initial_usp),a0 |
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| 105 | movec a0,usp |
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| 106 | move.l SYM (initial_msp),a0 |
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| 107 | movec a0,msp |
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| 108 | #else |
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| 109 | movea.l SYM (initial_msp),a7 |
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| 110 | #endif |
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| 111 | move.w SYM (initial_sr),sr |
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| 112 | rts |
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| 113 | |
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| 114 | END_CODE |
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| 115 | |
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| 116 | BEGIN_DATA |
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| 117 | |
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[df49c60] | 118 | PUBLIC (environ) |
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| 119 | .align 2 |
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| 120 | SYM (environ): |
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| 121 | .long env |
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| 122 | |
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[ac7d5ef0] | 123 | PUBLIC (start_frame) |
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| 124 | SYM (start_frame): |
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| 125 | .space 4,0 |
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| 126 | |
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| 127 | END_DATA |
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| 128 | |
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| 129 | BEGIN_BSS |
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| 130 | |
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[df49c60] | 131 | env: .long 0 |
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| 132 | arg: .long 0 |
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[ac7d5ef0] | 133 | |
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| 134 | PUBLIC (initial_isp) |
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| 135 | SYM (initial_isp): |
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| 136 | .space 4 |
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| 137 | |
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| 138 | PUBLIC (initial_msp) |
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| 139 | SYM (initial_msp): |
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| 140 | .space 4 |
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| 141 | |
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| 142 | PUBLIC (initial_usp) |
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| 143 | SYM (initial_usp): |
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| 144 | .space 4 |
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| 145 | |
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| 146 | PUBLIC (initial_sr) |
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| 147 | SYM (initial_sr): |
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| 148 | .space 2 |
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| 149 | |
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| 150 | END_DATA |
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[906577f4] | 151 | #endif |
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[ac7d5ef0] | 152 | END |
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| 153 | |
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| 154 | |
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