source: rtems/c/src/lib/libbsp/m68k/shared/mvme/mvme16x_hw.h @ 5a09781f

4.104.114.84.95
Last change on this file since 5a09781f was 5a09781f, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 5, 2000 at 3:49:28 PM

2000-09-04 Ralf Corsepius <corsepiu@…>

  • clock/Makefile.am, console/Makefile.am, consolex/Makefile.am, start/Makefile.am, startup/Makefile.am, timer/Makefile.am, tod/Makefile.am, wrapup/Makefile.am, network/Makefile.am: Include compile.am
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/*  mvme16x_hw.h
2 *
3 *  This include file contains all MVME16x board IO definitions
4 *  and was derived by combining the common items in the
5 *  mvme162 and mvme167 BSPs.
6 *
7 *  COPYRIGHT (c) 1989-2000.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id#
15 */
16
17#ifndef __MVME16xHW_h
18#define __MVME16xHW_h
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
24/*
25 * Network driver configuration
26 */
27 
28struct rtems_bsdnet_ifconfig;
29int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
30#define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
31#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
32
33/*
34 *  This is NOT the base address of local RAM!
35 *  This is the base local address of the VMEbus short I/O space. A local
36 *  access to this space results in a A16 VMEbus I/O cycle. This base address
37 *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
38 *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
39 *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
40 *  GCSRs of other boards are accessible only through the VMEbus short I/O
41 *  space. See pages 2-45 and 2-7.
42 */
43#define BOARD_BASE_ADDRESS 0xFFFF0000
44
45/*
46 *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
47 *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
48 *  VMEbus short I/O space. It also should represent the group address of this
49 *  MVME167! The group address is configurable, and must match the address
50 *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
51 *  recommended by Motorola. It is arbitrary.
52 *  See pages 2-42 and 2-97 to 2-104.
53 */
54#define GROUP_BASE_ADDRESS 0x0000CC00
55
56
57/*
58 *  Representation of the VMEchip2 LCSR.
59 *  Could be made more detailed.
60 */
61
62typedef volatile struct {
63  unsigned long     slave_adr[2];
64  unsigned long     slave_trn[2];
65  unsigned long     slave_ctl;
66  unsigned long     mastr_adr[4];
67  unsigned long     mastr_trn;
68  unsigned long     mastr_att;
69  unsigned long     mastr_ctl;
70  unsigned long     dma_ctl_1;
71  unsigned long     dma_ctl_2;
72  unsigned long     dma_loc_cnt;
73  unsigned long     dma_vme_cnt;
74  unsigned long     dma_byte_cnt;
75  unsigned long     dma_adr_cnt;
76  unsigned long     dma_status;
77  unsigned long     to_ctl;
78  unsigned long     timer_cmp_1;
79  unsigned long     timer_cnt_1;
80  unsigned long     timer_cmp_2;
81  unsigned long     timer_cnt_2;
82  unsigned long     board_ctl;
83  unsigned long     prescaler_cnt;
84  unsigned long     intr_stat;
85  unsigned long     intr_ena;
86  unsigned long     intr_soft_set;
87  unsigned long     intr_clear;
88  unsigned long     intr_level[4];
89  unsigned long     vector_base;
90} lcsr_regs;
91
92/* 
93 *  Base address of VMEchip2 LCSR
94 *  Not configurable on the MVME167.
95 *  XXX what about 162?
96 */
97#define lcsr        ((lcsr_regs * const) 0xFFF40000)
98
99/*
100 *  Vector numbers for the interrupts from the VMEchip2. Use the values
101 *  "recommended" by Motorola.
102 *  See pages 2-70 to 2-92, and table 2-3.
103 */
104
105/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
106#define MASK_INT    0x00800000
107
108/* The content of VBR0 corresponds to "X" in table 2-3 */
109#define VBR0        0x6
110
111/* The content of VBR1 corresponds to "Y" in table 2-3 */
112#define VBR1        0x7
113
114/*
115 *  Representation of the PCCchip2
116 */
117typedef volatile struct pccchip2_regs_ {
118  unsigned char     chip_id;            /* 0xFFF42000 */
119  unsigned char     chip_revision;      /* 0xFFF42001 */
120  unsigned char     gen_control;        /* 0xFFF42002 */
121  unsigned char     vector_base;        /* 0xFFF42003 */
122  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
123  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
124  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
125  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
126  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
127  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
128  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
129  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
130  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
131  unsigned char     gpio_ctl;           /* 0xFFF42019 */
132  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
133  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
134  unsigned char     SCC_error;          /* 0xFFF4201C */
135  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
136  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
137  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
138  unsigned char     reserved1[3];
139  unsigned char     modem_piack;        /* 0xFFF42023 */
140  unsigned char     reserved2;
141  unsigned char     tx_piack;           /* 0xFFF42025 */
142  unsigned char     reserved3;
143  unsigned char     rx_piack;           /* 0xFFF42027 */
144  unsigned char     LANC_error;         /* 0xFFF42028 */
145  unsigned char     reserved4;
146  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
147  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
148  unsigned char     SCSI_error;         /* 0xFFF4202C */
149  unsigned char     reserved5[2];
150  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
151  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
152  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
153  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
154  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
155  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
156  unsigned char     reserved6;
157  unsigned char     print_input_status; /* 0xFFF42036 */
158  unsigned char     print_ctl;          /* 0xFFF42037 */
159  unsigned char     chip_speed;         /* 0xFFF42038 */
160  unsigned char     reserved7;
161  unsigned char     print_data;         /* 0xFFF4203A */
162  unsigned char     reserved8[3];
163  unsigned char     int_level;          /* 0xFFF4203E */
164  unsigned char     int_mask;           /* 0xFFF4203F */
165} pccchip2_regs;
166
167/*
168 *  Base address of the PCCchip2.
169 *  This is not configurable in the MVME167.
170 */
171#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
172
173/*
174 *  On the MVME162, we have the mcchip and the pccchip2 on
175 *  the 167.  They are similar but different enough where
176 *  we have to reconcile them later.
177 */
178
179/*
180 * Vector numbers for the interrupts from the PCCchip2. Use the values
181 * "recommended" by Motorola.
182 * See page 3-15.
183 */
184#define PCCCHIP2_VBR    0x5
185
186/*
187 * The following registers are located in the VMEbus short
188 * IO space and respond to address modifier codes $29 and $2D.
189 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
190 */
191
192typedef volatile struct {
193  unsigned char       chip_revision;
194  unsigned char       chip_id;
195  unsigned char       lmsig;
196  unsigned char       board_scr;
197  unsigned short      gpr[6];
198} gcsr_regs;
199
200#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
201#define gcsr     ((gcsr_regs * const) 0xFFF40100)
202
203/*
204 *  Representation of 82596CA LAN controller: Memory Map
205 */
206typedef volatile struct i82596_regs_ {
207  unsigned short  port_lower;             /* 0xFFF46000 */
208  unsigned short  port_upper;             /* 0xFFF46002 */
209  unsigned long   chan_attn;              /* 0xFFF46004 */
210} i82596_regs;
211
212/*
213 *  Base address of the 82596.
214 */
215
216#define i82596    ((i82596_regs * const) 0xFFF46000)
217
218/*
219 *  Representation of initialization data in NVRAM
220 */
221
222#if defined(mvme167)
223typedef volatile struct nvram_config_ {
224  unsigned char   cache_mode;          /* 0xFFFC0000 */
225  unsigned char   console_mode;        /* 0xFFFC0001 */
226  unsigned char   console_printk_port; /* 0xFFFC0002 */
227  unsigned char   pad1;                /* 0xFFFC0003 */
228  unsigned long   ipaddr;              /* 0xFFFC0004 */
229  unsigned long   netmask;             /* 0xFFFC0008 */
230  unsigned char   enaddr[6];           /* 0xFFFC000C */
231  unsigned short  processor_id;        /* 0xFFFC0012 */
232  unsigned long   rma_start;           /* 0xFFFC0014 */
233  unsigned long   vma_start;           /* 0xFFFC0018 */
234  unsigned long   ramsize;             /* 0xFFFC001C */
235} nvram_config;
236
237/*
238 *  Pointer to the base of User Area NVRAM
239 */
240
241#define nvram      ((nvram_config * const) 0xFFFC0000)
242
243#endif
244
245
246/*
247 *  Flag to indicate if J1-4 is on (and parameters should be
248 *  sought in User Area NVRAM)
249 */
250
251#if defined(mvme167)
252#define NVRAM_CONFIGURE \
253  ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
254#else
255#define NVRAM_CONFIGURE 0
256#endif
257
258
259#ifdef __cplusplus
260}
261#endif
262
263#endif
264/* end of include file */
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