source: rtems/c/src/lib/libbsp/m68k/ods68302/startup/cpuboot.c @ 6128a4a

4.104.114.84.9
Last change on this file since 6128a4a was 6128a4a, checked in by Ralf Corsepius <ralf.corsepius@…>, on Apr 21, 2004 at 10:43:04 AM

Remove stray white spaces.

  • Property mode set to 100644
File size: 3.8 KB
Line 
1/*****************************************************************************/
2/*
3  Boot the CPU.
4
5  Occurs in 3 phases for a 68302.
6
7  Phase 1.
8
9  Called as soon as able after reset. The BAR has been programed, and
10  a small stack exists in the DPRAM. All interrupts are masked, and
11  the processor is running in supervisor mode. No other hardware or
12  chip selects are active.
13
14  This phase programs the chip select registers, the parallel ports
15  are set into default configurations, and basic registers cleared or
16  reset. The leds are programmed to show the end of phase 1.
17
18  Phase 2.
19
20  This is a piece of code which is copied to DPRAM and executed. It
21  should not do any more thann is currently present. The return to ROM
22  is managed by modifing the return address. Again leds show the status.
23
24  Phase 3.
25
26  This code executes with a valid C environment. That is the data
27  section has been intialised and the bss section set to 0. This phase
28  performs any special card initialisation and then calls boot card.
29
30  $Id$
31
32*/
33/*****************************************************************************/
34
35#include <bsp.h>
36#include <rtems/m68k/m68302.h>
37#include <debugport.h>
38#include <crc.h>
39
40/*
41  Open the address, reset all registers
42  */
43
44extern int ROM_SIZE, ROM_BASE;
45extern int RAM_SIZE, RAM_BASE;
46
47#define _ROM_SIZE ((unsigned int)&ROM_SIZE)
48#define _ROM_BASE ((unsigned int)&ROM_BASE)
49#define _RAM_SIZE ((unsigned int)&RAM_SIZE)
50#define _RAM_BASE ((unsigned int)&RAM_BASE)
51
52void boot_phase_1()
53{
54  M302_SCR = SCR_DEFAULT;
55
56  WRITE_OR(CSEL_ROM, _ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
57  WRITE_BR(CSEL_ROM, _RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
58  WRITE_OR(CSEL_RAM, _RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
59  WRITE_BR(CSEL_RAM, _ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
60
61#if defined(CSEL_1)
62  WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
63  WRITE_BR(CSEL_1, CSEL_1_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
64#endif
65
66#if defined(CSEL_2)
67  WRITE_OR(CSEL_2, CSEL_2_SIZE, CSEL_2_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
68  WRITE_BR(CSEL_2, CSEL_2_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
69#endif
70
71  m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0;
72  m302.reg.gimr = 0x0080;
73
74  m302.reg.simode = 0;
75
76  m302.reg.pacnt = CARD_PA_CONFIGURATION;
77  m302.reg.paddr = CARD_PA_DEFAULT_DIRECTIONS;
78  m302.reg.padat = CARD_PA_DEFAULT_DATA;
79
80  m302.reg.pbcnt = CARD_PB_CONFIGURATION;
81  m302.reg.pbddr = CARD_PB_DEFAULT_DIRECTIONS;
82  m302.reg.pbdat = CARD_PB_DEFAULT_DATA;
83
84  m302.reg.wrr = WATCHDOG_TIMEOUT_PERIOD | WATCHDOG_ENABLE;
85
86#if defined(LED_CONTROL)
87  LED_CONTROL(LED_1_RED, LED_2_OFF, LED_3_OFF, LED_4_OFF,
88              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
89#endif
90}
91
92/*
93  Swap the chip select mapping for ROM and RAM
94  */
95
96void boot_phase_2(void)
97{
98  uint32_t         stack;
99
100#if defined(LED_CONTROL)
101  LED_CONTROL(LED_1_RED, LED_2_RED, LED_3_OFF, LED_4_OFF,
102              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
103#endif
104
105  WRITE_BR(CSEL_ROM, _ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
106  WRITE_BR(CSEL_RAM, _RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
107
108#if defined(LED_CONTROL)
109  LED_CONTROL(LED_1_GREEN, LED_2_RED, LED_3_OFF, LED_4_OFF,
110              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
111#endif
112
113  /* seems to want 2, looked at assember code output */
114  *((volatile uint32_t*) (&stack + 2)) |= ROM_BASE;
115}
116
117/*
118  Any pre-main initialisation, the C environment is setup, how-ever C++
119  static constructors have not been called, and RTEMS is not initialised.
120  */
121
122void boot_card();
123void set_debug_traps();
124void breakpoint();
125
126void boot_phase_3(void)
127{
128  if (GDB_RUN_MONITOR())
129  {
130    set_debug_traps();
131    breakpoint();
132  }
133
134  debug_port_banner();
135
136  /* FIXME : add RAM and ROM checks */
137
138  /* boot the bsp, what ever this means */
139  boot_card();
140
141  WATCHDOG_TRIGGER();
142}
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