[0074691a] | 1 | /*****************************************************************************/ |
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| 2 | /* |
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| 3 | Boot the CPU. |
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| 4 | |
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| 5 | Occurs in 3 phases for a 68302. |
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| 6 | |
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| 7 | Phase 1. |
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| 8 | |
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| 9 | Called as soon as able after reset. The BAR has been programed, and |
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| 10 | a small stack exists in the DPRAM. All interrupts are masked, and |
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| 11 | the processor is running in supervisor mode. No other hardware or |
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| 12 | chip selects are active. |
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| 13 | |
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| 14 | This phase programs the chip select registers, the parallel ports |
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| 15 | are set into default configurations, and basic registers cleared or |
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| 16 | reset. The leds are programmed to show the end of phase 1. |
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| 17 | |
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| 18 | Phase 2. |
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| 19 | |
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| 20 | This is a piece of code which is copied to DPRAM and executed. It |
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| 21 | should not do any more thann is currently present. The return to ROM |
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| 22 | is managed by modifing the return address. Again leds show the status. |
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| 23 | |
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| 24 | Phase 3. |
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| 25 | |
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| 26 | This code executes with a valid C environment. That is the data |
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| 27 | section has been intialised and the bss section set to 0. This phase |
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| 28 | performs any special card initialisation and then calls boot card. |
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| 29 | |
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| 30 | $Id$ |
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| 31 | |
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| 32 | */ |
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| 33 | /*****************************************************************************/ |
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| 34 | |
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| 35 | #include <bsp.h> |
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| 36 | #include <m68302.h> |
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| 37 | #include <debugport.h> |
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| 38 | #include <crc.h> |
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| 39 | |
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| 40 | /* |
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| 41 | Open the address, reset all registers |
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| 42 | */ |
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| 43 | |
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| 44 | void boot_phase_1() |
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| 45 | { |
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| 46 | M302_SCR = SCR_DEFAULT; |
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| 47 | |
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| 48 | WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC); |
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| 49 | WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED); |
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| 50 | WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC); |
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| 51 | WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED); |
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| 52 | |
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| 53 | #if defined(CSEL_1) |
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| 54 | WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC); |
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| 55 | WRITE_BR(CSEL_1, CSEL_1_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED); |
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| 56 | #endif |
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| 57 | |
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| 58 | #if defined(CSEL_2) |
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| 59 | WRITE_OR(CSEL_2, CSEL_2_SIZE, CSEL_2_WAIT_STATES, OR_MASK_RW, OR_MASK_FC); |
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| 60 | WRITE_BR(CSEL_2, CSEL_2_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED); |
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| 61 | #endif |
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| 62 | |
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| 63 | m302.reg.gimr = m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0; |
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| 64 | |
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| 65 | m302.reg.simode = 0; |
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| 66 | |
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| 67 | m302.reg.pacnt = CARD_PA_CONFIGURATION; |
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| 68 | m302.reg.paddr = CARD_PA_DEFAULT_DIRECTIONS; |
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| 69 | m302.reg.padat = CARD_PA_DEFAULT_DATA; |
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| 70 | |
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| 71 | m302.reg.pbcnt = CARD_PB_CONFIGURATION; |
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| 72 | m302.reg.pbddr = CARD_PB_DEFAULT_DIRECTIONS; |
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| 73 | m302.reg.pbdat = CARD_PB_DEFAULT_DATA; |
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| 74 | |
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| 75 | m302.reg.wrr = WATCHDOG_TIMEOUT_PERIOD | WATCHDOG_ENABLE; |
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| 76 | |
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| 77 | #if defined(LED_CONTROL) |
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| 78 | LED_CONTROL(LED_1_RED, LED_2_OFF, LED_3_OFF, LED_4_OFF, |
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| 79 | LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF); |
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| 80 | #endif |
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| 81 | } |
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| 82 | |
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| 83 | /* |
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| 84 | Swap the chip select mapping for ROM and RAM |
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| 85 | */ |
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| 86 | |
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| 87 | void boot_phase_2(void) |
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| 88 | { |
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| 89 | rtems_unsigned32 stack; |
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| 90 | |
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| 91 | #if defined(LED_CONTROL) |
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| 92 | LED_CONTROL(LED_1_RED, LED_2_RED, LED_3_OFF, LED_4_OFF, |
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| 93 | LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF); |
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| 94 | #endif |
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| 95 | |
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| 96 | WRITE_BR(CSEL_ROM, ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED); |
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| 97 | WRITE_BR(CSEL_RAM, RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED); |
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| 98 | |
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| 99 | #if defined(LED_CONTROL) |
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| 100 | LED_CONTROL(LED_1_GREEN, LED_2_RED, LED_3_OFF, LED_4_OFF, |
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| 101 | LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF); |
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| 102 | #endif |
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| 103 | |
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| 104 | /* seems to want 2, looked at assember code output */ |
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| 105 | *(&stack + 2) |= ROM_BASE; |
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| 106 | } |
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| 107 | |
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| 108 | /* |
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| 109 | Any pre-main initialisation, the C environment is setup, how-ever C++ |
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| 110 | static constructors have not been called, and RTEMS is not initialised. |
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| 111 | */ |
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| 112 | |
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[e2a2ec60] | 113 | void boot_card(); |
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[0074691a] | 114 | void set_debug_traps(); |
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| 115 | void breakpoint(); |
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| 116 | |
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| 117 | void boot_phase_3(void) |
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| 118 | { |
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| 119 | if (GDB_RUN_MONITOR()) |
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| 120 | { |
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| 121 | set_debug_traps(); |
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| 122 | breakpoint(); |
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| 123 | } |
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| 124 | |
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| 125 | debug_port_banner(); |
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| 126 | |
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| 127 | /* FIXME : add RAM and ROM checks */ |
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| 128 | |
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| 129 | /* boot the bsp, what ever this means */ |
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[e2a2ec60] | 130 | boot_card(); |
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[0074691a] | 131 | |
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| 132 | WATCHDOG_TRIGGER(); |
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| 133 | } |
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