source: rtems/c/src/lib/libbsp/m68k/ods68302/start302/cpuboot.c @ 674c900

4.104.114.84.95
Last change on this file since 674c900 was 0074691, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 31, 1997 at 10:13:29 PM

Merged very large and much appreciated patch from Chris Johns
<cjohns@…>. This patch includes the ods68302 bsp,
the RTEMS++ class library, and the rtems++ test.

  • Property mode set to 100644
File size: 3.5 KB
Line 
1/*****************************************************************************/
2/*
3  Boot the CPU.
4
5  Occurs in 3 phases for a 68302.
6
7  Phase 1.
8
9  Called as soon as able after reset. The BAR has been programed, and
10  a small stack exists in the DPRAM. All interrupts are masked, and
11  the processor is running in supervisor mode. No other hardware or
12  chip selects are active.
13
14  This phase programs the chip select registers, the parallel ports
15  are set into default configurations, and basic registers cleared or
16  reset. The leds are programmed to show the end of phase 1.
17
18  Phase 2.
19
20  This is a piece of code which is copied to DPRAM and executed. It
21  should not do any more thann is currently present. The return to ROM
22  is managed by modifing the return address. Again leds show the status.
23
24  Phase 3.
25
26  This code executes with a valid C environment. That is the data
27  section has been intialised and the bss section set to 0. This phase
28  performs any special card initialisation and then calls boot card.
29 
30  $Id$
31 
32*/
33/*****************************************************************************/
34
35#include <bsp.h>
36#include <m68302.h>
37#include <debugport.h>
38#include <crc.h>
39
40/*
41  Open the address, reset all registers
42  */
43
44void boot_phase_1()
45{
46  M302_SCR = SCR_DEFAULT;
47
48  WRITE_OR(CSEL_ROM, ROM_SIZE, ROM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
49  WRITE_BR(CSEL_ROM, RAM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
50  WRITE_OR(CSEL_RAM, RAM_SIZE, RAM_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
51  WRITE_BR(CSEL_RAM, ROM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
52
53#if defined(CSEL_1)
54  WRITE_OR(CSEL_1, CSEL_1_SIZE, CSEL_1_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
55  WRITE_BR(CSEL_1, CSEL_1_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
56#endif
57 
58#if defined(CSEL_2)
59  WRITE_OR(CSEL_2, CSEL_2_SIZE, CSEL_2_WAIT_STATES, OR_MASK_RW, OR_MASK_FC);
60  WRITE_BR(CSEL_2, CSEL_2_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
61#endif
62 
63  m302.reg.gimr = m302.reg.ipr = m302.reg.imr = m302.reg.isr = 0;
64 
65  m302.reg.simode = 0;
66
67  m302.reg.pacnt = CARD_PA_CONFIGURATION;
68  m302.reg.paddr = CARD_PA_DEFAULT_DIRECTIONS;
69  m302.reg.padat = CARD_PA_DEFAULT_DATA;
70
71  m302.reg.pbcnt = CARD_PB_CONFIGURATION;
72  m302.reg.pbddr = CARD_PB_DEFAULT_DIRECTIONS;
73  m302.reg.pbdat = CARD_PB_DEFAULT_DATA;
74
75  m302.reg.wrr = WATCHDOG_TIMEOUT_PERIOD | WATCHDOG_ENABLE;
76
77#if defined(LED_CONTROL)
78  LED_CONTROL(LED_1_RED, LED_2_OFF, LED_3_OFF, LED_4_OFF,
79              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
80#endif 
81}
82
83/*
84  Swap the chip select mapping for ROM and RAM
85  */
86
87void boot_phase_2(void)
88{
89  rtems_unsigned32 stack;
90 
91#if defined(LED_CONTROL)
92  LED_CONTROL(LED_1_RED, LED_2_RED, LED_3_OFF, LED_4_OFF,
93              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
94#endif
95 
96  WRITE_BR(CSEL_ROM, ROM_BASE, BR_READ_ONLY, BR_FC_NULL, BR_ENABLED);
97  WRITE_BR(CSEL_RAM, RAM_BASE, BR_READ_WRITE, BR_FC_NULL, BR_ENABLED);
98 
99#if defined(LED_CONTROL)
100  LED_CONTROL(LED_1_GREEN, LED_2_RED, LED_3_OFF, LED_4_OFF,
101              LED_5_OFF, LED_6_OFF, LED_7_OFF, LED_8_OFF);
102#endif
103
104  /* seems to want 2, looked at assember code output */
105  *(&stack + 2) |= ROM_BASE;
106}
107
108/*
109  Any pre-main initialisation, the C environment is setup, how-ever C++
110  static constructors have not been called, and RTEMS is not initialised.
111  */
112
113void boot_bsp();
114void set_debug_traps();
115void breakpoint();
116
117void boot_phase_3(void)
118{
119  if (GDB_RUN_MONITOR())
120  {
121    set_debug_traps();
122    breakpoint();
123  }
124 
125  debug_port_banner();
126 
127  /* FIXME : add RAM and ROM checks */
128 
129  /* boot the bsp, what ever this means */
130  boot_bsp();
131
132  WATCHDOG_TRIGGER();
133}
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