1 | /*****************************************************************************/ |
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2 | /* |
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3 | $Id$ |
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4 | |
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5 | Card Definition for a bare board. |
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6 | |
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7 | This is an example file which actually builds a BSP for a 68302 card |
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8 | called an MVF (Multi-Voice-Frequency). The card is one of a range |
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9 | which run in a 100Mbit voice/video/data switch used for high end |
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10 | applications such as Air Traffic Control. The transport is |
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11 | FDDI-2. Yes it alive and well and working in real systems. |
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12 | |
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13 | Chip selects are programmed as required. Three are controlled in the |
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14 | boot code. They are RAM, ROM, and peripherals. You can optionally |
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15 | configure the other two chip selects. |
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16 | |
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17 | SYSTEM_CLOCK - You must defined this. It is used for setting the |
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18 | baud rate. |
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19 | |
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20 | CSEL_ROM, CSEL_RAM - Must be defined, and made to be a single number |
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21 | with brackets. |
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22 | |
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23 | ROM_WAIT_STATES, RAM_WAIT_STATES - Must be defined. This sets the |
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24 | speed for the ROM and RAM. |
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25 | |
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26 | ROM and RAM size is passed on the command line. The makefile holds |
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27 | them. This allows a single place to defined it. The makefile allows |
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28 | them to be passed to the linker. |
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29 | |
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30 | CSEL_1, CSEL_2 - If defined the other macros needed to define the |
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31 | chip select must be defined. If not defined they are not programmed |
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32 | and registers are left in the reset state. |
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33 | |
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34 | Card Specific Devices - The MVF card uses a chip select to address a |
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35 | range of peripherials (CSEL_2). These include front panel leds, and |
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36 | 4 digit diagnostic display device. Put what ever you need. |
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37 | |
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38 | LED_CONTROL - If defined the boot code will set leds as it goes. |
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39 | |
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40 | UPDATE_DISPLAY - A four digit display device will also be updated to |
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41 | show the boot state. |
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42 | |
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43 | CARD_PA, CARD_PB - The default configuration, data direction and |
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44 | data must be specified. |
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45 | |
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46 | This file allows a range of common parameters which vary from one |
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47 | variant of card to another to placed in a central file. |
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48 | |
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49 | */ |
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50 | /*****************************************************************************/ |
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51 | |
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52 | #ifndef _BARE_H_ |
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53 | #define _BARE_H_ |
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54 | |
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55 | #if __cplusplus |
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56 | extern "C" |
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57 | { |
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58 | #endif |
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59 | |
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60 | /* name of the card */ |
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61 | #define CARD_ID "m68302-odsbare" |
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62 | |
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63 | /* speed of the processor */ |
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64 | #define SYSTEM_CLOCK (15360000) |
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65 | |
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66 | #define SCR_DEFAULT (RBIT_SCR_IPA | RBIT_SCR_HWT | RBIT_SCR_WPV | RBIT_SCR_ADC | \ |
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67 | RBIT_SCR_HWDEN | RBIT_SCR_HWDCN1 | RBIT_SCR_EMWS) |
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68 | |
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69 | /* define the chip selects */ |
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70 | #define CSEL_ROM 0 /* token pasted so no brackets */ |
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71 | #define ROM_WAIT_STATES (OR_DTACK_1) /* 100nsec at 16MHz */ |
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72 | #define CSEL_RAM 3 |
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73 | #define RAM_WAIT_STATES (OR_DTACK_0) /* 70nsec at 16MHz */ |
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74 | |
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75 | /* The remaining chip selects are called 1 and 2 */ |
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76 | /* |
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77 | #define CSEL_1 1 |
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78 | #define CSEL_1_BASE (0x00?00000) |
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79 | #define CSEL_1_SIZE (0x00?00000) |
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80 | #define CSEL_1_WAIT_STATES (OR_DTACK_1) |
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81 | */ |
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82 | #define CSEL_2 2 |
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83 | #define CSEL_2_BASE (0x00800000) |
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84 | #define CSEL_2_SIZE (0x00040000) |
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85 | #define CSEL_2_WAIT_STATES (OR_DTACK_EXT) |
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86 | |
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87 | /* |
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88 | * Need to define a watchdog period |
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89 | */ |
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90 | #define WATCHDOG_TIMEOUT_PERIOD (3000 * 2) |
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91 | |
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92 | /* |
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93 | * Console and debug port allocation, 0=SCC1, 2=SCC3 |
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94 | */ |
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95 | |
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96 | #define CONSOLE_PORT 1 |
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97 | #define CONSOLE_BAUD SCC_9600 |
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98 | #define DEBUG_PORT 2 |
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99 | #define DEBUG_BAUD SCC_57600 |
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100 | |
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101 | /* ---- |
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102 | Parallel Port Configuration, and default data directions |
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103 | |
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104 | PORT BITS - NAME , WHO , DEFAULT WHAT |
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105 | ------------------------------------------------------------ |
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106 | PPA:: 1: 0 - Serial , PERIPHERAL, - |
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107 | PPA:: 7: 2 - MVF_PPA:7:2 , IO , INPUTS |
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108 | PPA:: 9: 8 - Serial , PERIPHERAL, - |
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109 | PPA::15:10 - MVF_PPB:15:10 , IO , INPUTS |
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110 | |
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111 | PPB:: 1: 0 - Setup , IO , INPUTS |
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112 | PPB:: 3: 2 - SYNC_HIGHWAY_1:2 , IO , INPUTS |
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113 | - SYNC_HIGHWAY_2:3 , IO , INPUTS |
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114 | PPB:: 4: 4 - HARDWARE_RESET:4 , IO , OUTPUT |
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115 | PPB:: 6: 5 - SOFTWARE_OVERRIDE_1:6, IO , OUTPUT |
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116 | - SOFTWARE_OVERRIDE_2:5, IO , OUTPUT |
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117 | PPB:: 7: 7 - Watchdog , PERIPHERAL, - |
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118 | PPB::11: 8 - Interrupt , PERIPHERAL, - |
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119 | PPB::15:12 - Not implemented on the 68302 |
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120 | |
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121 | 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 |
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122 | ------------------------------------------------------ |
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123 | PACNT 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 = 0x0303 |
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124 | PBCNT - - - - - - - - 1 0 0 0 0 0 0 0 = 0x0080 |
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125 | |
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126 | PADDR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0x0000 |
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127 | PBDDR 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 = 0x0070 |
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128 | |
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129 | PADAT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 = 0x0000 |
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130 | |
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131 | */ |
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132 | #define CARD_PA_CONFIGURATION 0x0303 |
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133 | #define CARD_PB_CONFIGURATION 0x0080 |
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134 | |
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135 | #define CARD_PA_DEFAULT_DIRECTIONS 0x0000 |
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136 | #define CARD_PB_DEFAULT_DIRECTIONS 0x0070 |
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137 | |
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138 | #define CARD_PA_DEFAULT_DATA 0x0000 |
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139 | #define CARD_PB_DEFAULT_DATA (HARDWARE_RESET_DISABLE | \ |
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140 | SOFTWARE_OVERRIDE_1_DISABLE | \ |
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141 | SOFTWARE_OVERRIDE_2_DISABLE) |
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142 | |
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143 | /* these are specific to the card and are not required */ |
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144 | #define HARDWARE_RESET_ENABLE 0x0000 |
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145 | #define HARDWARE_RESET_DISABLE 0x0010 |
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146 | |
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147 | #define SOFTWARE_OVERRIDE_1_ENABLE 0x0000 |
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148 | #define SOFTWARE_OVERRIDE_1_DISABLE 0x0040 |
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149 | #define SOFTWARE_OVERRIDE_2_ENABLE 0x0000 |
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150 | #define SOFTWARE_OVERRIDE_2_DISABLE 0x0020 |
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151 | |
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152 | /* |
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153 | * Card Specific Devices, these are not required. Add what ever you |
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154 | * like here. |
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155 | */ |
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156 | |
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157 | /* Write */ |
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158 | #define WRITE_REGISTER_8(address, data) \ |
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159 | *((rtems_unsigned8 *) (address)) = ((rtems_unsigned8) (data)) |
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160 | #define WRITE_REGISTER_16(address, data) \ |
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161 | *((rtems_unsigned16 *) (address)) = ((rtems_unsigned16) (data)) |
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162 | #define WRITE_REGISTER_32(address, data) \ |
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163 | *((rtems_unsigned32 *) (address)) = ((rtems_unsigned32) (data)) |
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164 | /* Read */ |
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165 | #define READ_REGISTER_8(address, data) data = *((rtems_unsigned8 *) (address)) |
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166 | #define READ_REGISTER_16(address, data) data = *((rtems_unsigned16 *) (address)) |
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167 | #define READ_REGISTER_32(address, data) data = *((rtems_unsigned32 *) (address)) |
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168 | |
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169 | /* CS2 : Peripherials */ |
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170 | #define PERIPHERIALS_BASE (CSEL_2_BASE) |
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171 | |
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172 | #define STATUS_REGISTER_BASE (PERIPHERIALS_BASE + 0x00000000) |
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173 | |
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174 | #define PERIPHERIALS_SIZE (0x00040000) |
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175 | |
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176 | #define LEDS_BASE (PERIPHERIALS_BASE + 0x00004000) |
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177 | #define MSC_BASE (PERIPHERIALS_BASE + 0x00008000) |
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178 | #define SPARE_1_BASE (PERIPHERIALS_BASE + 0x0000C000) |
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179 | #define DISPLAY_BASE (PERIPHERIALS_BASE + 0x00010000) |
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180 | #define PIO_INT_BASE (PERIPHERIALS_BASE + 0x00014000) |
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181 | #define UART_BASE (PERIPHERIALS_BASE + 0x00018000) |
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182 | #define PIA_BASE (PERIPHERIALS_BASE + 0x0001C000) |
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183 | |
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184 | #define LED_1 0x0002 |
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185 | #define LED_1_GREEN 0xFFFD |
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186 | #define LED_1_RED 0xFFFF |
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187 | #define LED_1_OFF 0xFFFC |
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188 | |
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189 | #define LED_2 0x0001 |
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190 | #define LED_2_GREEN 0xFFFE |
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191 | #define LED_2_RED 0xFFFF |
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192 | #define LED_2_OFF 0xFFFC |
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193 | |
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194 | #define LED_3 0x0000 |
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195 | #define LED_3_GREEN 0xFFFC |
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196 | #define LED_3_RED 0xFFFC |
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197 | #define LED_3_OFF 0xFFFC |
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198 | |
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199 | #define LED_4 0x0000 |
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200 | #define LED_4_GREEN 0xFFFC |
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201 | #define LED_4_RED 0xFFFC |
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202 | #define LED_4_OFF 0xFFFC |
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203 | |
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204 | #define LED_5 0x0000 |
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205 | #define LED_5_GREEN 0xFFFC |
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206 | #define LED_5_RED 0xFFFC |
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207 | #define LED_5_OFF 0xFFFC |
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208 | |
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209 | #define LED_6 0x0000 |
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210 | #define LED_6_GREEN 0xFFFC |
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211 | #define LED_6_RED 0xFFFC |
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212 | #define LED_6_OFF 0xFFFC |
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213 | |
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214 | #define LED_7 0x0000 |
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215 | #define LED_7_GREEN 0xFFFC |
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216 | #define LED_7_RED 0xFFFC |
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217 | #define LED_7_OFF 0xFFFC |
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218 | |
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219 | #define LED_8 0x0000 |
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220 | #define LED_8_GREEN 0xFFFC |
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221 | #define LED_8_RED 0xFFFC |
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222 | #define LED_8_OFF 0xFFFC |
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223 | |
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224 | #define MAKE_LED(L1, L2, L3, L4) ((L1 & LED_1) | (L2 & LED_2) | (L3 & LED_3) | (L4 & LED_4)) |
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225 | |
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226 | #define LED_CONTROL(L1, L2, L3, L4, L5, L6, L7, L8) \ |
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227 | WRITE_REGISTER_16(LEDS_BASE, MAKE_LED(L1, L2, L3, L4)) |
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228 | |
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229 | /* update the display, needs a long word */ |
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230 | #define UPDATE_DISPLAY(LongWordPtr) \ |
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231 | ( WRITE_REGISTER_16(DISPLAY_BASE, *(((rtems_unsigned8 *) LongWordPtr) + 3)), \ |
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232 | WRITE_REGISTER_16(DISPLAY_BASE + 2, *(((rtems_unsigned8 *) LongWordPtr) + 2)), \ |
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233 | WRITE_REGISTER_16(DISPLAY_BASE + 4, *(((rtems_unsigned8 *) LongWordPtr) + 1)), \ |
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234 | WRITE_REGISTER_16(DISPLAY_BASE + 6, *((rtems_unsigned8 *) LongWordPtr)) ) |
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235 | |
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236 | /* make a better test, say switches */ |
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237 | #if defined(GDB_MONITOR_ACTIVE) |
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238 | #define GDB_RUN_MONITOR() (1 == 1) |
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239 | #else |
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240 | #define GDB_RUN_MONITOR() (1 == 0) |
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241 | #endif |
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242 | |
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243 | #if __cplusplus |
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244 | } |
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245 | #endif |
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246 | #endif |
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