source: rtems/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c @ ed09fd77

4.104.114.84.95
Last change on this file since ed09fd77 was ed09fd77, checked in by Joel Sherrill <joel.sherrill@…>, on 08/11/00 at 19:26:31

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

  • README: Updated
  • console/console.c: Fix polled input. Add support for shared printk. Add support for more flexible polled I/O with and without termios. I/O mode and console is selectable either from NVRAM or from mvme167.cfg. Clean up comments.

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

  • startup/page_table.c (page_table_init): Reorganize NVRAM parameters.
  • include/bsp.h: Reorganize NVRAM parameters. Add support for shared printk.
  • times: These are the times for the MVME167, not the MBX860-002.

2000-08-11 John Cotton <john.cotton@…>

  • network/network.c: Fix NVRAM configuration parameter handling from previous revision. Check J1-4, restructure NVRAM parameter handling.

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

  • network/network.c: Cleanup of network driver to reduce warnings. Addition of second parameter to uti596_attach.
  • Property mode set to 100644
File size: 5.9 KB
Line 
1/*  page_table.c
2 *
3 *  The code submitted by Eric Vaitl <vaitl@viasat.com> for the MVME162 appears
4 *  to be for a uniprocessor implementation. The function that sets up the
5 *  page tables, page_table_init(), is not data driven. For all processors, it
6 *  sets up page tables to map virtual addresses from 0x20000 to 0x3FFFFF to
7 *  physical addresses 0x20000 to 0x3FFFFF. This presumably maps a subset of
8 *  a local 4 MB space, which is probably the amount of RAM on Eric Vailt's
9 *  MVME162.
10 *
11 *  It is possible to set up the various bus bridges in the MVME167s to create
12 *  a flat physical address space across multiple boards, i.e., it is possible
13 *  for each MVME167 in a multiprocessor system to access a given memory
14 *  location using the same physical address, whether that location is in local
15 *  or VME space. Addres translation can be set up so that each virtual address
16 *  maps to its corresponding physical address, e.g. virtual address 0x12345678
17 *  is mapped to physical address 0x12345678. With this mapping, the MMU is
18 *  only used to control the caching modes for the various regions of memory.
19 *  Mapping the virtual addresses to their corresponding physical address makes
20 *  it unnecessary to map addresses under software control during the
21 *  initialization of RTEMS, before address translation is turned on.
22 *
23 *  With the above approach, address translation may be set up either with the
24 *  transparent address translation registers, or with page tables. If page
25 *  tables are used, a more efficient use of page table space can be achieved
26 *  by sharing the page tables between processors. The entire page table tree
27 *  can be shared, or each processor can hold a private copy of the top nodes
28 *  which point to leaf nodes stored on individual processors.
29 *
30 *  In this port, only the transparent address translation registers are used.
31 *  We map the entire virtual range from 0x0 to 0x7FFFFFFF to the identical
32 *  physical range 0x0 to 0x7FFFFFFF. We rely on the hardware to signal bus
33 *  errors if we address non-existent memory within this range. Our two
34 *  MVME167s are configured to exist at physical addresses 0x00800000 to
35 *  0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. If jumper J1-4 is
36 *  installed, memory and cache control can be done by providing parameters
37 *  in NVRAM and jumpers J1-[5-7] are ignored. See the README for details.
38 *  If J1-4 is removed, behaviour defaults to the following. We map the space
39 *  from 0x0 to 0x7FFFFFFF as copyback, unless jumper J1-5 is removed, in which
40 *  case we map as writethrough. If jumper J1-7 is removed, the data cache is
41 *  NOT enabled. If jumper J1-6 is removed, the instruction cache is not enabled.
42 *
43 *  Copyright (c) 1998, National Research Council of Canada
44 *
45 *  $Id$
46 */
47
48#include <bsp.h>
49#include <page_table.h>                 /* Nothing in here for us */
50
51/*
52 *  page_table_init
53 * 
54 *  Map the virtual range 0x00000000--0x7FFFFFFF to the physical range
55 *  0x00000000--0x7FFFFFFF. Rely on the hardware to raise exceptions when
56 *  addressing non-existent memory. Use only the transparent translation
57 *  registers (for now).
58 *
59 *  On all processors, the local virtual address range 0xFF000000--0xFFFFFFFF
60 *  is mapped to the physical address range 0xFF000000--0xFFFFFFFF as
61 *  caching disabled, serialized access.
62 *
63 *  Input parameters:
64 *    config_table - ignored for now
65 *
66 *  Output parameters: NONE
67 *
68 *  Return values: NONE
69 */
70void page_table_init(
71  rtems_configuration_table *config_table
72)
73{
74  unsigned char j1;               /* State of J1 jumpers */
75  register unsigned long dtt0;    /* Content of dtt0 */
76  register unsigned long cacr;    /* Content of cacr */
77 
78  /*
79   *  Logical base addr = 0x00    map starting at 0x00000000
80   *  Logical address mask = 0x7F map up to 0x7FFFFFFF
81   *  E = 0b1                     enable address translation
82   *  S-Field = 0b1X              ignore FC2 when matching
83   *  U1, U0 = 0b00               user page attributes not used
84   *  CM = 0b01                   cachable, copyback
85   *  W = 0b0                     read/write access allowed
86   */
87  dtt0 = 0x007FC020;
88 
89  cacr = 0x00000000;              /* Data and instruction cache off */
90 
91  /* Read the J1 header */
92  j1 = (unsigned char)(lcsr->vector_base & 0xFF);
93
94  if ( !(j1 & 0x10) ) {
95        /* Jumper J1-4 is on, configure from NVRAM */
96
97        if ( nvram->cache_mode & 0x01 )
98                cacr |= 0x80000000;
99
100        if ( nvram->cache_mode & 0x02 )
101                cacr |= 0x00008000;
102
103        if ( nvram->cache_mode )
104                dtt0 = ((nvram->cache_mode & 0x0C) << 3) | (dtt0 & 0xFFFFFF9F);
105  }
106        else {
107                /* Configure according to other jumper settings */
108 
109          if ( !(j1 & 0x80) )
110          /* Jumper J1-7 if on, enable data caching */
111                cacr |= 0x80000000;
112     
113          if ( !(j1 & 0x40) )
114            /* Jumper J1-6 if on, enable instruction caching */
115            cacr |= 0x00008000;
116     
117          if ( j1 & 0x20 )
118            /* Jumper J1-5 is off, enable writethrough caching */
119            dtt0 &= 0xFFFFFF9F;
120        }
121
122  /* do it ! */
123  asm volatile("movec %0, %%tc    /* turn off paged address translation */
124                movec %0, %%cacr  /* disable both caches */
125                cinva %%bc        /* clear both caches */
126                movec %1,%%dtt0   /* block address translation on */
127                movec %1,%%itt0
128                movec %2,%%dtt1
129                movec %2,%%itt1
130                movec %3,%%cacr"  /* data cache on */
131          :: "d" (0), "d" (dtt0), "d" (0xFF00C040), "d" (cacr));
132}
133
134 
135/*
136 *  page_table_teardown
137 *
138 *  Turn off paging. Turn off the cache. Flush the cache. Tear down
139 *  the transparent translations.
140 *
141 *  Input parameters: NONE
142 *
143 *  Output parameters: NONE
144 *
145 *  Return values: NONE
146 */
147void page_table_teardown( void )
148{
149  asm volatile ("movec %0,%%tc
150                 movec %0,%%cacr
151                 cpusha %%bc
152                 movec %0,%%dtt0
153                 movec %0,%%itt0
154                 movec %0,%%dtt1
155                 movec %0,%%itt1"
156    :: "d" (0) );
157}
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