source: rtems/c/src/lib/libbsp/m68k/mvme167/include/bsp.h @ f68401e

4.115
Last change on this file since f68401e was 72d0926, checked in by Joel Sherrill <joel.sherrill@…>, on 01/08/13 at 16:45:35

m68k/mvme167: Compiles again

Was including non-existent .h file.
Fixed some warnings.
Reformatted file header comment blocks.
  • Property mode set to 100644
File size: 13.7 KB
Line 
1/**
2 *  @file
3 *
4 *  Following defines must reflect the setup of the particular MVME167.
5 *  All page references are to the MVME166/MVME167/MVME187 Single Board
6 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
7 *  1993 supplements/addenda (MVME187PG/D2A1).
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2012.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.com/license/LICENSE.
17 *
18 *  Modifications of respective RTEMS file:
19 *  Copyright (c) 1998, National Research Council of Canada
20 */
21
22#ifndef _BSP_H
23#define _BSP_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <bspopts.h>
30#include <bsp/default-initial-extension.h>
31
32#include <rtems.h>
33#include <rtems/clockdrv.h>
34#include <rtems/console.h>
35#include <rtems/iosupp.h>
36#include <rtems/bspIo.h>
37
38#include <mvme16x_hw.h>
39
40/* GCSR is in mvme16x_hw.h */
41/* LCSR is in mvme16x_hw.h */
42/* i82596 is in mvme16x_hw.h */
43/* NVRAM is in mvme16x_hw.h */
44
45#if 0
46/*
47 *  Representation of the PCCchip2
48 */
49typedef volatile struct pccchip2_regs_ {
50  unsigned char     chip_id;            /* 0xFFF42000 */
51  unsigned char     chip_revision;      /* 0xFFF42001 */
52  unsigned char     gen_control;        /* 0xFFF42002 */
53  unsigned char     vector_base;        /* 0xFFF42003 */
54  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
55  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
56  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
57  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
58  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
59  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
60  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
61  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
62  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
63  unsigned char     gpio_ctl;           /* 0xFFF42019 */
64  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
65  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
66  unsigned char     SCC_error;          /* 0xFFF4201C */
67  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
68  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
69  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
70  unsigned char     reserved1[3];
71  unsigned char     modem_piack;        /* 0xFFF42023 */
72  unsigned char     reserved2;
73  unsigned char     tx_piack;           /* 0xFFF42025 */
74  unsigned char     reserved3;
75  unsigned char     rx_piack;           /* 0xFFF42027 */
76  unsigned char     LANC_error;         /* 0xFFF42028 */
77  unsigned char     reserved4;
78  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
79  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
80  unsigned char     SCSI_error;         /* 0xFFF4202C */
81  unsigned char     reserved5[2];
82  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
83  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
84  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
85  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
86  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
87  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
88  unsigned char     reserved6;
89  unsigned char     print_input_status; /* 0xFFF42036 */
90  unsigned char     print_ctl;          /* 0xFFF42037 */
91  unsigned char     chip_speed;         /* 0xFFF42038 */
92  unsigned char     reserved7;
93  unsigned char     print_data;         /* 0xFFF4203A */
94  unsigned char     reserved8[3];
95  unsigned char     int_level;          /* 0xFFF4203E */
96  unsigned char     int_mask;           /* 0xFFF4203F */
97} pccchip2_regs;
98
99/*
100 *  Base address of the PCCchip2.
101 *  This is not configurable in the MVME167.
102 */
103#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
104
105#endif
106/*
107 * The MVME167 is equiped with one or two MEMC040 memory controllers at
108 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
109 * were initialized by 167Bug.
110 */
111typedef volatile struct memc040_regs_ {
112  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
113  unsigned char     reserved1[3];
114  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
115  unsigned char     reserved2[3];
116  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
117  unsigned char     reserved3[3];
118  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
119  unsigned char     reserved4[3];
120  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
121  unsigned char     reserved5[3];
122  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
123  unsigned char     reserved6[3];
124  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
125  unsigned char     reserved7[3];
126  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
127} memc040_regs;
128
129/*
130 *  Base address of the MEMC040s.
131 *  This is not configurable in the MVME167.
132 */
133#define memc040_1   ((memc040_regs * const) 0xFFF43000)
134#define memc040_2   ((memc040_regs * const) 0xFFF43100)
135
136/*
137 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
138 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
139 *  assumes that these controllers, if present, are initialized by 167Bug.
140 *  They do not appear to hold information of interest at this time, so they
141 *  are not described. However, each MCECC pair lives at the same address as
142 *  the MEMC040 is replaces. The first eight registers of the MCECC are
143 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
144 *  can be used to read those first eight registers.
145 */
146
147/*
148 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
149 */
150typedef volatile struct cd2401_regs_ {
151  unsigned char     reserved1[7];
152  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
153  unsigned char     reserved2;
154  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
155  unsigned char     reserved3[6];
156  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
157  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
158  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
159  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
160  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
161  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
162  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
163  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
164  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
165  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
166  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
167  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
168  union {
169    struct {
170      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
171      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
172      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
173      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
174    } async;
175    struct {
176      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
177      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
178      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
179      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
180    } sync;
181  } u1;
182  unsigned char     reserved4[2];
183  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
184  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
185  union {
186    struct {
187      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
188    } w;
189    struct {
190      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
191      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
192    } b;
193  } u2;
194  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
195  unsigned char     reserved5[2];
196  union {
197    struct {
198      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
199    } async;
200    struct {
201      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
202    } sync;
203  } u3;
204  union {
205    struct {
206      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
207    } w;
208    struct {
209      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
210      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
211    } b;
212  } u4;
213  unsigned char     reserved6[2];
214  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
215  unsigned char     reserved7;
216  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
217  unsigned char     reserved8[7];
218  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
219  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
220  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
221  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
222  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
223  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
224  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
225  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
226  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
227  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
228  unsigned short    reserved9;
229  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
230  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
231  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
232  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
233  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
234  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
235  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
236  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
237  unsigned short    reserved10;
238  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
239  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
240  unsigned char     reserved11[32];
241  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
242  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
243  unsigned char     reserved12[2];
244  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
245  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
246  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
247  union {
248    struct {
249      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
250    } w;
251    struct {
252      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
253      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
254    } b;
255  } u5;
256  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
257  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
258  unsigned char     reserved13[2];
259  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
260  unsigned char     reserved14[49];
261  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
262  unsigned char     reserved15[2];
263  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
264  unsigned char     reserved16[4];
265  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
266  unsigned char     reserved17[2];
267  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
268  unsigned char     reserved18[10];
269  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
270  unsigned char     reserved19[3];
271  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
272  unsigned char     reserved20[3];
273  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
274  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
275  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
276  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
277  unsigned char     stk;            /* 0xFFF450E2 - Stack */
278  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
279  unsigned char     reserved21[8];
280  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
281  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
282  unsigned char     car;            /* 0xFFF450EE - Channel Access */
283  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
284  unsigned char     reserved22[6];
285  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
286  unsigned char     reserved23;
287  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
288} cd2401_regs;
289
290/*
291 *  Base address of the CD2401.
292 *  This is not configurable in the MVME167.
293 */
294#define cd2401          ((cd2401_regs * const) 0xFFF45000)
295
296/* CD2401 is clocked at 20 MHz */
297#define CD2401_CLK_RATE 20000000
298
299/* BSP-wide functions */
300
301rtems_isr_entry set_vector(
302  rtems_isr_entry     handler,
303  rtems_vector_number vector,
304  int                 type
305);
306
307#ifdef M167_INIT
308#undef EXTERN
309#define EXTERN
310#else
311#undef EXTERN
312#define EXTERN extern
313#endif
314
315extern void *M68Kvec[];   /* vector table address */
316
317#ifdef __cplusplus
318}
319#endif
320
321#endif
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