source: rtems/c/src/lib/libbsp/m68k/mvme167/include/bsp.h @ db9ae70

4.104.114.84.95
Last change on this file since db9ae70 was db9ae70, checked in by Joel Sherrill <joel.sherrill@…>, on 07/26/00 at 21:15:27

Patch from Charles-Antoine Gauthier <charles.gauthier@…> that
removes warnings from the network.c file and has slight additions
to the configuration file to support Java.

  • Property mode set to 100644
File size: 20.1 KB
Line 
1/*  bsp.h
2 *
3 *  Following defines must reflect the setup of the particular MVME167.
4 *  All page references are to the MVME166/MVME167/MVME187 Single Board
5 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
6 *  1993 supplements/addenda (MVME187PG/D2A1).
7 *
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  Modifications of respective RTEMS file:
16 *  Copyright (c) 1998, National Research Council of Canada
17 *
18 *  $Id$
19 */
20
21#ifndef __MVME167_H
22#define __MVME167_H
23
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems.h>
30#include <clockdrv.h>
31#include <console.h>
32#include <iosupp.h>
33
34
35/*
36 *  confdefs.h overrides for this BSP:
37 *   - termios serial ports (defaults to 1)
38 *   - Interrupt stack space is not minimum if defined.
39 */
40
41#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4
42#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
43 
44/*
45 * Network driver configuration
46 */
47 
48struct rtems_bsdnet_ifconfig;
49int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
50#define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
51#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
52
53/*
54 *  This is NOT the base address of local RAM!
55 *  This is the base local address of the VMEbus short I/O space. A local
56 *  access to this space results in a A16 VMEbus I/O cycle. This base address
57 *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
58 *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
59 *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
60 *  GCSRs of other boards are accessible only through the VMEbus short I/O
61 *  space. See pages 2-45 and 2-7.
62 */
63#define BOARD_BASE_ADDRESS 0xFFFF0000
64
65
66/*
67 *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
68 *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
69 *  VMEbus short I/O space. It also should represent the group address of this
70 *  MVME167! The group address is configurable, and must match the address
71 *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
72 *  recommended by Motorola. It is arbitrary.
73 *  See pages 2-42 and 2-97 to 2-104.
74 */
75#define GROUP_BASE_ADDRESS 0x0000CC00
76
77
78/*
79 *  Representation of the GCSR
80 */
81typedef volatile struct gcsr_regs_ {
82  unsigned char     chip_revision;
83  unsigned char     chip_id;
84  unsigned char     lmsig;
85  unsigned char     board_scr;
86  unsigned short    gpr[6];
87} gcsr_regs;
88
89/* Address of GCSR in VMEbus space */
90#define gcsr_vme    ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
91
92/* Address of GCSR in local space */
93#define gcsr        ((gcsr_regs * const) 0xFFF40100)
94
95/*
96 *  Representation of the VMEchip2 LCSR.
97 *  Could be made more detailed.
98 */
99typedef volatile struct lcsr_regs_ {
100  unsigned long     slave_adr[2];       /* 0xFFF40000 */
101  unsigned long     slave_trn[2];       /* 0xFFF40008 */
102  unsigned long     slave_ctl;          /* 0xFFF40010 */
103  unsigned long     mastr_adr[4];       /* 0xFFF40014 */
104  unsigned long     mastr_trn;          /* 0xFFF40024 */
105  unsigned long     mastr_att;          /* 0xFFF40028 */
106  unsigned long     mastr_ctl;          /* 0xFFF4002C */
107  unsigned long     dma_ctl_1;          /* 0xFFF40030 */
108  unsigned long     dma_ctl_2;          /* 0xFFF40034 */
109  unsigned long     dma_loc_cnt;        /* 0xFFF40038 */
110  unsigned long     dma_vme_cnt;        /* 0xFFF4003C */
111  unsigned long     dma_byte_cnt;       /* 0xFFF40040 */
112  unsigned long     dma_adr_cnt;        /* 0xFFF40044 */
113  unsigned long     dma_status;         /* 0xFFF40048 */
114  unsigned long     to_ctl;             /* 0xFFF4004C */
115  unsigned long     timer_cmp_1;        /* 0xFFF40050 */
116  unsigned long     timer_cnt_1;        /* 0xFFF40054 */
117  unsigned long     timer_cmp_2;        /* 0xFFF40058 */
118  unsigned long     timer_cnt_2;        /* 0xFFF4005C */
119  unsigned long     board_ctl;          /* 0xFFF40060 */
120  unsigned long     prescaler_cnt;      /* 0xFFF40064 */
121  unsigned long     intr_stat;          /* 0xFFF40068 */
122  unsigned long     intr_ena;           /* 0xFFF4006C */
123  unsigned long     intr_soft_set;      /* 0xFFF40070 */
124  unsigned long     intr_clear;         /* 0xFFF40074 */
125  unsigned long     intr_level[4];      /* 0xFFF40078 */
126  unsigned long     vector_base;        /* 0xFFF40088 */
127} lcsr_regs;
128
129/*
130 *  Base address of VMEchip2 LCSR
131 *  Not configurable on the MVME167.
132 */
133#define lcsr        ((lcsr_regs * const) 0xFFF40000)
134
135/*
136 *  Vector numbers for the interrupts from the VMEchip2. Use the values
137 *  "recommended" by Motorola.
138 *  See pages 2-70 to 2-92, and table 2-3.
139 */
140
141/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
142#define MASK_INT    0x00800000
143
144/* The content of VBR0 corresponds to "X" in table 2-3 */
145#define VBR0        0x6
146
147/* The content of VBR1 corresponds to "Y" in table 2-3 */
148#define VBR1        0x7
149
150
151/*
152 *  Representation of the PCCchip2
153 */
154typedef volatile struct pccchip2_regs_ {
155  unsigned char     chip_id;            /* 0xFFF42000 */
156  unsigned char     chip_revision;      /* 0xFFF42001 */
157  unsigned char     gen_control;        /* 0xFFF42002 */
158  unsigned char     vector_base;        /* 0xFFF42003 */
159  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
160  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
161  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
162  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
163  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
164  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
165  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
166  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
167  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
168  unsigned char     gpio_ctl;           /* 0xFFF42019 */
169  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
170  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
171  unsigned char     SCC_error;          /* 0xFFF4201C */
172  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
173  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
174  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
175  unsigned char     reserved1[3];
176  unsigned char     modem_piack;        /* 0xFFF42023 */
177  unsigned char     reserved2;
178  unsigned char     tx_piack;           /* 0xFFF42025 */
179  unsigned char     reserved3;
180  unsigned char     rx_piack;           /* 0xFFF42027 */
181  unsigned char     LANC_error;         /* 0xFFF42028 */
182  unsigned char     reserved4;
183  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
184  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
185  unsigned char     SCSI_error;         /* 0xFFF4202C */
186  unsigned char     reserved5[2];
187  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
188  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
189  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
190  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
191  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
192  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
193  unsigned char     reserved6;
194  unsigned char     print_input_status; /* 0xFFF42036 */
195  unsigned char     print_ctl;          /* 0xFFF42037 */
196  unsigned char     chip_speed;         /* 0xFFF42038 */
197  unsigned char     reserved7;
198  unsigned char     print_data;         /* 0xFFF4203A */
199  unsigned char     reserved8[3];
200  unsigned char     int_level;          /* 0xFFF4203E */
201  unsigned char     int_mask;           /* 0xFFF4203F */
202} pccchip2_regs;
203
204/*
205 *  Base address of the PCCchip2.
206 *  This is not configurable in the MVME167.
207 */
208#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
209
210/*
211 * Vector numbers for the interrupts from the PCCchip2. Use the values
212 * "recommended" by Motorola.
213 * See page 3-15.
214 */
215#define PCCCHIP2_VBR    0x5
216
217
218/*
219 * The MVME167 is equiped with one or two MEMC040 memory controllers at
220 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
221 * were initialized by 167Bug.
222 */
223typedef volatile struct memc040_regs_ {
224  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
225  unsigned char     reserved1[3];
226  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
227  unsigned char     reserved2[3];
228  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
229  unsigned char     reserved3[3];
230  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
231  unsigned char     reserved4[3];
232  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
233  unsigned char     reserved5[3];
234  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
235  unsigned char     reserved6[3];
236  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
237  unsigned char     reserved7[3];
238  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
239} memc040_regs;
240
241/*
242 *  Base address of the MEMC040s.
243 *  This is not configurable in the MVME167.
244 */
245#define memc040_1   ((memc040_regs * const) 0xFFF43000)
246#define memc040_2   ((memc040_regs * const) 0xFFF43100)
247
248
249/*
250 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
251 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
252 *  assumes that these controllers, if present, are initialized by 167Bug.
253 *  They do not appear to hold information of interest at this time, so they
254 *  are not described. However, each MCECC pair lives at the same address as
255 *  the MEMC040 is replaces. The first eight registers of the MCECC are
256 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
257 *  can be used to read those first eight registers.
258 */
259 
260
261/*
262 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
263 */
264typedef volatile struct cd2401_regs_ {
265  unsigned char     reserved1[7];
266  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
267  unsigned char     reserved2;
268  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
269  unsigned char     reserved3[6];
270  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
271  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
272  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
273  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
274  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
275  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
276  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
277  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
278  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
279  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
280  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
281  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
282  union {
283    struct {
284      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
285      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
286      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
287      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
288    } async;
289    struct {
290      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
291      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
292      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
293      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
294    } sync;
295  } u1;   
296  unsigned char     reserved4[2];
297  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
298  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
299  union {
300    struct {
301      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
302    } w;
303    struct {
304      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
305      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
306    } b;
307  } u2;
308  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
309  unsigned char     reserved5[2];
310  union {
311    struct {
312      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
313    } async;
314    struct {
315      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
316    } sync;
317  } u3;
318  union {
319    struct {
320      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
321    } w;
322    struct {
323      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
324      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
325    } b;
326  } u4;
327  unsigned char     reserved6[2];
328  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
329  unsigned char     reserved7;
330  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
331  unsigned char     reserved8[7];
332  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
333  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
334  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
335  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
336  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
337  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
338  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
339  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
340  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
341  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
342  unsigned short    reserved9;
343  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
344  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
345  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
346  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
347  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
348  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
349  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
350  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
351  unsigned short    reserved10;
352  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
353  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
354  unsigned char     reserved11[32];
355  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
356  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
357  unsigned char     reserved12[2];
358  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
359  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
360  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
361  union {
362    struct {
363      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
364    } w;
365    struct {
366      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
367      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
368    } b;
369  } u5;   
370  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
371  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
372  unsigned char     reserved13[2];
373  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
374  unsigned char     reserved14[49];
375  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
376  unsigned char     reserved15[2];
377  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
378  unsigned char     reserved16[4];
379  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
380  unsigned char     reserved17[2];
381  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
382  unsigned char     reserved18[10];
383  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
384  unsigned char     reserved19[3];
385  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
386  unsigned char     reserved20[3];
387  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
388  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
389  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
390  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
391  unsigned char     stk;            /* 0xFFF450E2 - Stack */
392  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
393  unsigned char     reserved21[8];
394  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
395  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
396  unsigned char     car;            /* 0xFFF450EE - Channel Access */
397  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
398  unsigned char     reserved22[6];
399  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
400  unsigned char     reserved23;
401  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
402} cd2401_regs;
403
404
405/*
406 *  Base address of the CD2401.
407 *  This is not configurable in the MVME167.
408 */
409#define cd2401          ((cd2401_regs * const) 0xFFF45000)
410
411
412/* CD2401 is clocked at 20 MHz */
413#define CD2401_CLK_RATE 20000000
414
415/*
416 *  Debug print functions: implemented in console.c
417 */
418void printk( char *fmt, ... );
419void BSP_output_string( char * buf );
420
421/*
422 *  Representation of 82596CA LAN controller: Memory Map
423 */
424typedef volatile struct i82596_regs_ {
425  unsigned short        port_lower;             /* 0xFFF46000 */
426  unsigned short        port_upper;             /* 0xFFF46002 */
427  unsigned long         chan_attn;              /* 0xFFF46004 */
428} i82596_regs;
429
430/*
431 *  Base address of the 82596.
432 */
433#define i82596    ((i82596_regs * const) 0xFFF46000)
434
435/*
436 *  Representation of initialization data in NVRAM
437 */
438typedef volatile struct nvram_config_ {
439  unsigned char  dcache_enable;                         /* 0xFFFC0000 */
440  unsigned char  icache_enable;                         /* 0xFFFC0001 */
441  unsigned short cache_mode;                            /* 0xFFFC0002 */
442  unsigned long  ipaddr;                                        /* 0xFFFC0004 */
443  unsigned long  netmask;                                       /* 0xFFFC0008 */
444  unsigned char  enaddr[6];                                     /* 0xFFFC000C */
445  unsigned short processor_id;                          /* 0xFFFC0012 */
446  unsigned long  rma_start;                                     /* 0xFFFC0014 */
447  unsigned long  vma_start;                                     /* 0xFFFC0018 */
448  unsigned long  ramsize;                                       /* 0xFFFC001C */
449} nvram_config;
450
451/*
452 *  Pointer to the base of User Area NVRAM
453 */
454#define nvram                   ((nvram_config * const) 0xFFFC0000)
455
456
457/* BSP-wide functions */
458
459void bsp_cleanup( void );
460
461m68k_isr_entry set_vector(
462  rtems_isr_entry     handler,
463  rtems_vector_number vector,
464  int                 type
465);
466
467#ifdef M167_INIT
468#undef EXTERN
469#define EXTERN
470#else
471#undef EXTERN
472#define EXTERN extern
473#endif
474
475/*
476 *  Device Driver Table Entries
477 */
478
479/*
480 * NOTE: Use the standard Console driver entry
481 */
482 
483/*
484 * NOTE: Use the standard Clock driver entry
485 */
486
487/*
488 * How many libio files we want
489 */
490
491#define BSP_LIBIO_MAX_FDS       20
492
493
494/* miscellaneous stuff assumed to exist */
495
496extern rtems_configuration_table BSP_Configuration;
497
498extern m68k_isr_entry M68Kvec[];   /* vector table address */
499
500
501/*
502 *  Define the time limits for RTEMS Test Suite test durations.
503 *  Long test and short test duration limits are provided.  These
504 *  values are in seconds and need to be converted to ticks for the
505 *  application.
506 *
507 */
508
509#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
510#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
511
512/*
513 *  Define the interrupt mechanism for Time Test 27
514 *
515 *  NOTE: We use software interrupt 0
516 */
517#define MUST_WAIT_FOR_INTERRUPT 0
518
519#define Install_tm27_vector( handler ) \
520            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
521            lcsr->intr_level[2] |= 3; \
522            lcsr->intr_ena |= 0x100
523
524#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100
525
526#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100
527
528#define Lower_tm27_intr()
529
530#ifdef __cplusplus
531}
532#endif
533
534#endif
535/* end of include file */
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