source: rtems/c/src/lib/libbsp/m68k/mvme167/include/bsp.h @ bb734cc

Last change on this file since bb734cc was bb734cc, checked in by Joel Sherrill <joel.sherrill@…>, on 04/05/00 at 18:24:48

Patch from Charles-Antoine Gauthier <charles.gauthier@…>
to update the mvme167 BSP and account for the fact that RAM base
does not have to start at 0.
  • Property mode set to 100644
File size: 19.2 KB
Line 
1/*  bsp.h
2 *
3 *  Following defines must reflect the setup of the particular MVME167.
4 *  All page references are to the MVME166/MVME167/MVME187 Single Board
5 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
6 *  1993 supplements/addenda (MVME187PG/D2A1).
7 *
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  Modifications of respective RTEMS file:
16 *  Copyright (c) 1998, National Research Council of Canada
17 *
18 *  $Id$
19 */
20
21#ifndef __MVME167_H
22#define __MVME167_H
23
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems.h>
30#include <clockdrv.h>
31#include <console.h>
32#include <iosupp.h>
33
34
35/*
36 * Network driver configuration
37 */
38 
39struct rtems_bsdnet_ifconfig;
40extern int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig );
41#define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
42#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
43
44/*
45 *  This is NOT the base address of local RAM!
46 *  This is the base local address of the VMEbus short I/O space. A local
47 *  access to this space results in a A16 VMEbus I/O cycle. This base address
48 *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
49 *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
50 *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
51 *  GCSRs of other boards are accessible only through the VMEbus short I/O
52 *  space. See pages 2-45 and 2-7.
53 */
54#define BOARD_BASE_ADDRESS 0xFFFF0000
55
56
57/*
58 *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
59 *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
60 *  VMEbus short I/O space. It also should represent the group address of this
61 *  MVME167! The group address is configurable, and must match the address
62 *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
63 *  recommended by Motorola. It is arbitrary.
64 *  See pages 2-42 and 2-97 to 2-104.
65 */
66#define GROUP_BASE_ADDRESS 0x0000CC00
67
68
69/*
70 *  Representation of the GCSR
71 */
72typedef volatile struct gcsr_regs_ {
73  unsigned char     chip_revision;
74  unsigned char     chip_id;
75  unsigned char     lmsig;
76  unsigned char     board_scr;
77  unsigned short    gpr[6];
78} gcsr_regs;
79
80/* Address of GCSR in VMEbus space */
81#define gcsr_vme    ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
82
83/* Address of GCSR in local space */
84#define gcsr        ((gcsr_regs * const) 0xFFF40100)
85
86/*
87 *  Representation of the VMEchip2 LCSR.
88 *  Could be made more detailed.
89 */
90typedef volatile struct lcsr_regs_ {
91  unsigned long     slave_adr[2];       /* 0xFFF40000 */
92  unsigned long     slave_trn[2];       /* 0xFFF40008 */
93  unsigned long     slave_ctl;          /* 0xFFF40010 */
94  unsigned long     mastr_adr[4];       /* 0xFFF40014 */
95  unsigned long     mastr_trn;          /* 0xFFF40024 */
96  unsigned long     mastr_att;          /* 0xFFF40028 */
97  unsigned long     mastr_ctl;          /* 0xFFF4002C */
98  unsigned long     dma_ctl_1;          /* 0xFFF40030 */
99  unsigned long     dma_ctl_2;          /* 0xFFF40034 */
100  unsigned long     dma_loc_cnt;        /* 0xFFF40038 */
101  unsigned long     dma_vme_cnt;        /* 0xFFF4003C */
102  unsigned long     dma_byte_cnt;       /* 0xFFF40040 */
103  unsigned long     dma_adr_cnt;        /* 0xFFF40044 */
104  unsigned long     dma_status;         /* 0xFFF40048 */
105  unsigned long     to_ctl;             /* 0xFFF4004C */
106  unsigned long     timer_cmp_1;        /* 0xFFF40050 */
107  unsigned long     timer_cnt_1;        /* 0xFFF40054 */
108  unsigned long     timer_cmp_2;        /* 0xFFF40058 */
109  unsigned long     timer_cnt_2;        /* 0xFFF4005C */
110  unsigned long     board_ctl;          /* 0xFFF40060 */
111  unsigned long     prescaler_cnt;      /* 0xFFF40064 */
112  unsigned long     intr_stat;          /* 0xFFF40068 */
113  unsigned long     intr_ena;           /* 0xFFF4006C */
114  unsigned long     intr_soft_set;      /* 0xFFF40070 */
115  unsigned long     intr_clear;         /* 0xFFF40074 */
116  unsigned long     intr_level[4];      /* 0xFFF40078 */
117  unsigned long     vector_base;        /* 0xFFF40088 */
118} lcsr_regs;
119
120/*
121 *  Base address of VMEchip2 LCSR
122 *  Not configurable on the MVME167.
123 */
124#define lcsr        ((lcsr_regs * const) 0xFFF40000)
125
126/*
127 *  Vector numbers for the interrupts from the VMEchip2. Use the values
128 *  "recommended" by Motorola.
129 *  See pages 2-70 to 2-92, and table 2-3.
130 */
131
132/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
133#define MASK_INT    0x00800000
134
135/* The content of VBR0 corresponds to "X" in table 2-3 */
136#define VBR0        0x6
137
138/* The content of VBR1 corresponds to "Y" in table 2-3 */
139#define VBR1        0x7
140
141
142/*
143 *  Representation of the PCCchip2
144 */
145typedef volatile struct pccchip2_regs_ {
146  unsigned char     chip_id;            /* 0xFFF42000 */
147  unsigned char     chip_revision;      /* 0xFFF42001 */
148  unsigned char     gen_control;        /* 0xFFF42002 */
149  unsigned char     vector_base;        /* 0xFFF42003 */
150  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
151  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
152  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
153  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
154  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
155  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
156  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
157  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
158  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
159  unsigned char     gpio_ctl;           /* 0xFFF42019 */
160  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
161  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
162  unsigned char     SCC_error;          /* 0xFFF4201C */
163  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
164  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
165  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
166  unsigned char     reserved1[3];
167  unsigned char     modem_piack;        /* 0xFFF42023 */
168  unsigned char     reserved2;
169  unsigned char     tx_piack;           /* 0xFFF42025 */
170  unsigned char     reserved3;
171  unsigned char     rx_piack;           /* 0xFFF42027 */
172  unsigned char     LANC_error;         /* 0xFFF42028 */
173  unsigned char     reserved4;
174  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
175  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
176  unsigned char     SCSI_error;         /* 0xFFF4202C */
177  unsigned char     reserved5[2];
178  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
179  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
180  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
181  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
182  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
183  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
184  unsigned char     reserved6;
185  unsigned char     print_input_status; /* 0xFFF42036 */
186  unsigned char     print_ctl;          /* 0xFFF42037 */
187  unsigned char     chip_speed;         /* 0xFFF42038 */
188  unsigned char     reserved7;
189  unsigned char     print_data;         /* 0xFFF4203A */
190  unsigned char     reserved8[3];
191  unsigned char     int_level;          /* 0xFFF4203E */
192  unsigned char     int_mask;           /* 0xFFF4203F */
193} pccchip2_regs;
194
195/*
196 *  Base address of the PCCchip2.
197 *  This is not configurable in the MVME167.
198 */
199#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
200
201/*
202 * Vector numbers for the interrupts from the PCCchip2. Use the values
203 * "recommended" by Motorola.
204 * See page 3-15.
205 */
206#define PCCCHIP2_VBR    0x5
207
208
209/*
210 * The MVME167 is equiped with one or two MEMC040 memory controllers at
211 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
212 * were initialized by 167Bug.
213 */
214typedef volatile struct memc040_regs_ {
215  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
216  unsigned char     reserved1[3];
217  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
218  unsigned char     reserved2[3];
219  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
220  unsigned char     reserved3[3];
221  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
222  unsigned char     reserved4[3];
223  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
224  unsigned char     reserved5[3];
225  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
226  unsigned char     reserved6[3];
227  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
228  unsigned char     reserved7[3];
229  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
230} memc040_regs;
231
232/*
233 *  Base address of the MEMC040s.
234 *  This is not configurable in the MVME167.
235 */
236#define memc040_1   ((memc040_regs * const) 0xFFF43000)
237#define memc040_2   ((memc040_regs * const) 0xFFF43100)
238
239
240/*
241 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
242 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
243 *  assumes that these controllers, if present, are initialized by 167Bug.
244 *  They do not appear to hold information of interest at this time, so they
245 *  are not described. However, each MCECC pair lives at the same address as
246 *  the MEMC040 is replaces. The first eight registers of the MCECC are
247 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
248 *  can be used to read those first eight registers.
249 */
250 
251
252/*
253 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
254 */
255typedef volatile struct cd2401_regs_ {
256  unsigned char     reserved1[7];
257  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
258  unsigned char     reserved2;
259  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
260  unsigned char     reserved3[6];
261  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
262  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
263  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
264  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
265  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
266  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
267  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
268  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
269  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
270  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
271  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
272  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
273  union {
274    struct {
275      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
276      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
277      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
278      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
279    } async;
280    struct {
281      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
282      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
283      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
284      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
285    } sync;
286  } u1;   
287  unsigned char     reserved4[2];
288  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
289  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
290  union {
291    struct {
292      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
293    } w;
294    struct {
295      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
296      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
297    } b;
298  } u2;
299  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
300  unsigned char     reserved5[2];
301  union {
302    struct {
303      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
304    } async;
305    struct {
306      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
307    } sync;
308  } u3;
309  union {
310    struct {
311      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
312    } w;
313    struct {
314      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
315      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
316    } b;
317  } u4;
318  unsigned char     reserved6[2];
319  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
320  unsigned char     reserved7;
321  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
322  unsigned char     reserved8[7];
323  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
324  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
325  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
326  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
327  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
328  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
329  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
330  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
331  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
332  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
333  unsigned short    reserved9;
334  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
335  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
336  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
337  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
338  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
339  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
340  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
341  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
342  unsigned short    reserved10;
343  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
344  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
345  unsigned char     reserved11[32];
346  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
347  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
348  unsigned char     reserved12[2];
349  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
350  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
351  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
352  union {
353    struct {
354      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
355    } w;
356    struct {
357      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
358      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
359    } b;
360  } u5;   
361  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
362  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
363  unsigned char     reserved13[2];
364  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
365  unsigned char     reserved14[49];
366  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
367  unsigned char     reserved15[2];
368  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
369  unsigned char     reserved16[4];
370  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
371  unsigned char     reserved17[2];
372  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
373  unsigned char     reserved18[10];
374  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
375  unsigned char     reserved19[3];
376  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
377  unsigned char     reserved20[3];
378  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
379  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
380  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
381  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
382  unsigned char     stk;            /* 0xFFF450E2 - Stack */
383  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
384  unsigned char     reserved21[8];
385  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
386  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
387  unsigned char     car;            /* 0xFFF450EE - Channel Access */
388  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
389  unsigned char     reserved22[6];
390  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
391  unsigned char     reserved23;
392  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
393} cd2401_regs;
394
395
396/*
397 *  Base address of the CD2401.
398 *  This is not configurable in the MVME167.
399 */
400#define cd2401          ((cd2401_regs * const) 0xFFF45000)
401
402
403/* CD2401 is clocked at 20 MHz */
404#define CD2401_CLK_RATE 20000000
405
406void console_reserve_resources( rtems_configuration_table *configuration );
407
408/*
409 *  Debug print functions: implemented in console.c
410 */
411void printk( char *fmt, ... );
412void BSP_output_string( char * buf );
413
414/*
415 *  Representation of 82596CA LAN controller: Memory Map
416 */
417typedef volatile struct i82596_regs_ {
418  unsigned short        port_lower;                               /* 0xFFF46000 */
419  unsigned short        port_upper;                     /* 0xFFF46002 */
420  unsigned long         chan_attn;                                /* 0xFFF46004 */
421} i82596_regs;
422
423/*
424 *  Base address of the 82596.
425 */
426#define i82596    ((i82596_regs * const) 0xFFF46000)
427
428
429
430/* BSP-wide functions */
431
432void bsp_cleanup( void );
433
434m68k_isr_entry set_vector(
435  rtems_isr_entry     handler,
436  rtems_vector_number vector,
437  int                 type
438);
439
440#ifdef M167_INIT
441#undef EXTERN
442#define EXTERN
443#else
444#undef EXTERN
445#define EXTERN extern
446#endif
447
448/*
449 *  Device Driver Table Entries
450 */
451
452/*
453 * NOTE: Use the standard Console driver entry
454 */
455 
456/*
457 * NOTE: Use the standard Clock driver entry
458 */
459
460/*
461 * How many libio files we want
462 */
463
464#define BSP_LIBIO_MAX_FDS       20
465
466
467/* miscellaneous stuff assumed to exist */
468
469extern rtems_configuration_table BSP_Configuration;
470
471extern m68k_isr_entry M68Kvec[];   /* vector table address */
472
473
474/*
475 *  Define the time limits for RTEMS Test Suite test durations.
476 *  Long test and short test duration limits are provided.  These
477 *  values are in seconds and need to be converted to ticks for the
478 *  application.
479 *
480 */
481
482#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
483#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
484
485/*
486 *  Define the interrupt mechanism for Time Test 27
487 *
488 *  NOTE: We use software interrupt 0
489 */
490#define MUST_WAIT_FOR_INTERRUPT 0
491
492#define Install_tm27_vector( handler ) \
493            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
494            lcsr->intr_level[2] |= 3; \
495            lcsr->intr_ena |= 0x100
496
497#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100
498
499#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100
500
501#define Lower_tm27_intr()
502
503#ifdef __cplusplus
504}
505#endif
506
507#endif
508/* end of include file */
Note: See TracBrowser for help on using the repository browser.