source: rtems/c/src/lib/libbsp/m68k/mvme167/include/bsp.h @ 6d27f69

Last change on this file since 6d27f69 was 6d27f69, checked in by Joel Sherrill <joel@…>, on Mar 30, 2016 at 7:04:23 PM

m68k/mvme167/include/bsp.h: Do not include <rtems/iosupp.h>

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1/**
2 *  @file
3 *
4 *  Following defines must reflect the setup of the particular MVME167.
5 *  All page references are to the MVME166/MVME167/MVME187 Single Board
6 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
7 *  1993 supplements/addenda (MVME187PG/D2A1).
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2012.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 *
18 *  Modifications of respective RTEMS file:
19 *  Copyright (c) 1998, National Research Council of Canada
20 */
21
22#ifndef LIBBSP_M68K_MVME167_BSP_H
23#define LIBBSP_M68K_MVME167_BSP_H
24
25#include <bspopts.h>
26#include <bsp/default-initial-extension.h>
27
28#include <rtems.h>
29#include <rtems/bspIo.h>
30
31#include <mvme16x_hw.h>
32
33#ifdef __cplusplus
34extern "C" {
35#endif
36
37/* GCSR is in mvme16x_hw.h */
38/* LCSR is in mvme16x_hw.h */
39/* i82596 is in mvme16x_hw.h */
40/* NVRAM is in mvme16x_hw.h */
41
42#if 0
43/*
44 *  Representation of the PCCchip2
45 */
46typedef volatile struct pccchip2_regs_ {
47  unsigned char     chip_id;            /* 0xFFF42000 */
48  unsigned char     chip_revision;      /* 0xFFF42001 */
49  unsigned char     gen_control;        /* 0xFFF42002 */
50  unsigned char     vector_base;        /* 0xFFF42003 */
51  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
52  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
53  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
54  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
55  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
56  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
57  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
58  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
59  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
60  unsigned char     gpio_ctl;           /* 0xFFF42019 */
61  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
62  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
63  unsigned char     SCC_error;          /* 0xFFF4201C */
64  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
65  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
66  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
67  unsigned char     reserved1[3];
68  unsigned char     modem_piack;        /* 0xFFF42023 */
69  unsigned char     reserved2;
70  unsigned char     tx_piack;           /* 0xFFF42025 */
71  unsigned char     reserved3;
72  unsigned char     rx_piack;           /* 0xFFF42027 */
73  unsigned char     LANC_error;         /* 0xFFF42028 */
74  unsigned char     reserved4;
75  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
76  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
77  unsigned char     SCSI_error;         /* 0xFFF4202C */
78  unsigned char     reserved5[2];
79  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
80  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
81  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
82  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
83  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
84  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
85  unsigned char     reserved6;
86  unsigned char     print_input_status; /* 0xFFF42036 */
87  unsigned char     print_ctl;          /* 0xFFF42037 */
88  unsigned char     chip_speed;         /* 0xFFF42038 */
89  unsigned char     reserved7;
90  unsigned char     print_data;         /* 0xFFF4203A */
91  unsigned char     reserved8[3];
92  unsigned char     int_level;          /* 0xFFF4203E */
93  unsigned char     int_mask;           /* 0xFFF4203F */
94} pccchip2_regs;
95
96/*
97 *  Base address of the PCCchip2.
98 *  This is not configurable in the MVME167.
99 */
100#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
101
102#endif
103/*
104 * The MVME167 is equiped with one or two MEMC040 memory controllers at
105 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
106 * were initialized by 167Bug.
107 */
108typedef volatile struct memc040_regs_ {
109  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
110  unsigned char     reserved1[3];
111  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
112  unsigned char     reserved2[3];
113  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
114  unsigned char     reserved3[3];
115  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
116  unsigned char     reserved4[3];
117  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
118  unsigned char     reserved5[3];
119  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
120  unsigned char     reserved6[3];
121  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
122  unsigned char     reserved7[3];
123  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
124} memc040_regs;
125
126/*
127 *  Base address of the MEMC040s.
128 *  This is not configurable in the MVME167.
129 */
130#define memc040_1   ((memc040_regs * const) 0xFFF43000)
131#define memc040_2   ((memc040_regs * const) 0xFFF43100)
132
133/*
134 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
135 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
136 *  assumes that these controllers, if present, are initialized by 167Bug.
137 *  They do not appear to hold information of interest at this time, so they
138 *  are not described. However, each MCECC pair lives at the same address as
139 *  the MEMC040 is replaces. The first eight registers of the MCECC are
140 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
141 *  can be used to read those first eight registers.
142 */
143
144/*
145 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
146 */
147typedef volatile struct cd2401_regs_ {
148  unsigned char     reserved1[7];
149  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
150  unsigned char     reserved2;
151  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
152  unsigned char     reserved3[6];
153  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
154  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
155  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
156  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
157  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
158  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
159  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
160  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
161  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
162  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
163  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
164  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
165  union {
166    struct {
167      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
168      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
169      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
170      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
171    } async;
172    struct {
173      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
174      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
175      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
176      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
177    } sync;
178  } u1;
179  unsigned char     reserved4[2];
180  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
181  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
182  union {
183    struct {
184      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
185    } w;
186    struct {
187      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
188      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
189    } b;
190  } u2;
191  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
192  unsigned char     reserved5[2];
193  union {
194    struct {
195      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
196    } async;
197    struct {
198      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
199    } sync;
200  } u3;
201  union {
202    struct {
203      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
204    } w;
205    struct {
206      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
207      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
208    } b;
209  } u4;
210  unsigned char     reserved6[2];
211  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
212  unsigned char     reserved7;
213  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
214  unsigned char     reserved8[7];
215  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
216  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
217  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
218  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
219  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
220  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
221  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
222  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
223  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
224  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
225  unsigned short    reserved9;
226  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
227  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
228  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
229  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
230  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
231  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
232  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
233  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
234  unsigned short    reserved10;
235  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
236  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
237  unsigned char     reserved11[32];
238  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
239  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
240  unsigned char     reserved12[2];
241  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
242  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
243  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
244  union {
245    struct {
246      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
247    } w;
248    struct {
249      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
250      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
251    } b;
252  } u5;
253  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
254  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
255  unsigned char     reserved13[2];
256  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
257  unsigned char     reserved14[49];
258  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
259  unsigned char     reserved15[2];
260  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
261  unsigned char     reserved16[4];
262  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
263  unsigned char     reserved17[2];
264  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
265  unsigned char     reserved18[10];
266  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
267  unsigned char     reserved19[3];
268  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
269  unsigned char     reserved20[3];
270  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
271  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
272  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
273  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
274  unsigned char     stk;            /* 0xFFF450E2 - Stack */
275  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
276  unsigned char     reserved21[8];
277  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
278  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
279  unsigned char     car;            /* 0xFFF450EE - Channel Access */
280  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
281  unsigned char     reserved22[6];
282  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
283  unsigned char     reserved23;
284  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
285} cd2401_regs;
286
287/*
288 *  Base address of the CD2401.
289 *  This is not configurable in the MVME167.
290 */
291#define cd2401          ((cd2401_regs * const) 0xFFF45000)
292
293/* CD2401 is clocked at 20 MHz */
294#define CD2401_CLK_RATE 20000000
295
296/* BSP-wide functions */
297
298rtems_isr_entry set_vector(
299  rtems_isr_entry     handler,
300  rtems_vector_number vector,
301  int                 type
302);
303
304#ifdef M167_INIT
305#undef EXTERN
306#define EXTERN
307#else
308#undef EXTERN
309#define EXTERN extern
310#endif
311
312extern void *M68Kvec[];   /* vector table address */
313
314#ifdef __cplusplus
315}
316#endif
317
318#endif
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