source: rtems/c/src/lib/libbsp/m68k/mvme167/include/bsp.h @ 57b1f53

4.104.114.84.95
Last change on this file since 57b1f53 was 57b1f53, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 11, 2000 at 7:29:54 PM

2000-08-11 Charles-Antoine Gauthier <charles.gauthier@…>

  • README: Updated
  • console/console.c: Fix polled input. Add support for shared printk. Add support for more flexible polled I/O with and without termios. I/O mode and console is selectable either from NVRAM or from mvme167.cfg. Clean up comments.
  • Property mode set to 100644
File size: 15.0 KB
Line 
1/*  bsp.h
2 *
3 *  Following defines must reflect the setup of the particular MVME167.
4 *  All page references are to the MVME166/MVME167/MVME187 Single Board
5 *  Computer Programmer's Reference Guide (MVME187PG/D2) with the April
6 *  1993 supplements/addenda (MVME187PG/D2A1).
7 *
8 *  COPYRIGHT (c) 1989-1999.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.OARcorp.com/rtems/license.html.
14 *
15 *  Modifications of respective RTEMS file:
16 *  Copyright (c) 1998, National Research Council of Canada
17 *
18 *  $Id$
19 */
20
21#ifndef __MVME167_H
22#define __MVME167_H
23
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <rtems.h>
30#include <clockdrv.h>
31#include <console.h>
32#include <iosupp.h>
33#include <bspIo.h>
34
35
36/*
37 *  confdefs.h overrides for this BSP:
38 *   - termios serial ports (defaults to 1)
39 *   - Interrupt stack space is not minimum if defined.
40 */
41
42#define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 4
43#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
44 
45#include <mvme16x_hw.h>
46
47/* GCSR is in mvme16x_hw.h */
48/* LCSR is in mvme16x_hw.h */
49/* i82596 is in mvme16x_hw.h */
50/* NVRAM is in mvme16x_hw.h */
51
52#if 0
53/*
54 *  Representation of the PCCchip2
55 */
56typedef volatile struct pccchip2_regs_ {
57  unsigned char     chip_id;            /* 0xFFF42000 */
58  unsigned char     chip_revision;      /* 0xFFF42001 */
59  unsigned char     gen_control;        /* 0xFFF42002 */
60  unsigned char     vector_base;        /* 0xFFF42003 */
61  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
62  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
63  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
64  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
65  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
66  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
67  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
68  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
69  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
70  unsigned char     gpio_ctl;           /* 0xFFF42019 */
71  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
72  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
73  unsigned char     SCC_error;          /* 0xFFF4201C */
74  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
75  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
76  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
77  unsigned char     reserved1[3];
78  unsigned char     modem_piack;        /* 0xFFF42023 */
79  unsigned char     reserved2;
80  unsigned char     tx_piack;           /* 0xFFF42025 */
81  unsigned char     reserved3;
82  unsigned char     rx_piack;           /* 0xFFF42027 */
83  unsigned char     LANC_error;         /* 0xFFF42028 */
84  unsigned char     reserved4;
85  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
86  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
87  unsigned char     SCSI_error;         /* 0xFFF4202C */
88  unsigned char     reserved5[2];
89  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
90  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
91  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
92  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
93  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
94  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
95  unsigned char     reserved6;
96  unsigned char     print_input_status; /* 0xFFF42036 */
97  unsigned char     print_ctl;          /* 0xFFF42037 */
98  unsigned char     chip_speed;         /* 0xFFF42038 */
99  unsigned char     reserved7;
100  unsigned char     print_data;         /* 0xFFF4203A */
101  unsigned char     reserved8[3];
102  unsigned char     int_level;          /* 0xFFF4203E */
103  unsigned char     int_mask;           /* 0xFFF4203F */
104} pccchip2_regs;
105
106/*
107 *  Base address of the PCCchip2.
108 *  This is not configurable in the MVME167.
109 */
110#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
111
112#endif
113/*
114 * The MVME167 is equiped with one or two MEMC040 memory controllers at
115 * 0xFFF43000 and 0xFFF43100. This port assumes that the controllers
116 * were initialized by 167Bug.
117 */
118typedef volatile struct memc040_regs_ {
119  unsigned char     chip_id;            /* 0xFFF43000/0xFFF43100 */
120  unsigned char     reserved1[3];
121  unsigned char     chip_revision;      /* 0xFFF43004/0xFFF43104 */
122  unsigned char     reserved2[3];
123  unsigned char     mem_config;         /* 0xFFF43008/0xFFF43108 */
124  unsigned char     reserved3[3];
125  unsigned char     alt_status;         /* 0xFFF4300C/0xFFF4310C */
126  unsigned char     reserved4[3];
127  unsigned char     alt_ctl;            /* 0xFFF43010/0xFFF43110 */
128  unsigned char     reserved5[3];
129  unsigned char     base_addr;          /* 0xFFF43014/0xFFF43114 */
130  unsigned char     reserved6[3];
131  unsigned char     ram_ctl;            /* 0xFFF43018/0xFFF43118 */
132  unsigned char     reserved7[3];
133  unsigned char     bus_clk;            /* 0xFFF4301C/0xFFF4311C */
134} memc040_regs;
135
136/*
137 *  Base address of the MEMC040s.
138 *  This is not configurable in the MVME167.
139 */
140#define memc040_1   ((memc040_regs * const) 0xFFF43000)
141#define memc040_2   ((memc040_regs * const) 0xFFF43100)
142
143
144/*
145 *  The MVME167 may be equiped with error-correcting RAM cards. In this case,
146 *  each MEMC040 is replaced by two MCECC ECC DRAM controllers. This port
147 *  assumes that these controllers, if present, are initialized by 167Bug.
148 *  They do not appear to hold information of interest at this time, so they
149 *  are not described. However, each MCECC pair lives at the same address as
150 *  the MEMC040 is replaces. The first eight registers of the MCECC are
151 *  nearly identical to the ones of the MEMC040, and the memc040_X structures
152 *  can be used to read those first eight registers.
153 */
154 
155
156/*
157 *  Representation of the Cirrus Logic CL-CD2401 Multi-Protocol Controller
158 */
159typedef volatile struct cd2401_regs_ {
160  unsigned char     reserved1[7];
161  unsigned char     cor7;           /* 0xFFF45007 - Channel Option 7 */
162  unsigned char     reserved2;
163  unsigned char     livr;           /* 0xFFF45009 - Local Interrupt Vector */
164  unsigned char     reserved3[6];
165  unsigned char     cor1;           /* 0xFFF45010 - Channel Option 1 */
166  unsigned char     ier;            /* 0xFFF45011 - Interrupt Enable */
167  unsigned char     stcr;           /* 0xFFF45012 - Special Transmit Command */
168  unsigned char     ccr;            /* 0xFFF45013 - Channel Command */
169  unsigned char     cor5;           /* 0xFFF45014 - Channel Option 5 */
170  unsigned char     cor4;           /* 0xFFF45015 - Channel Option 4 */
171  unsigned char     cor3;           /* 0xFFF45016 - Channel Option 3 */
172  unsigned char     cor2;           /* 0xFFF45017 - Channel Option 2 */
173  unsigned char     cor6;           /* 0xFFF45018 - Channel Option 6 */
174  unsigned char     dmabsts;        /* 0xFFF45019 - DMA Buffer Status */
175  unsigned char     csr;            /* 0xFFF4501A - Channel Status */
176  unsigned char     cmr;            /* 0xFFF4501B - Channel Mode */
177  union {
178    struct {
179      unsigned char schr4;          /* 0xFFF4501C - Special Character 4 */
180      unsigned char schr3;          /* 0xFFF4501D - Special Character 3 */
181      unsigned char schr2;          /* 0xFFF4501E - Special Character 2 */
182      unsigned char schr1;          /* 0xFFF4501F - Special Character 1 */
183    } async;
184    struct {
185      unsigned char rfar4;          /* 0xFFF4501C - Receive Frame Address 4 */
186      unsigned char rfar3;          /* 0xFFF4501D - Receive Frame Address 3 */
187      unsigned char rfar2;          /* 0xFFF4501E - Receive Frame Address 2 */
188      unsigned char rfar1;          /* 0xFFF4501F - Receive Frame Address 1 */
189    } sync;
190  } u1;   
191  unsigned char     reserved4[2];
192  unsigned char     scrh;           /* 0xFFF45022 - Special Character Range High */
193  unsigned char     scrl;           /* 0xFFF45023 - Special Character Range Low */
194  union {
195    struct {
196      unsigned short rtpr;          /* 0xFFF45024 - Receive Timeout Period */
197    } w;
198    struct {
199      unsigned char rtprh;          /* 0xFFF45024 - Receive Timeout Period High */
200      unsigned char rtprl;          /* 0xFFF45025 - Receive Timeout Period Low */
201    } b;
202  } u2;
203  unsigned char     licr;           /* 0xFFF45026 - Local Interrupt Channel */
204  unsigned char     reserved5[2];
205  union {
206    struct {
207      unsigned char ttr;            /* 0xFFF45029 - Transmit Timer */
208    } async;
209    struct {
210      unsigned char gt2;            /* 0xFFF45029 - General Timer 2 */
211    } sync;
212  } u3;
213  union {
214    struct {
215      unsigned short gt1;           /* 0xFFF4502A - General Timer 1 */
216    } w;
217    struct {
218      unsigned char gt1h;           /* 0xFFF4502A - General Timer 2 High */
219      unsigned char gt1l;           /* 0xFFF4502B - General Timer 1 Low */
220    } b;
221  } u4;
222  unsigned char     reserved6[2];
223  unsigned char     lnxt;           /* 0xFF4502E - LNext Character */
224  unsigned char     reserved7;
225  unsigned char     rfoc;           /* 0xFFF45030 - Receive FIFO Output Count */
226  unsigned char     reserved8[7];
227  unsigned short    tcbadru;        /* 0xFF45038 - Transmit Current Buffer Address Upper */
228  unsigned short    tcbadrl;        /* 0xFF4503A - Transmit Current Buffer Address Lower */
229  unsigned short    rcbadru;        /* 0xFF4503C - Receive Current Buffer Address Upper */
230  unsigned short    rcbadrl;        /* 0xFF4503E - Receive Current Buffer Address Lower */
231  unsigned short    arbadru;        /* 0xFF45040 - A Receive Buffer Address Upper */
232  unsigned short    arbardl;        /* 0xFF45042 - A Receive Buffer Address Lower */
233  unsigned short    brbadru;        /* 0xFF45044 - B Receive Buffer Address Upper */
234  unsigned short    brbadrl;        /* 0xFF45046 - B Receive Buffer Address Lower */
235  unsigned short    brbcnt;         /* 0xFF45048 - B Receive Buffer Byte Count */
236  unsigned short    arbcnt;         /* 0xFF4504A - A Receive Buffer Byte Count */
237  unsigned short    reserved9;
238  unsigned char     brbsts;         /* 0xFF4504E - B Receive Buffer Status */
239  unsigned char     arbsts;         /* 0xFF4504F - A Receive Buffer Status */
240  unsigned short    atbadru;        /* 0xFF45050 - A Transmit Buffer Address Upper */
241  unsigned short    atbadrl;        /* 0xFF45052 - A Transmit Buffer Address Lower */
242  unsigned short    btbadru;        /* 0xFF45054 - B Transmit Buffer Address Upper */
243  unsigned short    btbadrl;        /* 0xFF45056 - B Transmit Buffer Address Lower */
244  unsigned short    btbcnt;         /* 0xFF45058 - B Transmit Buffer Byte Count */
245  unsigned short    atbcnt;         /* 0xFF4505A - A Transmit Buffer Byte Count */
246  unsigned short    reserved10;
247  unsigned char     btbsts;         /* 0xFF4505E - B Transmit Buffer Status */
248  unsigned char     atbsts;         /* 0xFF4505F - A Transmit Buffer Status */
249  unsigned char     reserved11[32];
250  unsigned char     tftc;           /* 0xFFF45080 - Transmit FIFO Transfer Count */
251  unsigned char     gfrcr;          /* 0xFFF45081 - Global Firmware Revision Code */
252  unsigned char     reserved12[2];
253  unsigned char     reoir;          /* 0xFFF45084 - Receive End Of Interrupt */
254  unsigned char     teoir;          /* 0xFFF45085 - Transmit End Of Interrupt */
255  unsigned char     meoir;          /* 0xFFF45086 - Modem End Of Interrupt */
256  union {
257    struct {
258      unsigned short risr;          /* 0xFFF45088 - Receive Interrupt Status */
259    } w;
260    struct {
261      unsigned char risrh;          /* 0xFFF45088 - Receive Interrupt Status High */
262      unsigned char risrl;          /* 0xFFF45089 - Receive Interrupt Status Low */
263    } b;
264  } u5;   
265  unsigned char     tisr;           /* 0xFFF4508A - Transmit Interrupt Status */
266  unsigned char     misr;           /* 0xFFF4508B - Modem/Timer Interrupt Status */
267  unsigned char     reserved13[2];
268  unsigned char     bercnt;         /* 0xFFF4508E - Bus Error Retry Count */
269  unsigned char     reserved14[49];
270  unsigned char     tcor;           /* 0xFFF450C0 - Transmit Clock Option */
271  unsigned char     reserved15[2];
272  unsigned char     tbpr;           /* 0xFFF450C3 - Transmit Baud Rate Period */
273  unsigned char     reserved16[4];
274  unsigned char     rcor;           /* 0xFFF450C8 - Receive Clock Option */
275  unsigned char     reserved17[2];
276  unsigned char     rbpr;           /* 0xFFF450CB - Receive Baud Rate Period */
277  unsigned char     reserved18[10];
278  unsigned char     cpsr;           /* 0xFFF450D6 - CRC Polynomial Select */
279  unsigned char     reserved19[3];
280  unsigned char     tpr;            /* 0xFFF450DA - Timer Period */
281  unsigned char     reserved20[3];
282  unsigned char     msvr_rts;       /* 0xFFF450DE - Modem Signal Value - RTS */
283  unsigned char     msvr_dtr;       /* 0xFFF450DF - Modem Signal Value - DTR */
284  unsigned char     tpilr;          /* 0xFFF450E0 - Transmit Priority Interrupt Level */
285  unsigned char     rpilr;          /* 0xFFF450E1 - Receive Priority Interrupt Level */
286  unsigned char     stk;            /* 0xFFF450E2 - Stack */
287  unsigned char     mpilr;          /* 0xFFF450E3 - Modem Priority Interrupt Level */
288  unsigned char     reserved21[8];
289  unsigned char     tir;            /* 0xFFF450EC - Transmit Interrupt */
290  unsigned char     rir;            /* 0xFFF450ED - Receive Interrupt */
291  unsigned char     car;            /* 0xFFF450EE - Channel Access */
292  unsigned char     mir;            /* 0xFFF450EF - Model Interrupt */
293  unsigned char     reserved22[6];
294  unsigned char     dmr;            /* 0xFFF450F6 - DMA Mode */
295  unsigned char     reserved23;
296  unsigned char     dr;             /* 0xFFF450F8 - Receive/Transmit Data */
297} cd2401_regs;
298
299
300/*
301 *  Base address of the CD2401.
302 *  This is not configurable in the MVME167.
303 */
304#define cd2401          ((cd2401_regs * const) 0xFFF45000)
305
306
307/* CD2401 is clocked at 20 MHz */
308#define CD2401_CLK_RATE 20000000
309
310/* BSP-wide functions */
311
312void bsp_cleanup( void );
313
314m68k_isr_entry set_vector(
315  rtems_isr_entry     handler,
316  rtems_vector_number vector,
317  int                 type
318);
319
320#ifdef M167_INIT
321#undef EXTERN
322#define EXTERN
323#else
324#undef EXTERN
325#define EXTERN extern
326#endif
327
328/*
329 *  Device Driver Table Entries
330 */
331
332/*
333 * NOTE: Use the standard Console driver entry
334 */
335 
336/*
337 * NOTE: Use the standard Clock driver entry
338 */
339
340/*
341 * How many libio files we want
342 */
343
344#define BSP_LIBIO_MAX_FDS       20
345
346
347/* miscellaneous stuff assumed to exist */
348
349extern rtems_configuration_table BSP_Configuration;
350
351extern m68k_isr_entry M68Kvec[];   /* vector table address */
352
353
354/*
355 *  Define the time limits for RTEMS Test Suite test durations.
356 *  Long test and short test duration limits are provided.  These
357 *  values are in seconds and need to be converted to ticks for the
358 *  application.
359 *
360 */
361
362#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
363#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
364
365/*
366 *  Define the interrupt mechanism for Time Test 27
367 *
368 *  NOTE: We use software interrupt 0
369 */
370#define MUST_WAIT_FOR_INTERRUPT 0
371
372#define Install_tm27_vector( handler ) \
373            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
374            lcsr->intr_level[2] |= 3; \
375            lcsr->intr_ena |= 0x100
376
377#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100
378
379#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100
380
381#define Lower_tm27_intr()
382
383#ifdef __cplusplus
384}
385#endif
386
387#endif
388/* end of include file */
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