1 | /* |
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2 | * $Id$ |
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3 | * |
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4 | * This file was submitted by Eric Vaitl <vaitl@viasat.com>. |
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5 | * The manipulation of the page table has a very positive impact on |
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6 | * the performance of the MVME162. |
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7 | * |
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8 | * The following history is included verbatim from the submitter. |
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9 | * |
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10 | * Revision 1.8 1995/11/18 00:07:25 vaitl |
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11 | * Modified asm statements to get rid of the register hard-codes. |
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12 | * |
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13 | * Revision 1.7 1995/10/27 21:00:32 vaitl |
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14 | * Modified page table routines so application code can map |
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15 | * VME space. |
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16 | * |
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17 | * Revision 1.6 1995/10/26 17:40:01 vaitl |
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18 | * Two cache changes after reading the mvme162 users manual. |
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19 | * |
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20 | * 1) The users manual says that the MPU can act as a source for the |
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21 | * VME2 chip, so I made the VME accessable memory copy-back instead |
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22 | * of write through. I have't changed the comments yet. If this |
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23 | * causes problems, I'll change it back. |
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24 | * |
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25 | * 2) The 162 book also says that IO space should be serialized as well as |
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26 | * non-cacheable. I flipped the appropriate dttr0 and ittr0 registers. I |
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27 | * don't think this is really necessary because we don't recover from any |
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28 | * exceptions. If it slows down IO addresses too much, I'll change it back |
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29 | * and see what happens. |
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30 | * |
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31 | * Revision 1.5 1995/10/25 19:32:38 vaitl |
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32 | * Got it. Three problems: |
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33 | * 1) Must cpusha instead of cinva. |
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34 | * 2) On page descriptors the PDT field of 1 or 3 is resident. On pointer |
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35 | * descriptors resident is 2 or 3. I was using 2 for everything. |
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36 | * Changed it to 3 for everything. |
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37 | * 3) Forgot to do a pflusha. |
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38 | * |
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39 | * Revision 1.4 1995/10/25 17:47:11 vaitl |
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40 | * Still working on it. |
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41 | * |
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42 | * Revision 1.3 1995/10/25 17:16:05 vaitl |
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43 | * Working on page table. Caching partially set up, but can't currently |
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44 | * set tc register. |
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45 | * |
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46 | */ |
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47 | |
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48 | #include <string.h> |
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49 | #include <page_table.h> |
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50 | |
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51 | /* All page table must fit between BASE_TABLE_ADDR and |
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52 | MAX_TABLE_ADDR. */ |
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53 | |
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54 | #define BASE_TABLE_ADDR 0x10000 |
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55 | #define MAX_TABLE_ADDR 0x20000 |
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56 | #define ROOT_TABLE_SIZE 512 |
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57 | #define POINTER_TABLE_SIZE 512 |
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58 | #define PAGE_TABLE_SIZE 256 |
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59 | |
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60 | static unsigned long *root_table; |
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61 | static unsigned long *next_avail; |
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62 | |
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63 | /* Returns a zeroed out table. */ |
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64 | static unsigned long *table_alloc(int size){ |
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65 | unsigned long *addr=next_avail; |
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66 | if(((unsigned long)next_avail + size) > MAX_TABLE_ADDR){ |
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67 | return 0; |
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68 | } |
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69 | bzero((void *)addr,size); |
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70 | next_avail =(unsigned long *)((unsigned long)next_avail + size); |
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71 | return addr; |
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72 | } |
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73 | |
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74 | |
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75 | |
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76 | /* |
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77 | void page_table_init(); |
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78 | |
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79 | This should transparently map the first 4 Meg of ram. Caching is |
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80 | turned off from 0x00000000 to 0x00020000 (this region is used by |
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81 | 162Bug and contains the page tables). From 0x00020000 to 0x00400000 |
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82 | we are using copy back caching. DTTR0 and ITTR0 are set up to |
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83 | directly translate from 0x80000000-0xffffffff with caching turned |
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84 | off and serialized. Addresses between 0x400000 and 0x80000000 are |
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85 | illegal. |
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86 | */ |
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87 | void page_table_init(){ |
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88 | |
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89 | /* put everything in a known state */ |
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90 | page_table_teardown(); |
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91 | |
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92 | root_table=table_alloc(ROOT_TABLE_SIZE); |
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93 | |
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94 | /* First set up TTR. |
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95 | base address = 0x80000000 |
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96 | address mask = 0x7f |
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97 | Ignore FC2 for match. |
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98 | Noncachable. |
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99 | Not write protected.*/ |
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100 | asm volatile ("movec %0,%%dtt0 |
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101 | movec %0,%%itt0" |
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102 | :: "d" (0x807fc040)); |
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103 | |
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104 | /* Point urp and srp at root page table. */ |
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105 | asm volatile ("movec %0,%%urp |
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106 | movec %0,%%srp" |
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107 | :: "d" (BASE_TABLE_ADDR)); |
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108 | |
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109 | page_table_map((void *)0,0x20000, CACHE_NONE); |
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110 | page_table_map((void *)0x20000,0x400000-0x20000,CACHE_COPYBACK); |
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111 | |
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112 | /* Turn on paging with a 4 k page size.*/ |
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113 | asm volatile ("movec %0,%%tc" |
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114 | :: "d" (0x8000)); |
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115 | |
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116 | /* Turn on the cache. */ |
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117 | asm volatile ("movec %0,%%cacr" |
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118 | :: "d" (0x80008000)); |
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119 | } |
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120 | |
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121 | void page_table_teardown(){ |
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122 | next_avail=(unsigned long *)BASE_TABLE_ADDR; |
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123 | /* Turn off paging. Turn off the cache. Flush the cache. Tear down |
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124 | the transparent translations. */ |
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125 | asm volatile ("movec %0,%%tc |
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126 | movec %0,%%cacr |
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127 | cpusha %%bc |
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128 | movec %0,%%dtt0 |
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129 | movec %0,%%itt0 |
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130 | movec %0,%%dtt1 |
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131 | movec %0,%%itt1" |
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132 | :: "d" (0) ); |
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133 | } |
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134 | |
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135 | /* Identity maps addr to addr+size with caching cache_type. */ |
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136 | int page_table_map(void *addr, unsigned long size, int cache_type){ |
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137 | unsigned long *pointer_table; |
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138 | unsigned long *page_table; |
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139 | unsigned long root_index, pointer_index, page_index; |
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140 | /* addr must be a multiple of 4k */ |
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141 | if((unsigned long)addr & 0xfff){ |
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142 | return PTM_BAD_ADDR; |
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143 | } |
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144 | /* size must also be a multiple of 4k */ |
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145 | if(size & 0xfff){ |
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146 | return PTM_BAD_SIZE; |
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147 | } |
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148 | /* check for valid cache type */ |
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149 | if( (cache_type>CACHE_NONE) || (cache_type<CACHE_WRITE_THROUGH)){ |
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150 | return PTM_BAD_CACHE; |
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151 | } |
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152 | |
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153 | while(size){ |
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154 | root_index=(unsigned long)addr; |
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155 | root_index >>= 25; |
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156 | root_index &= 0x7f; |
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157 | |
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158 | if(root_table[root_index]){ |
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159 | pointer_table = |
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160 | (unsigned long *) (root_table[root_index] & 0xfffffe00); |
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161 | }else{ |
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162 | if(!(pointer_table=table_alloc(POINTER_TABLE_SIZE))){ |
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163 | return PTM_NO_TABLE_SPACE; |
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164 | } |
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165 | root_table[root_index]=((unsigned long)pointer_table) + 0x03; |
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166 | } |
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167 | |
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168 | pointer_index=(unsigned long)addr; |
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169 | pointer_index >>=18; |
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170 | pointer_index &= 0x7f; |
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171 | |
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172 | if(pointer_table[pointer_index]){ |
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173 | page_table = |
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174 | (unsigned long *) (pointer_table[pointer_index] & |
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175 | 0xffffff00); |
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176 | }else{ |
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177 | if(!(page_table=table_alloc(PAGE_TABLE_SIZE))){ |
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178 | return PTM_NO_TABLE_SPACE; |
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179 | } |
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180 | pointer_table[pointer_index]= |
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181 | ((unsigned long)page_table) + 0x03; |
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182 | } |
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183 | |
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184 | page_index=(unsigned long)addr; |
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185 | page_index >>=12; |
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186 | page_index &= 0x3f; |
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187 | |
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188 | page_table[page_index] = |
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189 | ((unsigned long) addr & 0xfffff000) + 0x03 + (cache_type << 5); |
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190 | |
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191 | size -= 4096; |
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192 | addr = (void *) ((unsigned long)addr + 4096); |
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193 | } |
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194 | |
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195 | /* Flush the ATC. Push and invalidate the cache. */ |
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196 | asm volatile ("pflusha |
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197 | cpusha %bc"); |
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198 | |
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199 | return PTM_SUCCESS; |
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200 | } |
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201 | |
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202 | |
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