source: rtems/c/src/lib/libbsp/m68k/mvme162/startup/page_table.c @ 7593d56c

4.104.114.84.95
Last change on this file since 7593d56c was 7593d56c, checked in by Joel Sherrill <joel.sherrill@…>, on 12/19/95 at 19:22:55

file lost in crash and re-added

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File size: 5.8 KB
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1/*
2 *  $Id$
3 *
4 *  This file was submitted by Eric Vaitl <vaitl@viasat.com>.
5 *  The manipulation of the page table has a very positive impact on
6 *  the performance of the MVME162.
7 *
8 *  The following history is included verbatim from the submitter.
9 *
10 * Revision 1.8  1995/11/18  00:07:25  vaitl
11 * Modified asm statements to get rid of the register hard-codes.
12 *
13 * Revision 1.7  1995/10/27  21:00:32  vaitl
14 * Modified page table routines so application code can map
15 * VME space.
16 *
17 * Revision 1.6  1995/10/26  17:40:01  vaitl
18 * Two cache changes after reading the mvme162 users manual.
19 *
20 * 1) The users manual says that the MPU can act as a source for the
21 *    VME2 chip, so I made the VME accessable memory copy-back instead
22 *    of write through.  I have't changed the comments yet. If this
23 *    causes problems, I'll change it back.
24 *
25 * 2) The 162 book also says that IO space should be serialized as well as
26 *    non-cacheable. I flipped the appropriate dttr0 and ittr0 registers. I
27 *    don't think this is really necessary because we don't recover from any
28 *    exceptions. If it slows down IO addresses too much, I'll change it back
29 *    and see what happens.
30 *
31 * Revision 1.5  1995/10/25  19:32:38  vaitl
32 * Got it. Three problems:
33 *   1) Must cpusha instead of cinva.
34 *   2) On page descriptors the PDT field of 1 or 3 is resident. On pointer
35 *      descriptors resident is 2 or 3. I was using 2 for everything.
36 *      Changed it to 3 for everything.
37 *   3) Forgot to do a pflusha.
38 *
39 * Revision 1.4  1995/10/25  17:47:11  vaitl
40 * Still working on it.
41 *
42 * Revision 1.3  1995/10/25  17:16:05  vaitl
43 * Working on page table. Caching partially set up, but can't currently
44 * set tc register.
45 *
46*/
47#include <string.h>
48#include "page_table.h"
49
50/* All page table must fit between BASE_TABLE_ADDR and
51   MAX_TABLE_ADDR. */
52
53#define BASE_TABLE_ADDR 0x10000
54#define MAX_TABLE_ADDR 0x20000
55#define ROOT_TABLE_SIZE 512
56#define POINTER_TABLE_SIZE 512
57#define PAGE_TABLE_SIZE 256
58
59static unsigned long *root_table;
60static unsigned long *next_avail;
61
62/* Returns a zeroed out table. */
63static unsigned long *table_alloc(int size){
64    unsigned long *addr=next_avail;
65    if(((unsigned long)next_avail + size) > MAX_TABLE_ADDR){
66        return 0;
67    }
68    bzero((void *)addr,size);
69    next_avail =(unsigned long *)((unsigned long)next_avail + size);
70    return addr;
71}
72
73
74
75/*
76   void page_table_init();
77
78   This should transparently map the first 4 Meg of ram.  Caching is
79   turned off from 0x00000000 to 0x00020000 (this region is used by
80   162Bug and contains the page tables). From 0x00020000 to 0x00400000
81   we are using copy back caching. DTTR0 and ITTR0 are set up to
82   directly translate from 0x80000000-0xffffffff with caching turned
83   off and serialized. Addresses between 0x400000 and 0x80000000 are
84   illegal.
85*/
86void page_table_init(){
87   
88    /* put everything in a known state */
89    page_table_teardown();
90
91    root_table=table_alloc(ROOT_TABLE_SIZE);
92
93    /* First set up TTR.
94       base address = 0x80000000
95       address mask = 0x7f
96       Ignore FC2 for match.
97       Noncachable.
98       Not write protected.*/
99    asm volatile ("movec %0,%%dtt0
100                   movec %0,%%itt0"
101                  :: "d" (0x807fc040));
102
103    /* Point urp and srp at root page table. */
104    asm volatile ("movec %0,%%urp
105                   movec %0,%%srp"
106                  :: "d" (BASE_TABLE_ADDR));
107
108    page_table_map((void *)0,0x20000, CACHE_NONE);
109    page_table_map((void *)0x20000,0x400000-0x20000,CACHE_COPYBACK);
110
111    /* Turn on paging with a 4 k page size.*/
112    asm volatile ("movec %0,%%tc"
113                  :: "d" (0x8000));
114
115    /* Turn on the cache. */
116    asm volatile ("movec %0,%%cacr"
117                  :: "d" (0x80008000));
118}
119 
120void page_table_teardown(){
121    next_avail=(unsigned long *)BASE_TABLE_ADDR;
122    /* Turn off paging.  Turn off the cache. Flush the cache. Tear down
123       the transparent translations. */
124    asm volatile ("movec %0,%%tc
125                   movec %0,%%cacr
126                   cpusha %%bc
127                   movec %0,%%dtt0
128                   movec %0,%%itt0
129                   movec %0,%%dtt1
130                   movec %0,%%itt1"
131                  :: "d" (0) );
132}
133
134/* Identity maps addr to addr+size with caching cache_type. */
135int page_table_map(void *addr, unsigned long size, int cache_type){
136    unsigned long *pointer_table;
137    unsigned long *page_table;
138    unsigned long root_index, pointer_index, page_index;
139    /* addr must be a multiple of 4k */
140    if((unsigned long)addr & 0xfff){
141        return  PTM_BAD_ADDR;
142    }
143    /* size must also be a multiple of 4k */
144    if(size & 0xfff){
145        return PTM_BAD_SIZE;
146    }
147    /* check for valid cache type */
148    if( (cache_type>CACHE_NONE) || (cache_type<CACHE_WRITE_THROUGH)){
149        return PTM_BAD_CACHE;
150    }
151
152    while(size){
153        root_index=(unsigned long)addr;
154        root_index >>= 25;
155        root_index &= 0x7f;
156
157        if(root_table[root_index]){
158            pointer_table =
159                (unsigned long *) (root_table[root_index] & 0xfffffe00);
160        }else{
161            if(!(pointer_table=table_alloc(POINTER_TABLE_SIZE))){
162                return  PTM_NO_TABLE_SPACE;
163            }
164            root_table[root_index]=((unsigned long)pointer_table) + 0x03;
165        }
166       
167        pointer_index=(unsigned long)addr;
168        pointer_index >>=18;
169        pointer_index &= 0x7f;
170       
171        if(pointer_table[pointer_index]){
172            page_table =
173                (unsigned long *) (pointer_table[pointer_index] &
174                                   0xffffff00);
175        }else{
176            if(!(page_table=table_alloc(PAGE_TABLE_SIZE))){
177                return  PTM_NO_TABLE_SPACE;
178            }
179            pointer_table[pointer_index]=
180                ((unsigned long)page_table) + 0x03; 
181        }
182
183        page_index=(unsigned long)addr;
184        page_index >>=12;
185        page_index &= 0x3f;
186
187        page_table[page_index] =
188            ((unsigned long) addr & 0xfffff000) + 0x03 + (cache_type << 5);
189
190        size -= 4096;
191        addr = (void *) ((unsigned long)addr + 4096);
192    }
193
194    /* Flush the ATC. Push and invalidate the cache. */
195    asm volatile ("pflusha
196                   cpusha %bc");
197
198    return  PTM_SUCCESS;
199}
200
201
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