1 | /* mvme16x_hw.h |
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2 | * |
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3 | * This include file contains all MVME16x board IO definitions |
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4 | * and was derived by combining the common items in the |
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5 | * mvme162 and mvme167 BSPs. |
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6 | * |
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7 | * COPYRIGHT (c) 1989-2000. |
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8 | * On-Line Applications Research Corporation (OAR). |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.OARcorp.com/rtems/license.html. |
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13 | * |
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14 | * $Id# |
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15 | */ |
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16 | |
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17 | #ifndef __MVME16xHW_h |
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18 | #define __MVME16xHW_h |
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19 | |
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20 | #ifdef __cplusplus |
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21 | extern "C" { |
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22 | #endif |
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23 | |
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24 | /* |
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25 | * Network driver configuration |
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26 | */ |
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27 | |
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28 | struct rtems_bsdnet_ifconfig; |
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29 | int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching ); |
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30 | #define RTEMS_BSP_NETWORK_DRIVER_NAME "uti1" |
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31 | #define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach |
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32 | |
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33 | /* |
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34 | * This is NOT the base address of local RAM! |
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35 | * This is the base local address of the VMEbus short I/O space. A local |
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36 | * access to this space results in a A16 VMEbus I/O cycle. This base address |
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37 | * is NOT configurable on the MVME167, although the types of VMEbus short I/O |
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38 | * cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address |
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39 | * range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The |
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40 | * GCSRs of other boards are accessible only through the VMEbus short I/O |
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41 | * space. See pages 2-45 and 2-7. |
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42 | */ |
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43 | #define BOARD_BASE_ADDRESS 0xFFFF0000 |
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44 | |
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45 | /* |
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46 | * This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of |
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47 | * other MVMEs in the group, i.e. it represents the offset of the GCSRs in the |
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48 | * VMEbus short I/O space. It also should represent the group address of this |
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49 | * MVME167! The group address is configurable, and must match the address |
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50 | * programmed into the MVME167 through the 167Bug monitor. 0xCC is the address |
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51 | * recommended by Motorola. It is arbitrary. |
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52 | * See pages 2-42 and 2-97 to 2-104. |
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53 | */ |
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54 | #define GROUP_BASE_ADDRESS 0x0000CC00 |
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55 | |
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56 | |
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57 | /* |
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58 | * Representation of the VMEchip2 LCSR. |
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59 | * Could be made more detailed. |
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60 | */ |
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61 | |
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62 | typedef volatile struct { |
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63 | unsigned long slave_adr[2]; |
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64 | unsigned long slave_trn[2]; |
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65 | unsigned long slave_ctl; |
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66 | unsigned long mastr_adr[4]; |
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67 | unsigned long mastr_trn; |
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68 | unsigned long mastr_att; |
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69 | unsigned long mastr_ctl; |
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70 | unsigned long dma_ctl_1; |
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71 | unsigned long dma_ctl_2; |
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72 | unsigned long dma_loc_cnt; |
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73 | unsigned long dma_vme_cnt; |
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74 | unsigned long dma_byte_cnt; |
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75 | unsigned long dma_adr_cnt; |
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76 | unsigned long dma_status; |
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77 | unsigned long to_ctl; |
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78 | unsigned long timer_cmp_1; |
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79 | unsigned long timer_cnt_1; |
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80 | unsigned long timer_cmp_2; |
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81 | unsigned long timer_cnt_2; |
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82 | unsigned long board_ctl; |
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83 | unsigned long prescaler_cnt; |
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84 | unsigned long intr_stat; |
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85 | unsigned long intr_ena; |
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86 | unsigned long intr_soft_set; |
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87 | unsigned long intr_clear; |
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88 | unsigned long intr_level[4]; |
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89 | unsigned long vector_base; |
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90 | } lcsr_regs; |
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91 | |
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92 | /* |
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93 | * Base address of VMEchip2 LCSR |
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94 | * Not configurable on the MVME167. |
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95 | * XXX what about 162? |
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96 | */ |
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97 | #define lcsr ((lcsr_regs * const) 0xFFF40000) |
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98 | |
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99 | /* |
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100 | * Vector numbers for the interrupts from the VMEchip2. Use the values |
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101 | * "recommended" by Motorola. |
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102 | * See pages 2-70 to 2-92, and table 2-3. |
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103 | */ |
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104 | |
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105 | /* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */ |
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106 | #define MASK_INT 0x00800000 |
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107 | |
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108 | /* The content of VBR0 corresponds to "X" in table 2-3 */ |
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109 | #define VBR0 0x6 |
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110 | |
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111 | /* The content of VBR1 corresponds to "Y" in table 2-3 */ |
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112 | #define VBR1 0x7 |
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113 | |
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114 | /* |
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115 | * Representation of the PCCchip2 |
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116 | */ |
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117 | typedef volatile struct pccchip2_regs_ { |
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118 | unsigned char chip_id; /* 0xFFF42000 */ |
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119 | unsigned char chip_revision; /* 0xFFF42001 */ |
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120 | unsigned char gen_control; /* 0xFFF42002 */ |
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121 | unsigned char vector_base; /* 0xFFF42003 */ |
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122 | unsigned long timer_cmp_1; /* 0xFFF42004 */ |
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123 | unsigned long timer_cnt_1; /* 0xFFF42008 */ |
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124 | unsigned long timer_cmp_2; /* 0xFFF4200C */ |
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125 | unsigned long timer_cnt_2; /* 0xFFF42010 */ |
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126 | unsigned char LSB_prescaler_count;/* 0xFFF42014 */ |
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127 | unsigned char prescaler_clock_adjust; /* 0xFFF42015 */ |
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128 | unsigned char timer_ctl_2; /* 0xFFF42016 */ |
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129 | unsigned char timer_ctl_1; /* 0xFFF42017 */ |
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130 | unsigned char gpi_int_ctl; /* 0xFFF42018 */ |
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131 | unsigned char gpio_ctl; /* 0xFFF42019 */ |
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132 | unsigned char timer_int_ctl_2; /* 0xFFF4201A */ |
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133 | unsigned char timer_int_ctl_1; /* 0xFFF4201B */ |
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134 | unsigned char SCC_error; /* 0xFFF4201C */ |
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135 | unsigned char SCC_modem_int_ctl; /* 0xFFF4201D */ |
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136 | unsigned char SCC_tx_int_ctl; /* 0xFFF4201E */ |
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137 | unsigned char SCC_rx_int_ctl; /* 0xFFF4201F */ |
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138 | unsigned char reserved1[3]; |
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139 | unsigned char modem_piack; /* 0xFFF42023 */ |
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140 | unsigned char reserved2; |
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141 | unsigned char tx_piack; /* 0xFFF42025 */ |
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142 | unsigned char reserved3; |
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143 | unsigned char rx_piack; /* 0xFFF42027 */ |
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144 | unsigned char LANC_error; /* 0xFFF42028 */ |
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145 | unsigned char reserved4; |
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146 | unsigned char LANC_int_ctl; /* 0xFFF4202A */ |
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147 | unsigned char LANC_berr_ctl; /* 0xFFF4202B */ |
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148 | unsigned char SCSI_error; /* 0xFFF4202C */ |
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149 | unsigned char reserved5[2]; |
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150 | unsigned char SCSI_int_ctl; /* 0xFFF4202F */ |
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151 | unsigned char print_ack_int_ctl; /* 0xFFF42030 */ |
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152 | unsigned char print_fault_int_ctl;/* 0xFFF42031 */ |
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153 | unsigned char print_sel_int_ctl; /* 0xFFF42032 */ |
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154 | unsigned char print_pe_int_ctl; /* 0xFFF42033 */ |
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155 | unsigned char print_busy_int_ctl; /* 0xFFF42034 */ |
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156 | unsigned char reserved6; |
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157 | unsigned char print_input_status; /* 0xFFF42036 */ |
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158 | unsigned char print_ctl; /* 0xFFF42037 */ |
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159 | unsigned char chip_speed; /* 0xFFF42038 */ |
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160 | unsigned char reserved7; |
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161 | unsigned char print_data; /* 0xFFF4203A */ |
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162 | unsigned char reserved8[3]; |
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163 | unsigned char int_level; /* 0xFFF4203E */ |
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164 | unsigned char int_mask; /* 0xFFF4203F */ |
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165 | } pccchip2_regs; |
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166 | |
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167 | /* |
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168 | * Base address of the PCCchip2. |
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169 | * This is not configurable in the MVME167. |
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170 | */ |
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171 | #define pccchip2 ((pccchip2_regs * const) 0xFFF42000) |
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172 | |
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173 | /* |
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174 | * On the MVME162, we have the mcchip and the pccchip2 on |
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175 | * the 167. They are similar but different enough where |
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176 | * we have to reconcile them later. |
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177 | */ |
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178 | |
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179 | /* |
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180 | * Vector numbers for the interrupts from the PCCchip2. Use the values |
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181 | * "recommended" by Motorola. |
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182 | * See page 3-15. |
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183 | */ |
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184 | #define PCCCHIP2_VBR 0x5 |
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185 | |
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186 | /* |
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187 | * The following registers are located in the VMEbus short |
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188 | * IO space and respond to address modifier codes $29 and $2D. |
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189 | * On FORCE CPU use address gcsr_vme and device /dev/vme16d32. |
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190 | */ |
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191 | |
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192 | typedef volatile struct { |
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193 | unsigned char chip_revision; |
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194 | unsigned char chip_id; |
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195 | unsigned char lmsig; |
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196 | unsigned char board_scr; |
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197 | unsigned short gpr[6]; |
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198 | } gcsr_regs; |
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199 | |
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200 | #define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS)) |
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201 | #define gcsr ((gcsr_regs * const) 0xFFF40100) |
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202 | |
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203 | /* |
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204 | * Representation of 82596CA LAN controller: Memory Map |
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205 | */ |
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206 | typedef volatile struct i82596_regs_ { |
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207 | unsigned short port_lower; /* 0xFFF46000 */ |
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208 | unsigned short port_upper; /* 0xFFF46002 */ |
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209 | unsigned long chan_attn; /* 0xFFF46004 */ |
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210 | } i82596_regs; |
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211 | |
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212 | /* |
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213 | * Base address of the 82596. |
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214 | */ |
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215 | #define i82596 ((i82596_regs * const) 0xFFF46000) |
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216 | |
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217 | /* |
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218 | * Representation of initialization data in NVRAM |
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219 | */ |
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220 | typedef volatile struct nvram_config_ { |
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221 | unsigned char dcache_enable; /* 0xFFFC0000 */ |
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222 | unsigned char icache_enable; /* 0xFFFC0001 */ |
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223 | unsigned short cache_mode; /* 0xFFFC0002 */ |
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224 | unsigned long ipaddr; /* 0xFFFC0004 */ |
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225 | unsigned long netmask; /* 0xFFFC0008 */ |
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226 | unsigned char enaddr[6]; /* 0xFFFC000C */ |
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227 | unsigned short processor_id; /* 0xFFFC0012 */ |
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228 | unsigned long rma_start; /* 0xFFFC0014 */ |
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229 | unsigned long vma_start; /* 0xFFFC0018 */ |
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230 | unsigned long ramsize; /* 0xFFFC001C */ |
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231 | } nvram_config; |
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232 | |
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233 | /* |
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234 | * Pointer to the base of User Area NVRAM |
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235 | */ |
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236 | #define nvram ((nvram_config * const) 0xFFFC0000) |
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237 | |
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238 | |
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239 | #ifdef __cplusplus |
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240 | } |
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241 | #endif |
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242 | |
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243 | #endif |
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244 | /* end of include file */ |
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