source: rtems/c/src/lib/libbsp/m68k/mvme162/include/mvme16x_hw.h @ 0eca1d08

4.104.114.84.95
Last change on this file since 0eca1d08 was 0eca1d08, checked in by Joel Sherrill <joel.sherrill@…>, on Sep 15, 2000 at 1:12:12 PM

2000-09-14 Joel Sherrill <joel@…>

  • include/mvme16x_hw.h: Include rtems/score/targopts.h so we can check which BSP this is being used with.
  • Property mode set to 100644
File size: 8.4 KB
Line 
1/*  mvme16x_hw.h
2 *
3 *  This include file contains all MVME16x board IO definitions
4 *  and was derived by combining the common items in the
5 *  mvme162 and mvme167 BSPs.
6 *
7 *  COPYRIGHT (c) 1989-2000.
8 *  On-Line Applications Research Corporation (OAR).
9 *
10 *  The license and distribution terms for this file may be
11 *  found in the file LICENSE in this distribution or at
12 *  http://www.OARcorp.com/rtems/license.html.
13 *
14 *  $Id#
15 */
16
17#ifndef __MVME16xHW_h
18#define __MVME16xHW_h
19
20#include <rtems/score/targopts.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 * Network driver configuration
28 */
29 
30struct rtems_bsdnet_ifconfig;
31int uti596_attach(struct rtems_bsdnet_ifconfig * pConfig, int attaching );
32#define RTEMS_BSP_NETWORK_DRIVER_NAME   "uti1"
33#define RTEMS_BSP_NETWORK_DRIVER_ATTACH uti596_attach
34
35/*
36 *  This is NOT the base address of local RAM!
37 *  This is the base local address of the VMEbus short I/O space. A local
38 *  access to this space results in a A16 VMEbus I/O cycle. This base address
39 *  is NOT configurable on the MVME167, although the types of VMEbus short I/O
40 *  cycles generated when a cycle in the local 0xFFFF0000-0xFFFFFFFF address
41 *  range is generated is under control of bits 8-15 of LCSR 0xFFF4002C. The
42 *  GCSRs of other boards are accessible only through the VMEbus short I/O
43 *  space. See pages 2-45 and 2-7.
44 */
45#define BOARD_BASE_ADDRESS 0xFFFF0000
46
47/*
48 *  This address must be added to the BOARD_BASE_ADDRESS to access the GCSR of
49 *  other MVMEs in the group, i.e. it represents the offset of the GCSRs in the
50 *  VMEbus short I/O space. It also should represent the group address of this
51 *  MVME167! The group address is configurable, and must match the address
52 *  programmed into the MVME167 through the 167Bug monitor. 0xCC is the address
53 *  recommended by Motorola. It is arbitrary.
54 *  See pages 2-42 and 2-97 to 2-104.
55 */
56#define GROUP_BASE_ADDRESS 0x0000CC00
57
58
59/*
60 *  Representation of the VMEchip2 LCSR.
61 *  Could be made more detailed.
62 */
63
64typedef volatile struct {
65  unsigned long     slave_adr[2];
66  unsigned long     slave_trn[2];
67  unsigned long     slave_ctl;
68  unsigned long     mastr_adr[4];
69  unsigned long     mastr_trn;
70  unsigned long     mastr_att;
71  unsigned long     mastr_ctl;
72  unsigned long     dma_ctl_1;
73  unsigned long     dma_ctl_2;
74  unsigned long     dma_loc_cnt;
75  unsigned long     dma_vme_cnt;
76  unsigned long     dma_byte_cnt;
77  unsigned long     dma_adr_cnt;
78  unsigned long     dma_status;
79  unsigned long     to_ctl;
80  unsigned long     timer_cmp_1;
81  unsigned long     timer_cnt_1;
82  unsigned long     timer_cmp_2;
83  unsigned long     timer_cnt_2;
84  unsigned long     board_ctl;
85  unsigned long     prescaler_cnt;
86  unsigned long     intr_stat;
87  unsigned long     intr_ena;
88  unsigned long     intr_soft_set;
89  unsigned long     intr_clear;
90  unsigned long     intr_level[4];
91  unsigned long     vector_base;
92} lcsr_regs;
93
94/* 
95 *  Base address of VMEchip2 LCSR
96 *  Not configurable on the MVME167.
97 *  XXX what about 162?
98 */
99#define lcsr        ((lcsr_regs * const) 0xFFF40000)
100
101/*
102 *  Vector numbers for the interrupts from the VMEchip2. Use the values
103 *  "recommended" by Motorola.
104 *  See pages 2-70 to 2-92, and table 2-3.
105 */
106
107/* MIEN (Master Interrupt Enable) bit in LCSR 0xFFF40088. */
108#define MASK_INT    0x00800000
109
110/* The content of VBR0 corresponds to "X" in table 2-3 */
111#define VBR0        0x6
112
113/* The content of VBR1 corresponds to "Y" in table 2-3 */
114#define VBR1        0x7
115
116/*
117 *  Representation of the PCCchip2
118 */
119typedef volatile struct pccchip2_regs_ {
120  unsigned char     chip_id;            /* 0xFFF42000 */
121  unsigned char     chip_revision;      /* 0xFFF42001 */
122  unsigned char     gen_control;        /* 0xFFF42002 */
123  unsigned char     vector_base;        /* 0xFFF42003 */
124  unsigned long     timer_cmp_1;        /* 0xFFF42004 */
125  unsigned long     timer_cnt_1;        /* 0xFFF42008 */
126  unsigned long     timer_cmp_2;        /* 0xFFF4200C */
127  unsigned long     timer_cnt_2;        /* 0xFFF42010 */
128  unsigned char     LSB_prescaler_count;/* 0xFFF42014 */
129  unsigned char     prescaler_clock_adjust; /* 0xFFF42015 */
130  unsigned char     timer_ctl_2;        /* 0xFFF42016 */
131  unsigned char     timer_ctl_1;        /* 0xFFF42017 */
132  unsigned char     gpi_int_ctl;        /* 0xFFF42018 */
133  unsigned char     gpio_ctl;           /* 0xFFF42019 */
134  unsigned char     timer_int_ctl_2;    /* 0xFFF4201A */
135  unsigned char     timer_int_ctl_1;    /* 0xFFF4201B */
136  unsigned char     SCC_error;          /* 0xFFF4201C */
137  unsigned char     SCC_modem_int_ctl;  /* 0xFFF4201D */
138  unsigned char     SCC_tx_int_ctl;     /* 0xFFF4201E */
139  unsigned char     SCC_rx_int_ctl;     /* 0xFFF4201F */
140  unsigned char     reserved1[3];
141  unsigned char     modem_piack;        /* 0xFFF42023 */
142  unsigned char     reserved2;
143  unsigned char     tx_piack;           /* 0xFFF42025 */
144  unsigned char     reserved3;
145  unsigned char     rx_piack;           /* 0xFFF42027 */
146  unsigned char     LANC_error;         /* 0xFFF42028 */
147  unsigned char     reserved4;
148  unsigned char     LANC_int_ctl;       /* 0xFFF4202A */
149  unsigned char     LANC_berr_ctl;      /* 0xFFF4202B */
150  unsigned char     SCSI_error;         /* 0xFFF4202C */
151  unsigned char     reserved5[2];
152  unsigned char     SCSI_int_ctl;       /* 0xFFF4202F */
153  unsigned char     print_ack_int_ctl;  /* 0xFFF42030 */
154  unsigned char     print_fault_int_ctl;/* 0xFFF42031 */
155  unsigned char     print_sel_int_ctl;  /* 0xFFF42032 */
156  unsigned char     print_pe_int_ctl;   /* 0xFFF42033 */
157  unsigned char     print_busy_int_ctl; /* 0xFFF42034 */
158  unsigned char     reserved6;
159  unsigned char     print_input_status; /* 0xFFF42036 */
160  unsigned char     print_ctl;          /* 0xFFF42037 */
161  unsigned char     chip_speed;         /* 0xFFF42038 */
162  unsigned char     reserved7;
163  unsigned char     print_data;         /* 0xFFF4203A */
164  unsigned char     reserved8[3];
165  unsigned char     int_level;          /* 0xFFF4203E */
166  unsigned char     int_mask;           /* 0xFFF4203F */
167} pccchip2_regs;
168
169/*
170 *  Base address of the PCCchip2.
171 *  This is not configurable in the MVME167.
172 */
173#define pccchip2    ((pccchip2_regs * const) 0xFFF42000)
174
175/*
176 *  On the MVME162, we have the mcchip and the pccchip2 on
177 *  the 167.  They are similar but different enough where
178 *  we have to reconcile them later.
179 */
180
181/*
182 * Vector numbers for the interrupts from the PCCchip2. Use the values
183 * "recommended" by Motorola.
184 * See page 3-15.
185 */
186#define PCCCHIP2_VBR    0x5
187
188/*
189 * The following registers are located in the VMEbus short
190 * IO space and respond to address modifier codes $29 and $2D.
191 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
192 */
193
194typedef volatile struct {
195  unsigned char       chip_revision;
196  unsigned char       chip_id;
197  unsigned char       lmsig;
198  unsigned char       board_scr;
199  unsigned short      gpr[6];
200} gcsr_regs;
201
202#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
203#define gcsr     ((gcsr_regs * const) 0xFFF40100)
204
205/*
206 *  Representation of 82596CA LAN controller: Memory Map
207 */
208typedef volatile struct i82596_regs_ {
209  unsigned short  port_lower;             /* 0xFFF46000 */
210  unsigned short  port_upper;             /* 0xFFF46002 */
211  unsigned long   chan_attn;              /* 0xFFF46004 */
212} i82596_regs;
213
214/*
215 *  Base address of the 82596.
216 */
217
218#define i82596    ((i82596_regs * const) 0xFFF46000)
219
220/*
221 *  Representation of initialization data in NVRAM
222 */
223
224#if defined(mvme167)
225typedef volatile struct nvram_config_ {
226  unsigned char   cache_mode;          /* 0xFFFC0000 */
227  unsigned char   console_mode;        /* 0xFFFC0001 */
228  unsigned char   console_printk_port; /* 0xFFFC0002 */
229  unsigned char   pad1;                /* 0xFFFC0003 */
230  unsigned long   ipaddr;              /* 0xFFFC0004 */
231  unsigned long   netmask;             /* 0xFFFC0008 */
232  unsigned char   enaddr[6];           /* 0xFFFC000C */
233  unsigned short  processor_id;        /* 0xFFFC0012 */
234  unsigned long   rma_start;           /* 0xFFFC0014 */
235  unsigned long   vma_start;           /* 0xFFFC0018 */
236  unsigned long   ramsize;             /* 0xFFFC001C */
237} nvram_config;
238
239/*
240 *  Pointer to the base of User Area NVRAM
241 */
242
243#define nvram      ((nvram_config * const) 0xFFFC0000)
244
245#endif
246
247
248/*
249 *  Flag to indicate if J1-4 is on (and parameters should be
250 *  sought in User Area NVRAM)
251 */
252
253#if defined(mvme167)
254#define NVRAM_CONFIGURE \
255  ( !( ( (unsigned char)(lcsr->vector_base & 0xFF) ) & 0x10 ) )
256#else
257#define NVRAM_CONFIGURE 0
258#endif
259
260
261#ifdef __cplusplus
262}
263#endif
264
265#endif
266/* end of include file */
Note: See TracBrowser for help on using the repository browser.