source: rtems/c/src/lib/libbsp/m68k/mvme162/include/bsp.h @ c6fb8e90

4.104.114.84.95
Last change on this file since c6fb8e90 was c6fb8e90, checked in by Joel Sherrill <joel.sherrill@…>, on 08/01/95 at 15:33:39

updated mvme162 code from Misha (mms@…)

  • Property mode set to 100644
File size: 7.0 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all MVME162 board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
14 *  EISCAT Scientific Association. M.Savitski
15 *
16 *  This material is a part of the MVME162 Board Support Package
17 *  for the RTEMS executive. Its licensing policies are those of the
18 *  RTEMS above.
19 *
20 *  $Id$
21 */
22
23#ifndef __MVME162_h
24#define __MVME162_h
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems.h>
31#include <iosupp.h>
32
33/*
34 * Following defines must reflect the setup of the particular MVME162
35 */
36
37#define GROUP_BASE_ADDRESS    0x0000F200
38#define BOARD_BASE_ADDRESS    0xFFFF0000
39
40/* Base for local interrupters' vectors (with enable bit set) */
41
42#define MASK_INT              0x00800000
43#define VBR0                  0x6
44#define VBR1                  0x7
45
46/* RAM limits */
47
48#define RAM_START             0x00100000
49#define RAM_END               0x00200000
50
51/*
52 * ----------------------------------
53 */
54
55typedef volatile struct lcsr_regs {
56  unsigned long     slave_adr[2];
57  unsigned long     slave_trn[2];
58  unsigned long     slave_ctl;
59  unsigned long     mastr_adr[4];
60  unsigned long     mastr_trn;
61  unsigned long     mastr_att;
62  unsigned long     mastr_ctl;
63  unsigned long     dma_ctl_1;
64  unsigned long     dma_ctl_2;
65  unsigned long     dma_loc_cnt;
66  unsigned long     dma_vme_cnt;
67  unsigned long     dma_byte_cnt;
68  unsigned long     dma_adr_cnt;
69  unsigned long     dma_status;
70  unsigned long     to_ctl;
71  unsigned long     timer_cmp_1;
72  unsigned long     timer_cnt_1;
73  unsigned long     timer_cmp_2;
74  unsigned long     timer_cnt_2;
75  unsigned long     board_ctl;
76  unsigned long     prescaler_cnt;
77  unsigned long     intr_stat;
78  unsigned long     intr_ena;
79  unsigned long     intr_soft_set;
80  unsigned long     intr_clear;
81  unsigned long     intr_level[4];
82  unsigned long     vector_base;
83} lcsr_regs;
84
85#define lcsr      ((lcsr_regs * const) 0xFFF40000)
86
87typedef volatile struct mcchip_regs {
88
89  unsigned char     chipID;
90  unsigned char     chipREV;
91  unsigned char     gen_control;
92  unsigned char     vector_base;
93 
94  unsigned long     timer_cmp_1;
95  unsigned long     timer_cnt_1;
96  unsigned long     timer_cmp_2;
97  unsigned long     timer_cnt_2;
98 
99  unsigned char     LSB_prescaler_count;
100  unsigned char     prescaler_clock_adjust;
101  unsigned char     time_ctl_2;
102  unsigned char     time_ctl_1;
103 
104  unsigned char     time_int_ctl_4;
105  unsigned char     time_int_ctl_3;
106  unsigned char     time_int_ctl_2;
107  unsigned char     time_int_ctl_1;
108 
109  unsigned char     dram_err_int_ctl;
110  unsigned char     SCC_int_ctl;
111  unsigned char     time_ctl_4;
112  unsigned char     time_ctl_3;
113 
114  unsigned short    DRAM_space_base;
115  unsigned short    SRAM_space_base;
116 
117  unsigned char     DRAM_size;
118  unsigned char     DRAM_SRAM_opt;
119  unsigned char     SRAM_size;
120  unsigned char     reserved;
121
122  unsigned char     LANC_error;
123  unsigned char     reserved1;
124  unsigned char     LANC_int_ctl;
125  unsigned char     LANC_berr_ctl;
126
127  unsigned char     SCSI_error;
128  unsigned char     general_inputs;
129  unsigned char     MVME_162_version;
130  unsigned char     SCSI_int_ctl;
131
132  unsigned long     timer_cmp_3;
133  unsigned long     timer_cnt_3;
134  unsigned long     timer_cmp_4;
135  unsigned long     timer_cnt_4;
136 
137  unsigned char     bus_clk;
138  unsigned char     PROM_acc_time_ctl;
139  unsigned char     FLASH_acc_time_ctl;
140  unsigned char     ABORT_int_ctl;
141 
142  unsigned char     RESET_ctl;
143  unsigned char     watchdog_timer_ctl;
144  unsigned char     acc_watchdog_time_base_sel;
145  unsigned char     reserved2;
146 
147  unsigned char     DRAM_ctl;
148  unsigned char     reserved4;
149  unsigned char     MPU_status;
150  unsigned char     reserved3;
151 
152  unsigned long     prescaler_count;
153 
154} mcchip_regs;
155
156#define mcchip      ((mcchip_regs * const) 0xFFF42000)
157
158/*----------------------------------------------------------------*/
159
160/*
161 * SCC Z8523(0) defines and macros
162 * -------------------------------
163 * Prototypes for the low-level serial io are also included here,
164 * because such stuff is bsp-specific (yet). The function bodies
165 * are in console.c
166 */
167
168enum {portB, portA};
169
170rtems_boolean char_ready(int port, char *ch);
171char char_wait(int port);
172void char_put(int port, char ch);
173
174#define TX_BUFFER_EMPTY   0x04
175#define RX_DATA_AVAILABLE 0x01
176#define SCC_VECTOR        0x40
177
178typedef volatile struct scc_regs {
179  unsigned char pad1;
180  volatile unsigned char          csr;
181  unsigned char pad2;
182  volatile unsigned char          buf;
183} scc_regs;
184
185#define scc       ((scc_regs * const) 0xFFF45000)
186
187#define ZWRITE0(port, v)  (scc[port].csr = (unsigned char)(v))
188#define ZREAD0(port)  (scc[port].csr)
189
190#define ZREAD(port, n)  (ZWRITE0(port, n), (scc[port].csr))
191#define ZREADD(port)  (scc[port].buf)
192
193#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v))
194#define ZWRITED(port, v)  (scc[port].buf = (unsigned char)(v))
195/*----------------------------------------------------------------*/
196
197/*
198 * The following registers are located in the VMEbus short
199 * IO space and respond to address modifier codes $29 and $2D.
200 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
201*/
202typedef volatile struct gcsr_regs {
203  unsigned char       chip_revision;
204  unsigned char       chip_id;
205  unsigned char       lmsig;
206  unsigned char       board_scr;
207  unsigned short      gpr[6];
208} gcsr_regs;
209
210#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
211#define gcsr     ((gcsr_regs * const) 0xFFF40100)
212
213/*
214 *  Define the time limits for RTEMS Test Suite test durations.
215 *  Long test and short test duration limits are provided.  These
216 *  values are in seconds and need to be converted to ticks for the
217 *  application.
218 *
219 */
220
221#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
222#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
223
224/*
225 *  Define the interrupt mechanism for Time Test 27
226 *
227 *  NOTE: We use software interrupt 0
228 */
229
230#define MUST_WAIT_FOR_INTERRUPT 0
231
232#define Install_tm27_vector( handler ) \
233            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
234            lcsr->intr_level[2] |= 3; \
235            lcsr->intr_ena |= 0x100;
236
237#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100
238
239#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100
240
241#define Lower_tm27_intr()
242
243#ifdef M162_INIT
244#undef EXTERN
245#define EXTERN
246#else
247#undef EXTERN
248#define EXTERN extern
249#endif
250
251/* miscellaneous stuff assumed to exist */
252
253extern rtems_configuration_table BSP_Configuration;
254
255extern m68k_isr_entry M68Kvec[];   /* vector table address */
256
257/* functions */
258
259void bsp_cleanup( void );
260
261m68k_isr_entry set_vector(
262  rtems_isr_entry     handler,
263  rtems_vector_number vector,
264  int                 type
265);
266
267#ifdef __cplusplus
268}
269#endif
270
271#endif
272/* end of include file */
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