1 | /* bsp.h |
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2 | * |
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3 | * This include file contains all MVME162fx board IO definitions. |
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4 | * |
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5 | * COPYRIGHT (c) 1989-1998. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * Copyright assigned to U.S. Government, 1994. |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.OARcorp.com/rtems/license.html. |
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12 | * |
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13 | * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. |
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14 | * EISCAT Scientific Association. M.Savitski |
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15 | * |
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16 | * This material is a part of the MVME162 Board Support Package |
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17 | * for the RTEMS executive. Its licensing policies are those of the |
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18 | * RTEMS above. |
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19 | * |
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20 | * $Id$ |
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21 | */ |
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22 | |
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23 | #ifndef __MVME162_h |
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24 | #define __MVME162_h |
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25 | |
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26 | #ifdef __cplusplus |
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27 | extern "C" { |
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28 | #endif |
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29 | |
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30 | #include <rtems.h> |
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31 | #include <clockdrv.h> |
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32 | #include <console.h> |
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33 | #include <iosupp.h> |
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34 | |
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35 | /* |
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36 | * Following defines must reflect the setup of the particular MVME162 |
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37 | */ |
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38 | |
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39 | #define GROUP_BASE_ADDRESS 0x0000F200 |
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40 | #define BOARD_BASE_ADDRESS 0xFFFF0000 |
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41 | |
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42 | /* Base for local interrupters' vectors (with enable bit set) */ |
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43 | |
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44 | #define MASK_INT 0x00800000 |
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45 | #define VBR0 0x6 |
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46 | #define VBR1 0x7 |
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47 | |
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48 | /* RAM limits */ |
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49 | |
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50 | #define RAM_START 0x00100000 |
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51 | #define RAM_END 0x00200000 |
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52 | |
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53 | /* |
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54 | * ---------------------------------- |
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55 | */ |
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56 | |
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57 | typedef volatile struct lcsr_regs { |
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58 | unsigned long slave_adr[2]; |
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59 | unsigned long slave_trn[2]; |
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60 | unsigned long slave_ctl; |
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61 | unsigned long mastr_adr[4]; |
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62 | unsigned long mastr_trn; |
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63 | unsigned long mastr_att; |
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64 | unsigned long mastr_ctl; |
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65 | unsigned long dma_ctl_1; |
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66 | unsigned long dma_ctl_2; |
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67 | unsigned long dma_loc_cnt; |
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68 | unsigned long dma_vme_cnt; |
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69 | unsigned long dma_byte_cnt; |
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70 | unsigned long dma_adr_cnt; |
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71 | unsigned long dma_status; |
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72 | unsigned long to_ctl; |
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73 | unsigned long timer_cmp_1; |
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74 | unsigned long timer_cnt_1; |
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75 | unsigned long timer_cmp_2; |
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76 | unsigned long timer_cnt_2; |
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77 | unsigned long board_ctl; |
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78 | unsigned long prescaler_cnt; |
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79 | unsigned long intr_stat; |
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80 | unsigned long intr_ena; |
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81 | unsigned long intr_soft_set; |
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82 | unsigned long intr_clear; |
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83 | unsigned long intr_level[4]; |
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84 | unsigned long vector_base; |
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85 | } lcsr_regs; |
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86 | |
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87 | #define lcsr ((lcsr_regs * const) 0xFFF40000) |
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88 | |
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89 | typedef volatile struct mcchip_regs { |
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90 | |
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91 | unsigned char chipID; |
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92 | unsigned char chipREV; |
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93 | unsigned char gen_control; |
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94 | unsigned char vector_base; |
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95 | |
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96 | unsigned long timer_cmp_1; |
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97 | unsigned long timer_cnt_1; |
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98 | unsigned long timer_cmp_2; |
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99 | unsigned long timer_cnt_2; |
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100 | |
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101 | unsigned char LSB_prescaler_count; |
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102 | unsigned char prescaler_clock_adjust; |
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103 | unsigned char time_ctl_2; |
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104 | unsigned char time_ctl_1; |
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105 | |
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106 | unsigned char time_int_ctl_4; |
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107 | unsigned char time_int_ctl_3; |
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108 | unsigned char time_int_ctl_2; |
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109 | unsigned char time_int_ctl_1; |
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110 | |
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111 | unsigned char dram_err_int_ctl; |
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112 | unsigned char SCC_int_ctl; |
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113 | unsigned char time_ctl_4; |
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114 | unsigned char time_ctl_3; |
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115 | |
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116 | unsigned short DRAM_space_base; |
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117 | unsigned short SRAM_space_base; |
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118 | |
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119 | unsigned char DRAM_size; |
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120 | unsigned char DRAM_SRAM_opt; |
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121 | unsigned char SRAM_size; |
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122 | unsigned char reserved; |
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123 | |
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124 | unsigned char LANC_error; |
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125 | unsigned char reserved1; |
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126 | unsigned char LANC_int_ctl; |
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127 | unsigned char LANC_berr_ctl; |
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128 | |
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129 | unsigned char SCSI_error; |
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130 | unsigned char general_inputs; |
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131 | unsigned char MVME_162_version; |
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132 | unsigned char SCSI_int_ctl; |
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133 | |
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134 | unsigned long timer_cmp_3; |
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135 | unsigned long timer_cnt_3; |
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136 | unsigned long timer_cmp_4; |
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137 | unsigned long timer_cnt_4; |
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138 | |
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139 | unsigned char bus_clk; |
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140 | unsigned char PROM_acc_time_ctl; |
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141 | unsigned char FLASH_acc_time_ctl; |
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142 | unsigned char ABORT_int_ctl; |
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143 | |
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144 | unsigned char RESET_ctl; |
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145 | unsigned char watchdog_timer_ctl; |
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146 | unsigned char acc_watchdog_time_base_sel; |
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147 | unsigned char reserved2; |
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148 | |
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149 | unsigned char DRAM_ctl; |
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150 | unsigned char reserved4; |
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151 | unsigned char MPU_status; |
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152 | unsigned char reserved3; |
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153 | |
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154 | unsigned long prescaler_count; |
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155 | |
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156 | } mcchip_regs; |
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157 | |
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158 | #define mcchip ((mcchip_regs * const) 0xFFF42000) |
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159 | |
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160 | /*----------------------------------------------------------------*/ |
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161 | |
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162 | /* |
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163 | * SCC Z8523(0) defines and macros |
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164 | * ------------------------------- |
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165 | * Prototypes for the low-level serial io are also included here, |
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166 | * because such stuff is bsp-specific (yet). The function bodies |
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167 | * are in console.c |
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168 | * |
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169 | * NOTE from Eric Vaitl <evaitl@viasat.com>: |
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170 | * |
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171 | * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a |
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172 | * bug in the MC2 chip (revision 1) such that the SCC data register is |
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173 | * not accessible, it has to be accessed indirectly through the SCC |
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174 | * control register. |
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175 | */ |
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176 | |
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177 | enum {portB, portA}; |
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178 | |
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179 | rtems_boolean char_ready(int port, char *ch); |
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180 | char char_wait(int port); |
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181 | void char_put(int port, char ch); |
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182 | |
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183 | #define TX_BUFFER_EMPTY 0x04 |
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184 | #define RX_DATA_AVAILABLE 0x01 |
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185 | #define SCC_VECTOR 0x40 |
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186 | |
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187 | typedef volatile struct scc_regs { |
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188 | unsigned char pad1; |
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189 | volatile unsigned char csr; |
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190 | unsigned char pad2; |
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191 | volatile unsigned char buf; |
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192 | } scc_regs; |
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193 | |
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194 | #define scc ((scc_regs * const) 0xFFF45000) |
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195 | |
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196 | #define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) |
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197 | #define ZREAD0(port) (scc[port].csr) |
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198 | |
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199 | #define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) |
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200 | #define ZREADD(port) (scc[port].csr=0x08, scc[port].csr ) |
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201 | |
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202 | #define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) |
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203 | #define ZWRITED(port, v) (scc[port].csr = 0x08, \ |
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204 | scc[port].csr = (unsigned char)(v)) |
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205 | /*----------------------------------------------------------------*/ |
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206 | |
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207 | /* |
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208 | * The following registers are located in the VMEbus short |
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209 | * IO space and respond to address modifier codes $29 and $2D. |
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210 | * On FORCE CPU use address gcsr_vme and device /dev/vme16d32. |
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211 | */ |
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212 | typedef volatile struct gcsr_regs { |
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213 | unsigned char chip_revision; |
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214 | unsigned char chip_id; |
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215 | unsigned char lmsig; |
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216 | unsigned char board_scr; |
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217 | unsigned short gpr[6]; |
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218 | } gcsr_regs; |
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219 | |
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220 | #define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS)) |
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221 | #define gcsr ((gcsr_regs * const) 0xFFF40100) |
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222 | |
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223 | /* |
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224 | * Define the time limits for RTEMS Test Suite test durations. |
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225 | * Long test and short test duration limits are provided. These |
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226 | * values are in seconds and need to be converted to ticks for the |
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227 | * application. |
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228 | * |
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229 | */ |
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230 | |
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231 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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232 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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233 | |
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234 | /* |
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235 | * Define the interrupt mechanism for Time Test 27 |
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236 | * |
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237 | * NOTE: We use software interrupt 0 |
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238 | */ |
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239 | |
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240 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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241 | |
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242 | #define Install_tm27_vector( handler ) \ |
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243 | set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ |
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244 | lcsr->intr_level[2] |= 3; \ |
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245 | lcsr->intr_ena |= 0x100; |
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246 | |
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247 | #define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 |
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248 | |
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249 | #define Clear_tm27_intr() lcsr->intr_clear |= 0x100 |
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250 | |
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251 | #define Lower_tm27_intr() |
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252 | |
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253 | #ifdef M162_INIT |
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254 | #undef EXTERN |
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255 | #define EXTERN |
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256 | #else |
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257 | #undef EXTERN |
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258 | #define EXTERN extern |
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259 | #endif |
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260 | |
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261 | /* |
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262 | * Device Driver Table Entries |
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263 | */ |
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264 | |
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265 | /* |
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266 | * NOTE: Use the standard Console driver entry |
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267 | */ |
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268 | |
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269 | /* |
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270 | * NOTE: Use the standard Clock driver entry |
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271 | */ |
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272 | |
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273 | /* |
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274 | * How many libio files we want |
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275 | */ |
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276 | |
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277 | #define BSP_LIBIO_MAX_FDS 20 |
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278 | |
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279 | /* miscellaneous stuff assumed to exist */ |
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280 | |
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281 | extern rtems_configuration_table BSP_Configuration; |
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282 | |
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283 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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284 | |
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285 | /* functions */ |
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286 | |
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287 | void bsp_cleanup( void ); |
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288 | |
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289 | m68k_isr_entry set_vector( |
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290 | rtems_isr_entry handler, |
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291 | rtems_vector_number vector, |
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292 | int type |
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293 | ); |
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294 | |
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295 | #ifdef __cplusplus |
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296 | } |
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297 | #endif |
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298 | |
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299 | #endif |
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300 | /* end of include file */ |
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