source: rtems/c/src/lib/libbsp/m68k/mvme162/include/bsp.h @ b3decdb

4.115
Last change on this file since b3decdb was b3decdb, checked in by Joel Sherrill <joel.sherrill@…>, on 02/02/12 at 20:08:08

PR 1962/bsps - MVME162 Console Corrections and Improvements

  • console/console.c: char_ready() was never returning true so console never processed input data
  • console/console.c: added printk() support to default device
  • include/bsp.h: Added #define for MOT_162BUG_VEC_ADDRESS
  • startup/bspclean.c: Modified to use MOT_162BUG_VEC_ADDRESS
  • startup/bspstart.c: Modified to use MOT_162BUG_VEC_ADDRESS
  • make/custom/mvme162.cfg: Modified to use "RTEMS_CPU_MODEL=68lc040" and "CPU_CFLAGS = -mcpu=68040 -msoft-float" so BSP will always work with all board variations.
  • README: Added notes on user required configuration changes and information about board models and variants
  • README.models: New file that contains a detailed list of MVME162 models and variants.

Signed-off-by: Vic Hoover <victor.hoover.ctr@…>

  • Property mode set to 100644
File size: 5.3 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all MVME162fx board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
13 *  EISCAT Scientific Association. M.Savitski
14 *
15 *  This material is a part of the MVME162 Board Support Package
16 *  for the RTEMS executive. Its licensing policies are those of the
17 *  RTEMS above.
18 *
19 *  $Id$
20 */
21
22#ifndef _BSP_H
23#define _BSP_H
24
25#ifdef __cplusplus
26extern "C" {
27#endif
28
29#include <bspopts.h>
30
31#include <rtems.h>
32#include <rtems/clockdrv.h>
33#include <rtems/console.h>
34#include <rtems/iosupp.h>
35
36#include <mvme16x_hw.h>
37
38/*----------------------------------------------------------------*/
39
40typedef volatile struct {
41
42  unsigned char     chipID;
43  unsigned char     chipREV;
44  unsigned char     gen_control;
45  unsigned char     vector_base;
46
47  unsigned long     timer_cmp_1;
48  unsigned long     timer_cnt_1;
49  unsigned long     timer_cmp_2;
50  unsigned long     timer_cnt_2;
51
52  unsigned char     LSB_prescaler_count;
53  unsigned char     prescaler_clock_adjust;
54  unsigned char     time_ctl_2;
55  unsigned char     time_ctl_1;
56
57  unsigned char     time_int_ctl_4;
58  unsigned char     time_int_ctl_3;
59  unsigned char     time_int_ctl_2;
60  unsigned char     time_int_ctl_1;
61
62  unsigned char     dram_err_int_ctl;
63  unsigned char     SCC_int_ctl;
64  unsigned char     time_ctl_4;
65  unsigned char     time_ctl_3;
66
67  unsigned short    DRAM_space_base;
68  unsigned short    SRAM_space_base;
69
70  unsigned char     DRAM_size;
71  unsigned char     DRAM_SRAM_opt;
72  unsigned char     SRAM_size;
73  unsigned char     reserved;
74
75  unsigned char     LANC_error;
76  unsigned char     reserved1;
77  unsigned char     LANC_int_ctl;
78  unsigned char     LANC_berr_ctl;
79
80  unsigned char     SCSI_error;
81  unsigned char     general_inputs;
82  unsigned char     MVME_162_version;
83  unsigned char     SCSI_int_ctl;
84
85  unsigned long     timer_cmp_3;
86  unsigned long     timer_cnt_3;
87  unsigned long     timer_cmp_4;
88  unsigned long     timer_cnt_4;
89
90  unsigned char     bus_clk;
91  unsigned char     PROM_acc_time_ctl;
92  unsigned char     FLASH_acc_time_ctl;
93  unsigned char     ABORT_int_ctl;
94
95  unsigned char     RESET_ctl;
96  unsigned char     watchdog_timer_ctl;
97  unsigned char     acc_watchdog_time_base_sel;
98  unsigned char     reserved2;
99
100  unsigned char     DRAM_ctl;
101  unsigned char     reserved4;
102  unsigned char     MPU_status;
103  unsigned char     reserved3;
104
105  unsigned long     prescaler_count;
106
107} mcchip_regs;
108
109#define mcchip      ((mcchip_regs * const) 0xFFF42000)
110
111/*----------------------------------------------------------------*/
112
113/*
114 * SCC Z8523(0) defines and macros
115 * -------------------------------
116 * Prototypes for the low-level serial io are also included here,
117 * because such stuff is bsp-specific (yet). The function bodies
118 * are in console.c
119 *
120 * NOTE from Eric Vaitl <evaitl@viasat.com>:
121 *
122 * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a
123 * bug in the MC2 chip (revision 1) such that the SCC data register is
124 * not accessible, it has to be accessed indirectly through the SCC
125 * control register.
126 */
127
128enum {portB, portA};
129
130extern bool char_ready(int port, char *ch);
131extern char char_wait(int port);
132extern void char_put(int port, char ch);
133
134#define TX_BUFFER_EMPTY   0x04
135#define RX_DATA_AVAILABLE 0x01
136#define SCC_VECTOR        0x40
137
138typedef volatile struct {
139  unsigned char pad1;
140  volatile unsigned char          csr;
141  unsigned char pad2;
142  volatile unsigned char          buf;
143} scc_regs;
144
145#define scc       ((scc_regs * const) 0xFFF45000)
146
147#define ZWRITE0(port, v)  (scc[port].csr = (unsigned char)(v))
148#define ZREAD0(port)  (scc[port].csr)
149
150#define ZREAD(port, n)  (ZWRITE0(port, n), (scc[port].csr))
151#define ZREADD(port)  (scc[port].csr=0x08, scc[port].csr )
152
153#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v))
154#define ZWRITED(port, v)  (scc[port].csr = 0x08, \
155                           scc[port].csr = (unsigned char)(v))
156/*----------------------------------------------------------------*/
157
158#ifdef M162_INIT
159#undef EXTERN
160#define EXTERN
161#else
162#undef EXTERN
163#define EXTERN extern
164#endif
165
166
167/*
168 *  This value is the default address location of the 162Bug vector table
169 *  and is also the default start address of the boards DRAM.  This value
170 *  may be different for your specific board based on a number of factors:
171 *
172 *     Default DRAM address:   0x00000000
173 *     Default SRAM address:   0xFFE00000
174 *
175 *  o  If no DRAM can be found by the 162Bug program, it will use SRAM.
176 *  o  The default SRAM address may be different if SRAM mezzanine boards
177 *     are installed on the main board.
178 *  o  Both the DRAM and SRAM addresses can be modified by changing the
179 *     appropriate values in NVRAM using the ENV command at the 162Bug
180 *     prompt.
181 *
182 *  If your board has different values than the defaults, change the value
183 *  of the following define.
184 *
185 */
186#define MOT_162BUG_VEC_ADDRESS  0x00000000
187
188extern m68k_isr_entry M68Kvec[];   /* vector table address */
189
190/* functions */
191
192m68k_isr_entry set_vector(
193  rtems_isr_entry     handler,
194  rtems_vector_number vector,
195  int                 type
196);
197
198#ifdef __cplusplus
199}
200#endif
201
202#endif
Note: See TracBrowser for help on using the repository browser.