source: rtems/c/src/lib/libbsp/m68k/mvme162/include/bsp.h @ a863c50

4.104.114.84.95
Last change on this file since a863c50 was a863c50, checked in by Joel Sherrill <joel.sherrill@…>, on May 18, 1998 at 2:41:15 PM

Updates from Pedro Romano.

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File size: 7.4 KB
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1/*  bsp.h
2 *
3 *  This include file contains all MVME162fx board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989-1998.
6 *  On-Line Applications Research Corporation (OAR).
7 *  Copyright assigned to U.S. Government, 1994.
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  Modifications of respective RTEMS file: COPYRIGHT (c) 1994.
14 *  EISCAT Scientific Association. M.Savitski
15 *
16 *  This material is a part of the MVME162 Board Support Package
17 *  for the RTEMS executive. Its licensing policies are those of the
18 *  RTEMS above.
19 *
20 *  $Id$
21 */
22
23#ifndef __MVME162_h
24#define __MVME162_h
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30#include <rtems.h>
31#include <clockdrv.h>
32#include <console.h>
33#include <iosupp.h>
34
35/*
36 * Following defines must reflect the setup of the particular MVME162
37 */
38
39#define GROUP_BASE_ADDRESS    0x0000F200
40#define BOARD_BASE_ADDRESS    0xFFFF0000
41
42/* Base for local interrupters' vectors (with enable bit set) */
43
44#define MASK_INT              0x00800000
45#define VBR0                  0x6
46#define VBR1                  0x7
47
48/* RAM limits */
49
50#define RAM_START             0x00100000
51#define RAM_END               0x00200000
52
53/*
54 * ----------------------------------
55 */
56
57typedef volatile struct {
58  unsigned long     slave_adr[2];
59  unsigned long     slave_trn[2];
60  unsigned long     slave_ctl;
61  unsigned long     mastr_adr[4];
62  unsigned long     mastr_trn;
63  unsigned long     mastr_att;
64  unsigned long     mastr_ctl;
65  unsigned long     dma_ctl_1;
66  unsigned long     dma_ctl_2;
67  unsigned long     dma_loc_cnt;
68  unsigned long     dma_vme_cnt;
69  unsigned long     dma_byte_cnt;
70  unsigned long     dma_adr_cnt;
71  unsigned long     dma_status;
72  unsigned long     to_ctl;
73  unsigned long     timer_cmp_1;
74  unsigned long     timer_cnt_1;
75  unsigned long     timer_cmp_2;
76  unsigned long     timer_cnt_2;
77  unsigned long     board_ctl;
78  unsigned long     prescaler_cnt;
79  unsigned long     intr_stat;
80  unsigned long     intr_ena;
81  unsigned long     intr_soft_set;
82  unsigned long     intr_clear;
83  unsigned long     intr_level[4];
84  unsigned long     vector_base;
85} lcsr_regs;
86
87#define lcsr      ((lcsr_regs * const) 0xFFF40000)
88
89typedef volatile struct {
90
91  unsigned char     chipID;
92  unsigned char     chipREV;
93  unsigned char     gen_control;
94  unsigned char     vector_base;
95 
96  unsigned long     timer_cmp_1;
97  unsigned long     timer_cnt_1;
98  unsigned long     timer_cmp_2;
99  unsigned long     timer_cnt_2;
100 
101  unsigned char     LSB_prescaler_count;
102  unsigned char     prescaler_clock_adjust;
103  unsigned char     time_ctl_2;
104  unsigned char     time_ctl_1;
105 
106  unsigned char     time_int_ctl_4;
107  unsigned char     time_int_ctl_3;
108  unsigned char     time_int_ctl_2;
109  unsigned char     time_int_ctl_1;
110 
111  unsigned char     dram_err_int_ctl;
112  unsigned char     SCC_int_ctl;
113  unsigned char     time_ctl_4;
114  unsigned char     time_ctl_3;
115 
116  unsigned short    DRAM_space_base;
117  unsigned short    SRAM_space_base;
118 
119  unsigned char     DRAM_size;
120  unsigned char     DRAM_SRAM_opt;
121  unsigned char     SRAM_size;
122  unsigned char     reserved;
123
124  unsigned char     LANC_error;
125  unsigned char     reserved1;
126  unsigned char     LANC_int_ctl;
127  unsigned char     LANC_berr_ctl;
128
129  unsigned char     SCSI_error;
130  unsigned char     general_inputs;
131  unsigned char     MVME_162_version;
132  unsigned char     SCSI_int_ctl;
133
134  unsigned long     timer_cmp_3;
135  unsigned long     timer_cnt_3;
136  unsigned long     timer_cmp_4;
137  unsigned long     timer_cnt_4;
138 
139  unsigned char     bus_clk;
140  unsigned char     PROM_acc_time_ctl;
141  unsigned char     FLASH_acc_time_ctl;
142  unsigned char     ABORT_int_ctl;
143 
144  unsigned char     RESET_ctl;
145  unsigned char     watchdog_timer_ctl;
146  unsigned char     acc_watchdog_time_base_sel;
147  unsigned char     reserved2;
148 
149  unsigned char     DRAM_ctl;
150  unsigned char     reserved4;
151  unsigned char     MPU_status;
152  unsigned char     reserved3;
153 
154  unsigned long     prescaler_count;
155 
156} mcchip_regs;
157
158#define mcchip      ((mcchip_regs * const) 0xFFF42000)
159
160/*----------------------------------------------------------------*/
161
162/*
163 * SCC Z8523(0) defines and macros
164 * -------------------------------
165 * Prototypes for the low-level serial io are also included here,
166 * because such stuff is bsp-specific (yet). The function bodies
167 * are in console.c
168 *
169 * NOTE from Eric Vaitl <evaitl@viasat.com>:
170 *
171 * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a
172 * bug in the MC2 chip (revision 1) such that the SCC data register is
173 * not accessible, it has to be accessed indirectly through the SCC
174 * control register.
175 */
176
177enum {portB, portA};
178
179rtems_boolean char_ready(int port, char *ch);
180char char_wait(int port);
181void char_put(int port, char ch);
182
183#define TX_BUFFER_EMPTY   0x04
184#define RX_DATA_AVAILABLE 0x01
185#define SCC_VECTOR        0x40
186
187typedef volatile struct {
188  unsigned char pad1;
189  volatile unsigned char          csr;
190  unsigned char pad2;
191  volatile unsigned char          buf;
192} scc_regs;
193
194#define scc       ((scc_regs * const) 0xFFF45000)
195
196#define ZWRITE0(port, v)  (scc[port].csr = (unsigned char)(v))
197#define ZREAD0(port)  (scc[port].csr)
198
199#define ZREAD(port, n)  (ZWRITE0(port, n), (scc[port].csr))
200#define ZREADD(port)  (scc[port].csr=0x08, scc[port].csr )
201
202#define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v))
203#define ZWRITED(port, v)  (scc[port].csr = 0x08, \
204                           scc[port].csr = (unsigned char)(v))
205/*----------------------------------------------------------------*/
206
207/*
208 * The following registers are located in the VMEbus short
209 * IO space and respond to address modifier codes $29 and $2D.
210 * On FORCE CPU use address gcsr_vme and device /dev/vme16d32.
211*/
212typedef volatile struct {
213  unsigned char       chip_revision;
214  unsigned char       chip_id;
215  unsigned char       lmsig;
216  unsigned char       board_scr;
217  unsigned short      gpr[6];
218} gcsr_regs;
219
220#define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS))
221#define gcsr     ((gcsr_regs * const) 0xFFF40100)
222
223/*
224 *  Define the time limits for RTEMS Test Suite test durations.
225 *  Long test and short test duration limits are provided.  These
226 *  values are in seconds and need to be converted to ticks for the
227 *  application.
228 *
229 */
230
231#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
232#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
233
234/*
235 *  Define the interrupt mechanism for Time Test 27
236 *
237 *  NOTE: We use software interrupt 0
238 */
239
240#define MUST_WAIT_FOR_INTERRUPT 0
241
242#define Install_tm27_vector( handler ) \
243            set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \
244            lcsr->intr_level[2] |= 3; \
245            lcsr->intr_ena |= 0x100;
246
247#define Cause_tm27_intr()  lcsr->intr_soft_set |= 0x100
248
249#define Clear_tm27_intr()  lcsr->intr_clear |= 0x100
250
251#define Lower_tm27_intr()
252
253#ifdef M162_INIT
254#undef EXTERN
255#define EXTERN
256#else
257#undef EXTERN
258#define EXTERN extern
259#endif
260
261/*
262 *  Device Driver Table Entries
263 */
264
265/*
266 * NOTE: Use the standard Console driver entry
267 */
268 
269/*
270 * NOTE: Use the standard Clock driver entry
271 */
272
273/* miscellaneous stuff assumed to exist */
274
275extern rtems_configuration_table BSP_Configuration;
276
277extern m68k_isr_entry M68Kvec[];   /* vector table address */
278
279/* functions */
280
281void bsp_cleanup( void );
282
283m68k_isr_entry set_vector(
284  rtems_isr_entry     handler,
285  rtems_vector_number vector,
286  int                 type
287);
288
289#ifdef __cplusplus
290}
291#endif
292
293#endif
294/* end of include file */
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