1 | /* |
---|
2 | * This include file contains all MVME162fx board IO definitions. |
---|
3 | */ |
---|
4 | |
---|
5 | /* |
---|
6 | * COPYRIGHT (c) 1989-2014. |
---|
7 | * On-Line Applications Research Corporation (OAR). |
---|
8 | * |
---|
9 | * The license and distribution terms for this file may be |
---|
10 | * found in the file LICENSE in this distribution or at |
---|
11 | * http://www.rtems.org/license/LICENSE. |
---|
12 | * |
---|
13 | * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. |
---|
14 | * EISCAT Scientific Association. M.Savitski |
---|
15 | * |
---|
16 | * This material is a part of the MVME162 Board Support Package |
---|
17 | * for the RTEMS executive. Its licensing policies are those of the |
---|
18 | * RTEMS above. |
---|
19 | */ |
---|
20 | |
---|
21 | #ifndef _BSP_H |
---|
22 | #define _BSP_H |
---|
23 | |
---|
24 | #include <bspopts.h> |
---|
25 | #include <bsp/default-initial-extension.h> |
---|
26 | |
---|
27 | #include <rtems.h> |
---|
28 | #include <rtems/clockdrv.h> |
---|
29 | #include <rtems/console.h> |
---|
30 | #include <rtems/iosupp.h> |
---|
31 | |
---|
32 | #include <mvme16x_hw.h> |
---|
33 | |
---|
34 | #ifdef __cplusplus |
---|
35 | extern "C" { |
---|
36 | #endif |
---|
37 | |
---|
38 | /*----------------------------------------------------------------*/ |
---|
39 | |
---|
40 | typedef volatile struct { |
---|
41 | |
---|
42 | unsigned char chipID; |
---|
43 | unsigned char chipREV; |
---|
44 | unsigned char gen_control; |
---|
45 | unsigned char vector_base; |
---|
46 | |
---|
47 | unsigned long timer_cmp_1; |
---|
48 | unsigned long timer_cnt_1; |
---|
49 | unsigned long timer_cmp_2; |
---|
50 | unsigned long timer_cnt_2; |
---|
51 | |
---|
52 | unsigned char LSB_prescaler_count; |
---|
53 | unsigned char prescaler_clock_adjust; |
---|
54 | unsigned char time_ctl_2; |
---|
55 | unsigned char time_ctl_1; |
---|
56 | |
---|
57 | unsigned char time_int_ctl_4; |
---|
58 | unsigned char time_int_ctl_3; |
---|
59 | unsigned char time_int_ctl_2; |
---|
60 | unsigned char time_int_ctl_1; |
---|
61 | |
---|
62 | unsigned char dram_err_int_ctl; |
---|
63 | unsigned char SCC_int_ctl; |
---|
64 | unsigned char time_ctl_4; |
---|
65 | unsigned char time_ctl_3; |
---|
66 | |
---|
67 | unsigned short DRAM_space_base; |
---|
68 | unsigned short SRAM_space_base; |
---|
69 | |
---|
70 | unsigned char DRAM_size; |
---|
71 | unsigned char DRAM_SRAM_opt; |
---|
72 | unsigned char SRAM_size; |
---|
73 | unsigned char reserved; |
---|
74 | |
---|
75 | unsigned char LANC_error; |
---|
76 | unsigned char reserved1; |
---|
77 | unsigned char LANC_int_ctl; |
---|
78 | unsigned char LANC_berr_ctl; |
---|
79 | |
---|
80 | unsigned char SCSI_error; |
---|
81 | unsigned char general_inputs; |
---|
82 | unsigned char MVME_162_version; |
---|
83 | unsigned char SCSI_int_ctl; |
---|
84 | |
---|
85 | unsigned long timer_cmp_3; |
---|
86 | unsigned long timer_cnt_3; |
---|
87 | unsigned long timer_cmp_4; |
---|
88 | unsigned long timer_cnt_4; |
---|
89 | |
---|
90 | unsigned char bus_clk; |
---|
91 | unsigned char PROM_acc_time_ctl; |
---|
92 | unsigned char FLASH_acc_time_ctl; |
---|
93 | unsigned char ABORT_int_ctl; |
---|
94 | |
---|
95 | unsigned char RESET_ctl; |
---|
96 | unsigned char watchdog_timer_ctl; |
---|
97 | unsigned char acc_watchdog_time_base_sel; |
---|
98 | unsigned char reserved2; |
---|
99 | |
---|
100 | unsigned char DRAM_ctl; |
---|
101 | unsigned char reserved4; |
---|
102 | unsigned char MPU_status; |
---|
103 | unsigned char reserved3; |
---|
104 | |
---|
105 | unsigned long prescaler_count; |
---|
106 | |
---|
107 | } mcchip_regs; |
---|
108 | |
---|
109 | #define mcchip ((mcchip_regs * const) 0xFFF42000) |
---|
110 | |
---|
111 | /*----------------------------------------------------------------*/ |
---|
112 | |
---|
113 | /* |
---|
114 | * SCC Z8523(0) defines and macros |
---|
115 | * ------------------------------- |
---|
116 | * Prototypes for the low-level serial io are also included here, |
---|
117 | * because such stuff is bsp-specific (yet). The function bodies |
---|
118 | * are in console.c |
---|
119 | * |
---|
120 | * NOTE from Eric Vaitl <evaitl@viasat.com>: |
---|
121 | * |
---|
122 | * I dropped RTEMS into a 162FX today (the MVME162-513). The 162FX has a |
---|
123 | * bug in the MC2 chip (revision 1) such that the SCC data register is |
---|
124 | * not accessible, it has to be accessed indirectly through the SCC |
---|
125 | * control register. |
---|
126 | */ |
---|
127 | |
---|
128 | enum {portB, portA}; |
---|
129 | |
---|
130 | extern bool char_ready(int port, char *ch); |
---|
131 | extern char char_wait(int port); |
---|
132 | extern void char_put(int port, char ch); |
---|
133 | |
---|
134 | #define TX_BUFFER_EMPTY 0x04 |
---|
135 | #define RX_DATA_AVAILABLE 0x01 |
---|
136 | #define SCC_VECTOR 0x40 |
---|
137 | |
---|
138 | typedef volatile struct { |
---|
139 | unsigned char pad1; |
---|
140 | volatile unsigned char csr; |
---|
141 | unsigned char pad2; |
---|
142 | volatile unsigned char buf; |
---|
143 | } scc_regs; |
---|
144 | |
---|
145 | #define scc ((scc_regs * const) 0xFFF45000) |
---|
146 | |
---|
147 | #define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) |
---|
148 | #define ZREAD0(port) (scc[port].csr) |
---|
149 | |
---|
150 | #define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) |
---|
151 | #define ZREADD(port) (scc[port].csr=0x08, scc[port].csr ) |
---|
152 | |
---|
153 | #define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) |
---|
154 | #define ZWRITED(port, v) (scc[port].csr = 0x08, \ |
---|
155 | scc[port].csr = (unsigned char)(v)) |
---|
156 | /*----------------------------------------------------------------*/ |
---|
157 | |
---|
158 | #ifdef M162_INIT |
---|
159 | #undef EXTERN |
---|
160 | #define EXTERN |
---|
161 | #else |
---|
162 | #undef EXTERN |
---|
163 | #define EXTERN extern |
---|
164 | #endif |
---|
165 | |
---|
166 | /* |
---|
167 | * This value is the default address location of the 162Bug vector table |
---|
168 | * and is also the default start address of the boards DRAM. This value |
---|
169 | * may be different for your specific board based on a number of factors: |
---|
170 | * |
---|
171 | * Default DRAM address: 0x00000000 |
---|
172 | * Default SRAM address: 0xFFE00000 |
---|
173 | * |
---|
174 | * o If no DRAM can be found by the 162Bug program, it will use SRAM. |
---|
175 | * o The default SRAM address may be different if SRAM mezzanine boards |
---|
176 | * are installed on the main board. |
---|
177 | * o Both the DRAM and SRAM addresses can be modified by changing the |
---|
178 | * appropriate values in NVRAM using the ENV command at the 162Bug |
---|
179 | * prompt. |
---|
180 | * |
---|
181 | * If your board has different values than the defaults, change the value |
---|
182 | * of the following define. |
---|
183 | * |
---|
184 | */ |
---|
185 | #define MOT_162BUG_VEC_ADDRESS 0x00000000 |
---|
186 | |
---|
187 | extern rtems_isr_entry M68Kvec[]; /* vector table address */ |
---|
188 | |
---|
189 | /* functions */ |
---|
190 | |
---|
191 | rtems_isr_entry set_vector( |
---|
192 | rtems_isr_entry handler, |
---|
193 | rtems_vector_number vector, |
---|
194 | int type |
---|
195 | ); |
---|
196 | |
---|
197 | /* |
---|
198 | * Prototypes for methods in the BSP that cross file boundaries. |
---|
199 | */ |
---|
200 | bool char_ready(int port, char *ch); |
---|
201 | |
---|
202 | |
---|
203 | #ifdef __cplusplus |
---|
204 | } |
---|
205 | #endif |
---|
206 | |
---|
207 | #endif |
---|