[ac7d5ef0] | 1 | /* bsp.h |
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| 2 | * |
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| 3 | * This include file contains all MVME162 board IO definitions. |
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| 4 | * |
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| 5 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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| 6 | * On-Line Applications Research Corporation (OAR). |
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| 7 | * All rights assigned to U.S. Government, 1994. |
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| 8 | * |
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| 9 | * This material may be reproduced by or for the U.S. Government pursuant |
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| 10 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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| 11 | * notice must appear in all copies of this file and its derivatives. |
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| 12 | * |
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| 13 | * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. |
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| 14 | * EISCAT Scientific Association. M.Savitski |
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| 15 | * |
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| 16 | * This material is a part of the MVME162 Board Support Package |
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| 17 | * for the RTEMS executive. Its licensing policies are those of the |
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| 18 | * RTEMS above. |
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| 19 | * |
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| 20 | * $Id$ |
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| 21 | */ |
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| 22 | |
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| 23 | #ifndef __MVME162_h |
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| 24 | #define __MVME162_h |
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| 25 | |
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| 26 | #ifdef __cplusplus |
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| 27 | extern "C" { |
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| 28 | #endif |
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| 29 | |
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| 30 | #include <rtems.h> |
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| 31 | #include <iosupp.h> |
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| 32 | |
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| 33 | /* |
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[c6fb8e90] | 34 | * Following defines must reflect the setup of the particular MVME162 |
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| 35 | */ |
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| 36 | |
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[ac7d5ef0] | 37 | #define GROUP_BASE_ADDRESS 0x0000F200 |
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[c6fb8e90] | 38 | #define BOARD_BASE_ADDRESS 0xFFFF0000 |
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| 39 | |
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[ac7d5ef0] | 40 | /* Base for local interrupters' vectors (with enable bit set) */ |
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[c6fb8e90] | 41 | |
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| 42 | #define MASK_INT 0x00800000 |
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| 43 | #define VBR0 0x6 |
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| 44 | #define VBR1 0x7 |
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| 45 | |
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[ac7d5ef0] | 46 | /* RAM limits */ |
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[c6fb8e90] | 47 | |
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[ac7d5ef0] | 48 | #define RAM_START 0x00100000 |
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| 49 | #define RAM_END 0x00200000 |
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[c6fb8e90] | 50 | |
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[ac7d5ef0] | 51 | /* |
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[c6fb8e90] | 52 | * ---------------------------------- |
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| 53 | */ |
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| 54 | |
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| 55 | typedef volatile struct lcsr_regs { |
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[ac7d5ef0] | 56 | unsigned long slave_adr[2]; |
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| 57 | unsigned long slave_trn[2]; |
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| 58 | unsigned long slave_ctl; |
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| 59 | unsigned long mastr_adr[4]; |
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| 60 | unsigned long mastr_trn; |
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| 61 | unsigned long mastr_att; |
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| 62 | unsigned long mastr_ctl; |
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| 63 | unsigned long dma_ctl_1; |
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| 64 | unsigned long dma_ctl_2; |
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| 65 | unsigned long dma_loc_cnt; |
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| 66 | unsigned long dma_vme_cnt; |
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| 67 | unsigned long dma_byte_cnt; |
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| 68 | unsigned long dma_adr_cnt; |
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| 69 | unsigned long dma_status; |
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| 70 | unsigned long to_ctl; |
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| 71 | unsigned long timer_cmp_1; |
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| 72 | unsigned long timer_cnt_1; |
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| 73 | unsigned long timer_cmp_2; |
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| 74 | unsigned long timer_cnt_2; |
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| 75 | unsigned long board_ctl; |
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| 76 | unsigned long prescaler_cnt; |
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| 77 | unsigned long intr_stat; |
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| 78 | unsigned long intr_ena; |
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| 79 | unsigned long intr_soft_set; |
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| 80 | unsigned long intr_clear; |
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| 81 | unsigned long intr_level[4]; |
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| 82 | unsigned long vector_base; |
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[c6fb8e90] | 83 | } lcsr_regs; |
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[ac7d5ef0] | 84 | |
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[c6fb8e90] | 85 | #define lcsr ((lcsr_regs * const) 0xFFF40000) |
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[ac7d5ef0] | 86 | |
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[c6fb8e90] | 87 | typedef volatile struct mcchip_regs { |
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[ac7d5ef0] | 88 | |
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[c6fb8e90] | 89 | unsigned char chipID; |
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| 90 | unsigned char chipREV; |
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| 91 | unsigned char gen_control; |
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| 92 | unsigned char vector_base; |
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| 93 | |
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| 94 | unsigned long timer_cmp_1; |
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| 95 | unsigned long timer_cnt_1; |
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| 96 | unsigned long timer_cmp_2; |
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| 97 | unsigned long timer_cnt_2; |
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| 98 | |
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| 99 | unsigned char LSB_prescaler_count; |
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| 100 | unsigned char prescaler_clock_adjust; |
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| 101 | unsigned char time_ctl_2; |
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| 102 | unsigned char time_ctl_1; |
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| 103 | |
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| 104 | unsigned char time_int_ctl_4; |
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| 105 | unsigned char time_int_ctl_3; |
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| 106 | unsigned char time_int_ctl_2; |
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| 107 | unsigned char time_int_ctl_1; |
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| 108 | |
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| 109 | unsigned char dram_err_int_ctl; |
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| 110 | unsigned char SCC_int_ctl; |
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| 111 | unsigned char time_ctl_4; |
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| 112 | unsigned char time_ctl_3; |
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| 113 | |
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| 114 | unsigned short DRAM_space_base; |
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| 115 | unsigned short SRAM_space_base; |
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| 116 | |
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| 117 | unsigned char DRAM_size; |
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| 118 | unsigned char DRAM_SRAM_opt; |
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| 119 | unsigned char SRAM_size; |
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| 120 | unsigned char reserved; |
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| 121 | |
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| 122 | unsigned char LANC_error; |
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| 123 | unsigned char reserved1; |
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| 124 | unsigned char LANC_int_ctl; |
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| 125 | unsigned char LANC_berr_ctl; |
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| 126 | |
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| 127 | unsigned char SCSI_error; |
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| 128 | unsigned char general_inputs; |
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| 129 | unsigned char MVME_162_version; |
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| 130 | unsigned char SCSI_int_ctl; |
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| 131 | |
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| 132 | unsigned long timer_cmp_3; |
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| 133 | unsigned long timer_cnt_3; |
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| 134 | unsigned long timer_cmp_4; |
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| 135 | unsigned long timer_cnt_4; |
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| 136 | |
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| 137 | unsigned char bus_clk; |
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| 138 | unsigned char PROM_acc_time_ctl; |
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| 139 | unsigned char FLASH_acc_time_ctl; |
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| 140 | unsigned char ABORT_int_ctl; |
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| 141 | |
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| 142 | unsigned char RESET_ctl; |
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| 143 | unsigned char watchdog_timer_ctl; |
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| 144 | unsigned char acc_watchdog_time_base_sel; |
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| 145 | unsigned char reserved2; |
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| 146 | |
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| 147 | unsigned char DRAM_ctl; |
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| 148 | unsigned char reserved4; |
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| 149 | unsigned char MPU_status; |
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| 150 | unsigned char reserved3; |
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| 151 | |
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| 152 | unsigned long prescaler_count; |
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| 153 | |
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| 154 | } mcchip_regs; |
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| 155 | |
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| 156 | #define mcchip ((mcchip_regs * const) 0xFFF42000) |
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| 157 | |
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| 158 | /*----------------------------------------------------------------*/ |
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| 159 | |
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| 160 | /* |
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| 161 | * SCC Z8523(0) defines and macros |
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| 162 | * ------------------------------- |
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| 163 | * Prototypes for the low-level serial io are also included here, |
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| 164 | * because such stuff is bsp-specific (yet). The function bodies |
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| 165 | * are in console.c |
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| 166 | */ |
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| 167 | |
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| 168 | enum {portB, portA}; |
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| 169 | |
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| 170 | rtems_boolean char_ready(int port, char *ch); |
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| 171 | char char_wait(int port); |
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| 172 | void char_put(int port, char ch); |
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| 173 | |
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| 174 | #define TX_BUFFER_EMPTY 0x04 |
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| 175 | #define RX_DATA_AVAILABLE 0x01 |
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| 176 | #define SCC_VECTOR 0x40 |
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| 177 | |
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| 178 | typedef volatile struct scc_regs { |
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| 179 | unsigned char pad1; |
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| 180 | volatile unsigned char csr; |
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| 181 | unsigned char pad2; |
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| 182 | volatile unsigned char buf; |
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| 183 | } scc_regs; |
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| 184 | |
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| 185 | #define scc ((scc_regs * const) 0xFFF45000) |
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| 186 | |
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| 187 | #define ZWRITE0(port, v) (scc[port].csr = (unsigned char)(v)) |
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| 188 | #define ZREAD0(port) (scc[port].csr) |
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| 189 | |
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| 190 | #define ZREAD(port, n) (ZWRITE0(port, n), (scc[port].csr)) |
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| 191 | #define ZREADD(port) (scc[port].buf) |
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| 192 | |
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| 193 | #define ZWRITE(port, n, v) (ZWRITE0(port, n), ZWRITE0(port, v)) |
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| 194 | #define ZWRITED(port, v) (scc[port].buf = (unsigned char)(v)) |
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| 195 | /*----------------------------------------------------------------*/ |
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[ac7d5ef0] | 196 | |
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| 197 | /* |
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[c6fb8e90] | 198 | * The following registers are located in the VMEbus short |
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| 199 | * IO space and respond to address modifier codes $29 and $2D. |
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| 200 | * On FORCE CPU use address gcsr_vme and device /dev/vme16d32. |
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[ac7d5ef0] | 201 | */ |
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[c6fb8e90] | 202 | typedef volatile struct gcsr_regs { |
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[ac7d5ef0] | 203 | unsigned char chip_revision; |
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| 204 | unsigned char chip_id; |
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| 205 | unsigned char lmsig; |
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| 206 | unsigned char board_scr; |
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| 207 | unsigned short gpr[6]; |
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[c6fb8e90] | 208 | } gcsr_regs; |
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| 209 | |
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| 210 | #define gcsr_vme ((gcsr_regs * const) (GROUP_BASE_ADDRESS + BOARD_BASE_ADDRESS)) |
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| 211 | #define gcsr ((gcsr_regs * const) 0xFFF40100) |
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[ac7d5ef0] | 212 | |
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| 213 | /* |
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| 214 | * Define the time limits for RTEMS Test Suite test durations. |
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| 215 | * Long test and short test duration limits are provided. These |
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| 216 | * values are in seconds and need to be converted to ticks for the |
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| 217 | * application. |
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| 218 | * |
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| 219 | */ |
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| 220 | |
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| 221 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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| 222 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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| 223 | |
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| 224 | /* |
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[c6fb8e90] | 225 | * Define the interrupt mechanism for Time Test 27 |
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[ac7d5ef0] | 226 | * |
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[c6fb8e90] | 227 | * NOTE: We use software interrupt 0 |
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[ac7d5ef0] | 228 | */ |
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| 229 | |
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| 230 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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| 231 | |
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[c6fb8e90] | 232 | #define Install_tm27_vector( handler ) \ |
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| 233 | set_vector( (handler), VBR1 * 0x10 + 0x8, 1 ); \ |
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| 234 | lcsr->intr_level[2] |= 3; \ |
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| 235 | lcsr->intr_ena |= 0x100; |
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[ac7d5ef0] | 236 | |
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[c6fb8e90] | 237 | #define Cause_tm27_intr() lcsr->intr_soft_set |= 0x100 |
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[ac7d5ef0] | 238 | |
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[c6fb8e90] | 239 | #define Clear_tm27_intr() lcsr->intr_clear |= 0x100 |
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[ac7d5ef0] | 240 | |
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| 241 | #define Lower_tm27_intr() |
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| 242 | |
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[c6fb8e90] | 243 | #ifdef M162_INIT |
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[ac7d5ef0] | 244 | #undef EXTERN |
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| 245 | #define EXTERN |
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| 246 | #else |
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| 247 | #undef EXTERN |
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| 248 | #define EXTERN extern |
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| 249 | #endif |
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| 250 | |
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| 251 | /* miscellaneous stuff assumed to exist */ |
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| 252 | |
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| 253 | extern rtems_configuration_table BSP_Configuration; |
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| 254 | |
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[497428a2] | 255 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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[ac7d5ef0] | 256 | |
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| 257 | /* functions */ |
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| 258 | |
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| 259 | void bsp_cleanup( void ); |
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| 260 | |
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[497428a2] | 261 | m68k_isr_entry set_vector( |
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[ac7d5ef0] | 262 | rtems_isr_entry handler, |
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| 263 | rtems_vector_number vector, |
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| 264 | int type |
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| 265 | ); |
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| 266 | |
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| 267 | #ifdef __cplusplus |
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| 268 | } |
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| 269 | #endif |
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| 270 | |
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| 271 | #endif |
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| 272 | /* end of include file */ |
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