[ac7d5ef0] | 1 | /* Clock_init() |
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| 2 | * |
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| 3 | * This routine initializes the Tick Timer 2 on the MVME162 board. |
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| 4 | * The tick frequency is 1 millisecond. |
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| 5 | * |
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| 6 | * Input parameters: NONE |
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| 7 | * |
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| 8 | * Output parameters: NONE |
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| 9 | * |
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[08311cc3] | 10 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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[98e4ebf5] | 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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[f4fe0092] | 15 | * http://www.rtems.com/license/LICENSE. |
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[ac7d5ef0] | 16 | * |
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| 17 | * Modifications of respective RTEMS file: COPYRIGHT (c) 1994. |
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| 18 | * EISCAT Scientific Association. M.Savitski |
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| 19 | * |
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| 20 | * This material is a part of the MVME162 Board Support Package |
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| 21 | * for the RTEMS executive. Its licensing policies are those of the |
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| 22 | * RTEMS above. |
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| 23 | * |
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| 24 | * $Id$ |
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| 25 | */ |
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| 26 | |
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| 27 | #include <stdlib.h> |
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| 28 | |
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| 29 | #include <bsp.h> |
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[3a4ae6c] | 30 | #include <rtems/libio.h> |
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[ac7d5ef0] | 31 | |
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| 32 | #define MS_COUNT 1000 /* T2's countdown constant (1 ms) */ |
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[c6fb8e90] | 33 | #define CLOCK_INT_LEVEL 6 /* T2's interrupt level */ |
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[ac7d5ef0] | 34 | |
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[629e12a] | 35 | uint32_t Clock_isrs; /* ISRs until next tick */ |
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| 36 | volatile uint32_t Clock_driver_ticks; /* ticks since initialization */ |
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[ac7d5ef0] | 37 | rtems_isr_entry Old_ticker; |
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| 38 | |
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[3a4ae6c] | 39 | void Clock_exit( void ); |
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[6128a4a] | 40 | |
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[3a4ae6c] | 41 | #define CLOCK_VECTOR (VBR0 * 0x10 + 0x9) |
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| 42 | /* |
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| 43 | * These are set by clock driver during its init |
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| 44 | */ |
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[6128a4a] | 45 | |
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[3a4ae6c] | 46 | rtems_device_major_number rtems_clock_major = ~0; |
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| 47 | rtems_device_minor_number rtems_clock_minor; |
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[6128a4a] | 48 | |
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[3a4ae6c] | 49 | /* |
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| 50 | * ISR Handler |
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| 51 | */ |
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| 52 | |
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| 53 | rtems_isr Clock_isr(rtems_vector_number vector) |
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[ac7d5ef0] | 54 | { |
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[3a4ae6c] | 55 | Clock_driver_ticks += 1; |
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| 56 | lcsr->timer_cnt_2 = 0; /* clear counter */ |
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| 57 | lcsr->intr_clear |= 0x02000000; |
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[ac7d5ef0] | 58 | |
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[3a4ae6c] | 59 | if ( Clock_isrs == 1 ) { |
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| 60 | rtems_clock_tick(); |
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[12bd47e] | 61 | Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000; |
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[3a4ae6c] | 62 | } |
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[6128a4a] | 63 | else |
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[3a4ae6c] | 64 | Clock_isrs -= 1; |
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[ac7d5ef0] | 65 | } |
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| 66 | |
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[c6fb8e90] | 67 | void Install_clock(rtems_isr_entry clock_isr ) |
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[ac7d5ef0] | 68 | { |
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| 69 | |
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| 70 | Clock_driver_ticks = 0; |
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[12bd47e] | 71 | Clock_isrs = rtems_configuration_get_microseconds_per_tick() / 1000; |
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[ac7d5ef0] | 72 | |
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[0dd1d44] | 73 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); |
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| 74 | lcsr->vector_base |= MASK_INT; /* unmask VMEchip2 interrupts */ |
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| 75 | lcsr->to_ctl = 0xE7; /* prescaler to 1 MHz (see Appendix A1) */ |
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| 76 | lcsr->timer_cmp_2 = MS_COUNT; |
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| 77 | lcsr->timer_cnt_2 = 0; /* clear counter */ |
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| 78 | lcsr->board_ctl |= 0x700; /* increment, reset-on-compare, and */ |
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| 79 | /* clear-overflow-cnt */ |
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[ac7d5ef0] | 80 | |
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[0dd1d44] | 81 | lcsr->intr_level[0] |= CLOCK_INT_LEVEL * 0x10; /* set int level */ |
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| 82 | lcsr->intr_ena |= 0x02000000; /* enable tick timer 2 interrupt */ |
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[ac7d5ef0] | 83 | |
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[0dd1d44] | 84 | atexit( Clock_exit ); |
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[3a4ae6c] | 85 | } |
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[ac7d5ef0] | 86 | |
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| 87 | void Clock_exit( void ) |
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| 88 | { |
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| 89 | /* Dummy for now. See other m68k BSP's for code examples */ |
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| 90 | } |
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[3a4ae6c] | 91 | |
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| 92 | rtems_device_driver Clock_initialize( |
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| 93 | rtems_device_major_number major, |
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| 94 | rtems_device_minor_number minor, |
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| 95 | void *pargp |
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| 96 | ) |
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| 97 | { |
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| 98 | Install_clock( Clock_isr ); |
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[6128a4a] | 99 | |
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[3a4ae6c] | 100 | /* |
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| 101 | * make major/minor avail to others such as shared memory driver |
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| 102 | */ |
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[6128a4a] | 103 | |
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[3a4ae6c] | 104 | rtems_clock_major = major; |
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| 105 | rtems_clock_minor = minor; |
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[6128a4a] | 106 | |
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[3a4ae6c] | 107 | return RTEMS_SUCCESSFUL; |
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| 108 | } |
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