source: rtems/c/src/lib/libbsp/m68k/mvme147s/include/bsp.h @ d2632274

4.104.114.84.95
Last change on this file since d2632274 was 98e4ebf, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 8, 1997 at 3:45:54 PM

Fixed typo in the pointer to the license terms.

  • Property mode set to 100644
File size: 7.7 KB
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1/*  bsp.h
2 *
3 *  This include file contains all MVME147 board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989-1997.
6 *  On-Line Applications Research Corporation (OAR).
7 *  Copyright assigned to U.S. Government, 1994.
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  MVME147 port for TNI - Telecom Bretagne
14 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
15 *  May 1996
16 *
17 *  $Id$
18 */
19
20#ifndef __MVME147_h
21#define __MVME147_h
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems.h>
28#include <clockdrv.h>
29#include <console.h>
30#include <iosupp.h>
31
32/* Constants */
33
34#define RAM_START 0x00007000
35#define RAM_END   0x003e0000
36#define DRAM_END  0x00400000
37  /* We leave 128k for the shared memory */
38
39  /* MVME 147 Peripheral controller chip
40     see MVME147/D1, 3.4 */
41
42struct pcc_map {
43  /* 32 bit registers */
44  rtems_unsigned32 dma_table_address;            /* 0xfffe1000 */
45  rtems_unsigned32 dma_data_address;             /* 0xfffe1004 */
46  rtems_unsigned32 dma_bytecount;                /* 0xfffe1008 */
47  rtems_unsigned32 dma_data_holding;             /* 0xfffe100c */
48
49  /* 16 bit registers */
50  rtems_unsigned16 timer1_preload;               /* 0xfffe1010 */
51  rtems_unsigned16 timer1_count;                 /* 0xfffe1012 */
52  rtems_unsigned16 timer2_preload;               /* 0xfffe1014 */
53  rtems_unsigned16 timer2_count;                 /* 0xfffe1016 */
54
55  /* 8 bit registers */
56  rtems_unsigned8 timer1_int_control;            /* 0xfffe1018 */
57  rtems_unsigned8 timer1_control;                /* 0xfffe1019 */
58  rtems_unsigned8 timer2_int_control;            /* 0xfffe101a */
59  rtems_unsigned8 timer2_control;                /* 0xfffe101b */
60
61  rtems_unsigned8 acfail_int_control;            /* 0xfffe101c */
62  rtems_unsigned8 watchdog_control;              /* 0xfffe101d */
63
64  rtems_unsigned8 printer_int_control;           /* 0xfffe101e */
65  rtems_unsigned8 printer_control;               /* 0xfffe102f */
66
67  rtems_unsigned8 dma_int_control;               /* 0xfffe1020 */
68  rtems_unsigned8 dma_control;                   /* 0xfffe1021 */
69  rtems_unsigned8 bus_error_int_control;         /* 0xfffe1022 */
70  rtems_unsigned8 dma_status;                    /* 0xfffe1023 */
71  rtems_unsigned8 abort_int_control;             /* 0xfffe1024 */
72  rtems_unsigned8 table_address_function_code;   /* 0xfffe1025 */
73  rtems_unsigned8 serial_port_int_control;       /* 0xfffe1026 */
74  rtems_unsigned8 general_purpose_control;       /* 0xfffe1027 */
75  rtems_unsigned8 lan_int_control;               /* 0xfffe1028 */
76  rtems_unsigned8 general_purpose_status;        /* 0xfffe1029 */
77  rtems_unsigned8 scsi_port_int_control;         /* 0xfffe102a */
78  rtems_unsigned8 slave_base_address;            /* 0xfffe102b */
79  rtems_unsigned8 software_int_1_control;        /* 0xfffe102c */
80  rtems_unsigned8 int_base_vector;               /* 0xfffe102d */
81  rtems_unsigned8 software_int_2_control;        /* 0xfffe102e */
82  rtems_unsigned8 revision_level;                /* 0xfffe102f */
83};
84
85#define pcc      ((volatile struct pcc_map * const) 0xfffe1000)
86
87/* VME chip configuration registers */
88
89struct vme_lcsr_map {
90  rtems_unsigned8 unused_1;
91  rtems_unsigned8 system_controller;             /* 0xfffe2001 */
92  rtems_unsigned8 unused_2;
93  rtems_unsigned8 vme_bus_requester;             /* 0xfffe2003 */
94  rtems_unsigned8 unused_3;
95  rtems_unsigned8 master_configuration;          /* 0xfffe2005 */
96  rtems_unsigned8 unused_4;
97  rtems_unsigned8 slave_configuration;           /* 0xfffe2007 */
98  rtems_unsigned8 unused_5;
99  rtems_unsigned8 timer_configuration;           /* 0xfffe2009 */
100  rtems_unsigned8 unused_6;
101  rtems_unsigned8 slave_address_modifier;        /* 0xfffe200b */
102  rtems_unsigned8 unused_7;
103  rtems_unsigned8 master_address_modifier;       /* 0xfffe200d */
104  rtems_unsigned8 unused_8;
105  rtems_unsigned8 interrupt_handler_mask;        /* 0xfffe200f */
106  rtems_unsigned8 unused_9;
107  rtems_unsigned8 utility_interrupt_mask;        /* 0xfffe2011 */
108  rtems_unsigned8 unused_10;
109  rtems_unsigned8 utility_interrupt_vector;      /* 0xfffe2013 */
110  rtems_unsigned8 unused_11;
111  rtems_unsigned8 interrupt_request;             /* 0xfffe2015 */
112  rtems_unsigned8 unused_12;
113  rtems_unsigned8 vme_bus_status_id;             /* 0xfffe2017 */
114  rtems_unsigned8 unused_13;
115  rtems_unsigned8 bus_error_status;              /* 0xfffe2019 */
116  rtems_unsigned8 unused_14;
117  rtems_unsigned8 gcsr_base_address;             /* 0xfffe201b */
118};
119
120#define vme_lcsr      ((volatile struct vme_lcsr_map * const) 0xfffe2000)
121
122
123struct vme_gcsr_map {
124  rtems_unsigned8 unused_1;
125  rtems_unsigned8 global_0;                      /* 0xfffe2021 */
126  rtems_unsigned8 unused_2;
127  rtems_unsigned8 global_1;                      /* 0xfffe2023 */
128  rtems_unsigned8 unused_3;
129  rtems_unsigned8 board_identification;          /* 0xfffe2025 */
130  rtems_unsigned8 unused_4;
131  rtems_unsigned8 general_purpose_0;             /* 0xfffe2027 */
132  rtems_unsigned8 unused_5;
133  rtems_unsigned8 general_purpose_1;             /* 0xfffe2029 */
134  rtems_unsigned8 unused_6;
135  rtems_unsigned8 general_purpose_2;             /* 0xfffe202b */
136  rtems_unsigned8 unused_7;
137  rtems_unsigned8 general_purpose_3;             /* 0xfffe202d */
138  rtems_unsigned8 unused_8;
139  rtems_unsigned8 general_purpose_4;             /* 0xfffe202f */
140};
141
142#define vme_gcsr      ((volatile struct vme_gcsr_map * const) 0xfffe2020)
143
144
145
146#define z8530 0xfffe3001
147
148
149/* interrupt vectors - see MVME147/D1 4.14 */
150#define PCC_BASE_VECTOR        0x40 /* First user int */
151#define SCC_VECTOR             PCC_BASE_VECTOR+3
152#define TIMER_1_VECTOR         PCC_BASE_VECTOR+8
153#define TIMER_2_VECTOR         PCC_BASE_VECTOR+9 
154#define SOFT_1_VECTOR          PCC_BASE_VECTOR+10
155#define SOFT_2_VECTOR          PCC_BASE_VECTOR+11
156
157#define VME_BASE_VECTOR        0x50
158#define VME_SIGLP_VECTOR       VME_BASE_VECTOR+1
159
160#define USE_CHANNEL_A   1                /* 1 = use channel A for console */
161#define USE_CHANNEL_B   0                /* 1 = use channel B for console */
162
163#if (USE_CHANNEL_A == 1)
164#define CONSOLE_CONTROL  0xfffe3002
165#define CONSOLE_DATA     0xfffe3003
166#elif (USE_CHANNEL_B == 1)
167#define CONSOLE_CONTROL  0xfffe3000
168#define CONSOLE_DATA     0xfffe3001
169#endif
170
171
172
173#define FOREVER       1                  /* infinite loop */
174
175#ifdef M147_INIT
176#undef EXTERN
177#define EXTERN
178#else
179#undef EXTERN
180#define EXTERN extern
181#endif
182
183/*
184 *  Define the time limits for RTEMS Test Suite test durations.
185 *  Long test and short test duration limits are provided.  These
186 *  values are in seconds and need to be converted to ticks for the
187 *  application.
188 *
189 */
190
191#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
192#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
193
194/*
195 *  Define the interrupt mechanism for Time Test 27
196 *
197 *  NOTE: Use the MPCSR vector for the MVME147
198 */
199
200#define MUST_WAIT_FOR_INTERRUPT 0
201
202#define Install_tm27_vector( handler ) set_vector( (handler), \
203                                                   SOFT_1_VECTOR, 1 )
204
205#define Cause_tm27_intr()  pcc->software_int_1_control = 0x0c
206  /* generate level 4 sotware int. */
207
208#define Clear_tm27_intr()  pcc->software_int_1_control = 0x00
209
210#define Lower_tm27_intr()
211
212
213/* miscellaneous stuff assumed to exist */
214
215extern rtems_configuration_table BSP_Configuration;
216
217extern m68k_isr_entry M68Kvec[];   /* vector table address */
218
219/*
220 *  Device Driver Table Entries
221 */
222
223/*
224 * NOTE: Use the standard Console driver entry
225 */
226 
227/*
228 * NOTE: Use the standard Clock driver entry
229 */
230
231/*
232 * How many libio files we want
233 */
234
235#define BSP_LIBIO_MAX_FDS       20
236
237/* functions */
238
239void bsp_cleanup( void );
240
241m68k_isr_entry set_vector(
242  rtems_isr_entry     handler,
243  rtems_vector_number vector,
244  int                 type
245);
246
247#ifdef __cplusplus
248}
249#endif
250
251#endif
252/* end of include file */
253
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