source: rtems/c/src/lib/libbsp/m68k/mvme147s/include/bsp.h @ c4d92216

4.104.114.84.95
Last change on this file since c4d92216 was c4d92216, checked in by Joel Sherrill <joel.sherrill@…>, on 06/18/01 at 16:54:47

2001-05-26 Ralf Corsepius <corsepiu@…>

  • configure.in: Add bspopts.h.
  • include/.cvsignore: Add bspopts.h*, stamp-h*.
  • include/Makefile.am: Use *_HEADERS instead of *H_FILES.
  • include/bsp.h: Include bspopts.h.
  • Property mode set to 100644
File size: 7.9 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all MVME147 board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.OARcorp.com/rtems/license.html.
11 *
12 *  MVME147 port for TNI - Telecom Bretagne
13 *  by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr)
14 *  May 1996
15 *
16 *  $Id$
17 */
18
19#ifndef __MVME147_h
20#define __MVME147_h
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <bspopts.h>
27
28#include <rtems.h>
29#include <clockdrv.h>
30#include <console.h>
31#include <iosupp.h>
32
33/*
34 *  confdefs.h overrides for this BSP:
35 *   - number of termios serial ports (defaults to 1)
36 *   - Interrupt stack space is not minimum if defined.
37 */
38
39/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
40#define CONFIGURE_INTERRUPT_STACK_MEMORY  (4 * 1024)
41
42/* Constants */
43
44#define RAM_START 0x00007000
45#define RAM_END   0x003e0000
46#define DRAM_END  0x00400000
47  /* We leave 128k for the shared memory */
48
49  /* MVME 147 Peripheral controller chip
50     see MVME147/D1, 3.4 */
51
52struct pcc_map {
53  /* 32 bit registers */
54  rtems_unsigned32 dma_table_address;            /* 0xfffe1000 */
55  rtems_unsigned32 dma_data_address;             /* 0xfffe1004 */
56  rtems_unsigned32 dma_bytecount;                /* 0xfffe1008 */
57  rtems_unsigned32 dma_data_holding;             /* 0xfffe100c */
58
59  /* 16 bit registers */
60  rtems_unsigned16 timer1_preload;               /* 0xfffe1010 */
61  rtems_unsigned16 timer1_count;                 /* 0xfffe1012 */
62  rtems_unsigned16 timer2_preload;               /* 0xfffe1014 */
63  rtems_unsigned16 timer2_count;                 /* 0xfffe1016 */
64
65  /* 8 bit registers */
66  rtems_unsigned8 timer1_int_control;            /* 0xfffe1018 */
67  rtems_unsigned8 timer1_control;                /* 0xfffe1019 */
68  rtems_unsigned8 timer2_int_control;            /* 0xfffe101a */
69  rtems_unsigned8 timer2_control;                /* 0xfffe101b */
70
71  rtems_unsigned8 acfail_int_control;            /* 0xfffe101c */
72  rtems_unsigned8 watchdog_control;              /* 0xfffe101d */
73
74  rtems_unsigned8 printer_int_control;           /* 0xfffe101e */
75  rtems_unsigned8 printer_control;               /* 0xfffe102f */
76
77  rtems_unsigned8 dma_int_control;               /* 0xfffe1020 */
78  rtems_unsigned8 dma_control;                   /* 0xfffe1021 */
79  rtems_unsigned8 bus_error_int_control;         /* 0xfffe1022 */
80  rtems_unsigned8 dma_status;                    /* 0xfffe1023 */
81  rtems_unsigned8 abort_int_control;             /* 0xfffe1024 */
82  rtems_unsigned8 table_address_function_code;   /* 0xfffe1025 */
83  rtems_unsigned8 serial_port_int_control;       /* 0xfffe1026 */
84  rtems_unsigned8 general_purpose_control;       /* 0xfffe1027 */
85  rtems_unsigned8 lan_int_control;               /* 0xfffe1028 */
86  rtems_unsigned8 general_purpose_status;        /* 0xfffe1029 */
87  rtems_unsigned8 scsi_port_int_control;         /* 0xfffe102a */
88  rtems_unsigned8 slave_base_address;            /* 0xfffe102b */
89  rtems_unsigned8 software_int_1_control;        /* 0xfffe102c */
90  rtems_unsigned8 int_base_vector;               /* 0xfffe102d */
91  rtems_unsigned8 software_int_2_control;        /* 0xfffe102e */
92  rtems_unsigned8 revision_level;                /* 0xfffe102f */
93};
94
95#define pcc      ((volatile struct pcc_map * const) 0xfffe1000)
96
97/* VME chip configuration registers */
98
99struct vme_lcsr_map {
100  rtems_unsigned8 unused_1;
101  rtems_unsigned8 system_controller;             /* 0xfffe2001 */
102  rtems_unsigned8 unused_2;
103  rtems_unsigned8 vme_bus_requester;             /* 0xfffe2003 */
104  rtems_unsigned8 unused_3;
105  rtems_unsigned8 master_configuration;          /* 0xfffe2005 */
106  rtems_unsigned8 unused_4;
107  rtems_unsigned8 slave_configuration;           /* 0xfffe2007 */
108  rtems_unsigned8 unused_5;
109  rtems_unsigned8 timer_configuration;           /* 0xfffe2009 */
110  rtems_unsigned8 unused_6;
111  rtems_unsigned8 slave_address_modifier;        /* 0xfffe200b */
112  rtems_unsigned8 unused_7;
113  rtems_unsigned8 master_address_modifier;       /* 0xfffe200d */
114  rtems_unsigned8 unused_8;
115  rtems_unsigned8 interrupt_handler_mask;        /* 0xfffe200f */
116  rtems_unsigned8 unused_9;
117  rtems_unsigned8 utility_interrupt_mask;        /* 0xfffe2011 */
118  rtems_unsigned8 unused_10;
119  rtems_unsigned8 utility_interrupt_vector;      /* 0xfffe2013 */
120  rtems_unsigned8 unused_11;
121  rtems_unsigned8 interrupt_request;             /* 0xfffe2015 */
122  rtems_unsigned8 unused_12;
123  rtems_unsigned8 vme_bus_status_id;             /* 0xfffe2017 */
124  rtems_unsigned8 unused_13;
125  rtems_unsigned8 bus_error_status;              /* 0xfffe2019 */
126  rtems_unsigned8 unused_14;
127  rtems_unsigned8 gcsr_base_address;             /* 0xfffe201b */
128};
129
130#define vme_lcsr      ((volatile struct vme_lcsr_map * const) 0xfffe2000)
131
132
133struct vme_gcsr_map {
134  rtems_unsigned8 unused_1;
135  rtems_unsigned8 global_0;                      /* 0xfffe2021 */
136  rtems_unsigned8 unused_2;
137  rtems_unsigned8 global_1;                      /* 0xfffe2023 */
138  rtems_unsigned8 unused_3;
139  rtems_unsigned8 board_identification;          /* 0xfffe2025 */
140  rtems_unsigned8 unused_4;
141  rtems_unsigned8 general_purpose_0;             /* 0xfffe2027 */
142  rtems_unsigned8 unused_5;
143  rtems_unsigned8 general_purpose_1;             /* 0xfffe2029 */
144  rtems_unsigned8 unused_6;
145  rtems_unsigned8 general_purpose_2;             /* 0xfffe202b */
146  rtems_unsigned8 unused_7;
147  rtems_unsigned8 general_purpose_3;             /* 0xfffe202d */
148  rtems_unsigned8 unused_8;
149  rtems_unsigned8 general_purpose_4;             /* 0xfffe202f */
150};
151
152#define vme_gcsr      ((volatile struct vme_gcsr_map * const) 0xfffe2020)
153
154
155
156#define z8530 0xfffe3001
157
158
159/* interrupt vectors - see MVME147/D1 4.14 */
160#define PCC_BASE_VECTOR        0x40 /* First user int */
161#define SCC_VECTOR             PCC_BASE_VECTOR+3
162#define TIMER_1_VECTOR         PCC_BASE_VECTOR+8
163#define TIMER_2_VECTOR         PCC_BASE_VECTOR+9 
164#define SOFT_1_VECTOR          PCC_BASE_VECTOR+10
165#define SOFT_2_VECTOR          PCC_BASE_VECTOR+11
166
167#define VME_BASE_VECTOR        0x50
168#define VME_SIGLP_VECTOR       VME_BASE_VECTOR+1
169
170#define USE_CHANNEL_A   1                /* 1 = use channel A for console */
171#define USE_CHANNEL_B   0                /* 1 = use channel B for console */
172
173#if (USE_CHANNEL_A == 1)
174#define CONSOLE_CONTROL  0xfffe3002
175#define CONSOLE_DATA     0xfffe3003
176#elif (USE_CHANNEL_B == 1)
177#define CONSOLE_CONTROL  0xfffe3000
178#define CONSOLE_DATA     0xfffe3001
179#endif
180
181
182
183#define FOREVER       1                  /* infinite loop */
184
185#ifdef M147_INIT
186#undef EXTERN
187#define EXTERN
188#else
189#undef EXTERN
190#define EXTERN extern
191#endif
192
193/*
194 *  Define the time limits for RTEMS Test Suite test durations.
195 *  Long test and short test duration limits are provided.  These
196 *  values are in seconds and need to be converted to ticks for the
197 *  application.
198 *
199 */
200
201#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
202#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
203
204/*
205 *  Define the interrupt mechanism for Time Test 27
206 *
207 *  NOTE: Use the MPCSR vector for the MVME147
208 */
209
210#define MUST_WAIT_FOR_INTERRUPT 0
211
212#define Install_tm27_vector( handler ) set_vector( (handler), \
213                                                   SOFT_1_VECTOR, 1 )
214
215#define Cause_tm27_intr()  pcc->software_int_1_control = 0x0c
216  /* generate level 4 sotware int. */
217
218#define Clear_tm27_intr()  pcc->software_int_1_control = 0x00
219
220#define Lower_tm27_intr()
221
222
223/* miscellaneous stuff assumed to exist */
224
225extern rtems_configuration_table BSP_Configuration;
226
227extern m68k_isr_entry M68Kvec[];   /* vector table address */
228
229/*
230 *  Device Driver Table Entries
231 */
232
233/*
234 * NOTE: Use the standard Console driver entry
235 */
236 
237/*
238 * NOTE: Use the standard Clock driver entry
239 */
240
241/* functions */
242
243void bsp_cleanup( void );
244
245m68k_isr_entry set_vector(
246  rtems_isr_entry     handler,
247  rtems_vector_number vector,
248  int                 type
249);
250
251#ifdef __cplusplus
252}
253#endif
254
255#endif
256/* end of include file */
257
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