1 | /* bsp.h |
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2 | * |
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3 | * This include file contains all MVME147 board IO definitions. |
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4 | * |
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5 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * All rights assigned to U.S. Government, 1994. |
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8 | * |
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9 | * This material may be reproduced by or for the U.S. Government pursuant |
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10 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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11 | * notice must appear in all copies of this file and its derivatives. |
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12 | * |
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13 | * MVME147 port for TNI - Telecom Bretagne |
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14 | * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) |
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15 | * May 1996 |
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16 | * |
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17 | * $Id$ |
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18 | */ |
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19 | |
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20 | #ifndef __MVME147_h |
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21 | #define __MVME147_h |
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22 | |
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23 | #ifdef __cplusplus |
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24 | extern "C" { |
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25 | #endif |
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26 | |
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27 | #include <rtems.h> |
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28 | #include <clockdrv.h> |
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29 | #include <console.h> |
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30 | #include <iosupp.h> |
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31 | |
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32 | /* Constants */ |
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33 | |
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34 | #define RAM_START 0x00007000 |
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35 | #define RAM_END 0x003e0000 |
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36 | #define DRAM_END 0x00400000 |
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37 | /* We leave 128k for the shared memory */ |
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38 | |
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39 | /* MVME 147 Peripheral controller chip |
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40 | see MVME147/D1, 3.4 */ |
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41 | |
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42 | struct pcc_map { |
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43 | /* 32 bit registers */ |
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44 | rtems_unsigned32 dma_table_address; /* 0xfffe1000 */ |
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45 | rtems_unsigned32 dma_data_address; /* 0xfffe1004 */ |
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46 | rtems_unsigned32 dma_bytecount; /* 0xfffe1008 */ |
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47 | rtems_unsigned32 dma_data_holding; /* 0xfffe100c */ |
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48 | |
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49 | /* 16 bit registers */ |
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50 | rtems_unsigned16 timer1_preload; /* 0xfffe1010 */ |
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51 | rtems_unsigned16 timer1_count; /* 0xfffe1012 */ |
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52 | rtems_unsigned16 timer2_preload; /* 0xfffe1014 */ |
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53 | rtems_unsigned16 timer2_count; /* 0xfffe1016 */ |
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54 | |
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55 | /* 8 bit registers */ |
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56 | rtems_unsigned8 timer1_int_control; /* 0xfffe1018 */ |
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57 | rtems_unsigned8 timer1_control; /* 0xfffe1019 */ |
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58 | rtems_unsigned8 timer2_int_control; /* 0xfffe101a */ |
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59 | rtems_unsigned8 timer2_control; /* 0xfffe101b */ |
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60 | |
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61 | rtems_unsigned8 acfail_int_control; /* 0xfffe101c */ |
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62 | rtems_unsigned8 watchdog_control; /* 0xfffe101d */ |
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63 | |
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64 | rtems_unsigned8 printer_int_control; /* 0xfffe101e */ |
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65 | rtems_unsigned8 printer_control; /* 0xfffe102f */ |
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66 | |
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67 | rtems_unsigned8 dma_int_control; /* 0xfffe1020 */ |
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68 | rtems_unsigned8 dma_control; /* 0xfffe1021 */ |
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69 | rtems_unsigned8 bus_error_int_control; /* 0xfffe1022 */ |
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70 | rtems_unsigned8 dma_status; /* 0xfffe1023 */ |
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71 | rtems_unsigned8 abort_int_control; /* 0xfffe1024 */ |
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72 | rtems_unsigned8 table_address_function_code; /* 0xfffe1025 */ |
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73 | rtems_unsigned8 serial_port_int_control; /* 0xfffe1026 */ |
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74 | rtems_unsigned8 general_purpose_control; /* 0xfffe1027 */ |
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75 | rtems_unsigned8 lan_int_control; /* 0xfffe1028 */ |
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76 | rtems_unsigned8 general_purpose_status; /* 0xfffe1029 */ |
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77 | rtems_unsigned8 scsi_port_int_control; /* 0xfffe102a */ |
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78 | rtems_unsigned8 slave_base_address; /* 0xfffe102b */ |
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79 | rtems_unsigned8 software_int_1_control; /* 0xfffe102c */ |
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80 | rtems_unsigned8 int_base_vector; /* 0xfffe102d */ |
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81 | rtems_unsigned8 software_int_2_control; /* 0xfffe102e */ |
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82 | rtems_unsigned8 revision_level; /* 0xfffe102f */ |
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83 | }; |
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84 | |
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85 | #define pcc ((volatile struct pcc_map * const) 0xfffe1000) |
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86 | |
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87 | /* VME chip configuration registers */ |
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88 | |
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89 | struct vme_lcsr_map { |
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90 | rtems_unsigned8 unused_1; |
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91 | rtems_unsigned8 system_controller; /* 0xfffe2001 */ |
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92 | rtems_unsigned8 unused_2; |
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93 | rtems_unsigned8 vme_bus_requester; /* 0xfffe2003 */ |
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94 | rtems_unsigned8 unused_3; |
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95 | rtems_unsigned8 master_configuration; /* 0xfffe2005 */ |
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96 | rtems_unsigned8 unused_4; |
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97 | rtems_unsigned8 slave_configuration; /* 0xfffe2007 */ |
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98 | rtems_unsigned8 unused_5; |
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99 | rtems_unsigned8 timer_configuration; /* 0xfffe2009 */ |
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100 | rtems_unsigned8 unused_6; |
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101 | rtems_unsigned8 slave_address_modifier; /* 0xfffe200b */ |
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102 | rtems_unsigned8 unused_7; |
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103 | rtems_unsigned8 master_address_modifier; /* 0xfffe200d */ |
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104 | rtems_unsigned8 unused_8; |
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105 | rtems_unsigned8 interrupt_handler_mask; /* 0xfffe200f */ |
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106 | rtems_unsigned8 unused_9; |
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107 | rtems_unsigned8 utility_interrupt_mask; /* 0xfffe2011 */ |
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108 | rtems_unsigned8 unused_10; |
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109 | rtems_unsigned8 utility_interrupt_vector; /* 0xfffe2013 */ |
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110 | rtems_unsigned8 unused_11; |
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111 | rtems_unsigned8 interrupt_request; /* 0xfffe2015 */ |
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112 | rtems_unsigned8 unused_12; |
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113 | rtems_unsigned8 vme_bus_status_id; /* 0xfffe2017 */ |
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114 | rtems_unsigned8 unused_13; |
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115 | rtems_unsigned8 bus_error_status; /* 0xfffe2019 */ |
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116 | rtems_unsigned8 unused_14; |
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117 | rtems_unsigned8 gcsr_base_address; /* 0xfffe201b */ |
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118 | }; |
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119 | |
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120 | #define vme_lcsr ((volatile struct vme_lcsr_map * const) 0xfffe2000) |
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121 | |
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122 | |
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123 | struct vme_gcsr_map { |
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124 | rtems_unsigned8 unused_1; |
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125 | rtems_unsigned8 global_0; /* 0xfffe2021 */ |
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126 | rtems_unsigned8 unused_2; |
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127 | rtems_unsigned8 global_1; /* 0xfffe2023 */ |
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128 | rtems_unsigned8 unused_3; |
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129 | rtems_unsigned8 board_identification; /* 0xfffe2025 */ |
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130 | rtems_unsigned8 unused_4; |
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131 | rtems_unsigned8 general_purpose_0; /* 0xfffe2027 */ |
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132 | rtems_unsigned8 unused_5; |
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133 | rtems_unsigned8 general_purpose_1; /* 0xfffe2029 */ |
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134 | rtems_unsigned8 unused_6; |
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135 | rtems_unsigned8 general_purpose_2; /* 0xfffe202b */ |
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136 | rtems_unsigned8 unused_7; |
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137 | rtems_unsigned8 general_purpose_3; /* 0xfffe202d */ |
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138 | rtems_unsigned8 unused_8; |
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139 | rtems_unsigned8 general_purpose_4; /* 0xfffe202f */ |
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140 | }; |
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141 | |
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142 | #define vme_gcsr ((volatile struct vme_gcsr_map * const) 0xfffe2020) |
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143 | |
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144 | |
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145 | |
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146 | #define z8530 0xfffe3001 |
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147 | |
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148 | |
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149 | /* interrupt vectors - see MVME147/D1 4.14 */ |
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150 | #define PCC_BASE_VECTOR 0x40 /* First user int */ |
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151 | #define SCC_VECTOR PCC_BASE_VECTOR+3 |
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152 | #define TIMER_1_VECTOR PCC_BASE_VECTOR+8 |
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153 | #define TIMER_2_VECTOR PCC_BASE_VECTOR+9 |
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154 | #define SOFT_1_VECTOR PCC_BASE_VECTOR+10 |
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155 | #define SOFT_2_VECTOR PCC_BASE_VECTOR+11 |
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156 | |
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157 | #define VME_BASE_VECTOR 0x50 |
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158 | #define VME_SIGLP_VECTOR VME_BASE_VECTOR+1 |
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159 | |
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160 | #define USE_CHANNEL_A 1 /* 1 = use channel A for console */ |
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161 | #define USE_CHANNEL_B 0 /* 1 = use channel B for console */ |
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162 | |
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163 | #if (USE_CHANNEL_A == 1) |
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164 | #define CONSOLE_CONTROL 0xfffe3002 |
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165 | #define CONSOLE_DATA 0xfffe3003 |
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166 | #elif (USE_CHANNEL_B == 1) |
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167 | #define CONSOLE_CONTROL 0xfffe3000 |
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168 | #define CONSOLE_DATA 0xfffe3001 |
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169 | #endif |
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170 | |
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171 | |
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172 | |
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173 | #define FOREVER 1 /* infinite loop */ |
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174 | |
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175 | #ifdef M147_INIT |
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176 | #undef EXTERN |
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177 | #define EXTERN |
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178 | #else |
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179 | #undef EXTERN |
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180 | #define EXTERN extern |
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181 | #endif |
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182 | |
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183 | /* |
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184 | * Define the time limits for RTEMS Test Suite test durations. |
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185 | * Long test and short test duration limits are provided. These |
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186 | * values are in seconds and need to be converted to ticks for the |
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187 | * application. |
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188 | * |
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189 | */ |
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190 | |
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191 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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192 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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193 | |
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194 | /* |
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195 | * Define the interrupt mechanism for Time Test 27 |
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196 | * |
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197 | * NOTE: Use the MPCSR vector for the MVME147 |
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198 | */ |
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199 | |
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200 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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201 | |
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202 | #define Install_tm27_vector( handler ) set_vector( (handler), \ |
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203 | SOFT_1_VECTOR, 1 ) |
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204 | |
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205 | #define Cause_tm27_intr() pcc->software_int_1_control = 0x0c |
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206 | /* generate level 4 sotware int. */ |
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207 | |
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208 | #define Clear_tm27_intr() pcc->software_int_1_control = 0x00 |
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209 | |
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210 | #define Lower_tm27_intr() |
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211 | |
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212 | |
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213 | /* miscellaneous stuff assumed to exist */ |
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214 | |
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215 | extern rtems_configuration_table BSP_Configuration; |
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216 | |
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217 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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218 | |
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219 | /* |
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220 | * Device Driver Table Entries |
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221 | */ |
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222 | |
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223 | /* |
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224 | * NOTE: Use the standard Console driver entry |
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225 | */ |
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226 | |
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227 | /* |
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228 | * NOTE: Use the standard Clock driver entry |
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229 | */ |
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230 | |
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231 | /* |
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232 | * How many libio files we want |
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233 | */ |
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234 | |
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235 | #define BSP_LIBIO_MAX_FDS 20 |
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236 | |
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237 | /* functions */ |
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238 | |
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239 | void bsp_cleanup( void ); |
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240 | |
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241 | m68k_isr_entry set_vector( |
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242 | rtems_isr_entry handler, |
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243 | rtems_vector_number vector, |
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244 | int type |
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245 | ); |
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246 | |
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247 | #ifdef __cplusplus |
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248 | } |
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249 | #endif |
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250 | |
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251 | #endif |
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252 | /* end of include file */ |
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253 | |
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