1 | /* bsp.h |
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2 | * |
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3 | * This include file contains all MVME147 board IO definitions. |
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4 | * |
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5 | * COPYRIGHT (c) 1989-1999. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.com/license/LICENSE. |
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11 | * |
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12 | * MVME147 port for TNI - Telecom Bretagne |
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13 | * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) |
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14 | * May 1996 |
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15 | * |
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16 | * $Id$ |
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17 | */ |
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18 | |
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19 | #ifndef __MVME147_h |
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20 | #define __MVME147_h |
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21 | |
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22 | #ifdef __cplusplus |
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23 | extern "C" { |
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24 | #endif |
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25 | |
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26 | #include <bspopts.h> |
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27 | |
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28 | #include <rtems.h> |
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29 | #include <clockdrv.h> |
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30 | #include <console.h> |
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31 | #include <iosupp.h> |
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32 | |
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33 | /* |
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34 | * confdefs.h overrides for this BSP: |
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35 | * - number of termios serial ports (defaults to 1) |
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36 | * - Interrupt stack space is not minimum if defined. |
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37 | */ |
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38 | |
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39 | /* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */ |
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40 | #define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024) |
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41 | |
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42 | /* Constants */ |
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43 | |
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44 | #define RAM_START 0x00005000 |
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45 | #define RAM_END 0x00400000 |
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46 | |
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47 | /* MVME 147 Peripheral controller chip |
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48 | see MVME147/D1, 3.4 */ |
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49 | |
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50 | struct pcc_map { |
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51 | /* 32 bit registers */ |
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52 | uint32_t dma_table_address; /* 0xfffe1000 */ |
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53 | uint32_t dma_data_address; /* 0xfffe1004 */ |
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54 | uint32_t dma_bytecount; /* 0xfffe1008 */ |
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55 | uint32_t dma_data_holding; /* 0xfffe100c */ |
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56 | |
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57 | /* 16 bit registers */ |
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58 | uint16_t timer1_preload; /* 0xfffe1010 */ |
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59 | uint16_t timer1_count; /* 0xfffe1012 */ |
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60 | uint16_t timer2_preload; /* 0xfffe1014 */ |
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61 | uint16_t timer2_count; /* 0xfffe1016 */ |
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62 | |
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63 | /* 8 bit registers */ |
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64 | uint8_t timer1_int_control; /* 0xfffe1018 */ |
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65 | uint8_t timer1_control; /* 0xfffe1019 */ |
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66 | uint8_t timer2_int_control; /* 0xfffe101a */ |
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67 | uint8_t timer2_control; /* 0xfffe101b */ |
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68 | |
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69 | uint8_t acfail_int_control; /* 0xfffe101c */ |
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70 | uint8_t watchdog_control; /* 0xfffe101d */ |
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71 | |
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72 | uint8_t printer_int_control; /* 0xfffe101e */ |
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73 | uint8_t printer_control; /* 0xfffe102f */ |
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74 | |
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75 | uint8_t dma_int_control; /* 0xfffe1020 */ |
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76 | uint8_t dma_control; /* 0xfffe1021 */ |
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77 | uint8_t bus_error_int_control; /* 0xfffe1022 */ |
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78 | uint8_t dma_status; /* 0xfffe1023 */ |
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79 | uint8_t abort_int_control; /* 0xfffe1024 */ |
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80 | uint8_t table_address_function_code; /* 0xfffe1025 */ |
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81 | uint8_t serial_port_int_control; /* 0xfffe1026 */ |
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82 | uint8_t general_purpose_control; /* 0xfffe1027 */ |
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83 | uint8_t lan_int_control; /* 0xfffe1028 */ |
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84 | uint8_t general_purpose_status; /* 0xfffe1029 */ |
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85 | uint8_t scsi_port_int_control; /* 0xfffe102a */ |
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86 | uint8_t slave_base_address; /* 0xfffe102b */ |
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87 | uint8_t software_int_1_control; /* 0xfffe102c */ |
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88 | uint8_t int_base_vector; /* 0xfffe102d */ |
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89 | uint8_t software_int_2_control; /* 0xfffe102e */ |
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90 | uint8_t revision_level; /* 0xfffe102f */ |
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91 | }; |
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92 | |
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93 | #define pcc ((volatile struct pcc_map * const) 0xfffe1000) |
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94 | |
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95 | #define z8530 0xfffe3001 |
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96 | |
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97 | |
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98 | /* interrupt vectors - see MVME146/D1 4.14 */ |
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99 | #define PCC_BASE_VECTOR 0x40 /* First user int */ |
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100 | #define SCC_VECTOR PCC_BASE_VECTOR+3 |
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101 | #define TIMER_1_VECTOR PCC_BASE_VECTOR+8 |
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102 | #define TIMER_2_VECTOR PCC_BASE_VECTOR+9 |
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103 | #define SOFT_1_VECTOR PCC_BASE_VECTOR+10 |
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104 | #define SOFT_2_VECTOR PCC_BASE_VECTOR+11 |
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105 | |
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106 | #define USE_CHANNEL_A 1 /* 1 = use channel A for console */ |
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107 | #define USE_CHANNEL_B 0 /* 1 = use channel B for console */ |
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108 | |
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109 | #if (USE_CHANNEL_A == 1) |
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110 | #define CONSOLE_CONTROL 0xfffe3002 |
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111 | #define CONSOLE_DATA 0xfffe3003 |
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112 | #elif (USE_CHANNEL_B == 1) |
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113 | #define CONSOLE_CONTROL 0xfffe3000 |
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114 | #define CONSOLE_DATA 0xfffe3001 |
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115 | #endif |
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116 | |
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117 | |
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118 | |
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119 | #define FOREVER 1 /* infinite loop */ |
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120 | |
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121 | #ifdef M147_INIT |
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122 | #undef EXTERN |
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123 | #define EXTERN |
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124 | #else |
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125 | #undef EXTERN |
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126 | #define EXTERN extern |
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127 | #endif |
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128 | |
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129 | /* |
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130 | * Define the time limits for RTEMS Test Suite test durations. |
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131 | * Long test and short test duration limits are provided. These |
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132 | * values are in seconds and need to be converted to ticks for the |
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133 | * application. |
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134 | * |
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135 | */ |
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136 | |
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137 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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138 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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139 | |
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140 | /* |
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141 | * Define the interrupt mechanism for Time Test 27 |
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142 | * |
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143 | * NOTE: Use the MPCSR vector for the MVME147 |
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144 | */ |
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145 | |
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146 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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147 | |
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148 | #define Install_tm27_vector( handler ) set_vector( (handler), \ |
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149 | SOFT_1_VECTOR, 1 ) |
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150 | |
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151 | #define Cause_tm27_intr() pcc->software_int_1_control = 0x0c |
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152 | /* generate level 4 sotware int. */ |
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153 | |
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154 | #define Clear_tm27_intr() pcc->software_int_1_control = 0x00 |
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155 | |
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156 | #define Lower_tm27_intr() |
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157 | |
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158 | |
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159 | /* miscellaneous stuff assumed to exist */ |
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160 | |
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161 | extern rtems_configuration_table BSP_Configuration; |
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162 | |
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163 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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164 | |
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165 | /* |
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166 | * Device Driver Table Entries |
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167 | */ |
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168 | |
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169 | /* |
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170 | * NOTE: Use the standard Console driver entry |
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171 | */ |
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172 | |
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173 | /* |
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174 | * NOTE: Use the standard Clock driver entry |
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175 | */ |
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176 | |
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177 | /* functions */ |
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178 | |
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179 | void bsp_cleanup( void ); |
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180 | |
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181 | m68k_isr_entry set_vector( |
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182 | rtems_isr_entry handler, |
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183 | rtems_vector_number vector, |
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184 | int type |
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185 | ); |
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186 | |
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187 | #ifdef __cplusplus |
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188 | } |
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189 | #endif |
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190 | |
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191 | #endif |
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192 | /* end of include file */ |
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193 | |
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