1 | /* bsp.h |
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2 | * |
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3 | * This include file contains all MVME147 board IO definitions. |
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4 | * |
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5 | * COPYRIGHT (c) 1989-1999. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.org/license/LICENSE. |
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11 | * |
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12 | * MVME147 port for TNI - Telecom Bretagne |
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13 | * by Dominique LE CAMPION (Dominique.LECAMPION@enst-bretagne.fr) |
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14 | * May 1996 |
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15 | */ |
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16 | |
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17 | #ifndef LIBBSP_M68K_MVME147_BSP_H |
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18 | #define LIBBSP_M68K_MVME147_BSP_H |
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19 | |
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20 | #include <bspopts.h> |
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21 | #include <bsp/default-initial-extension.h> |
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22 | |
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23 | #include <rtems.h> |
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24 | |
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25 | #ifdef __cplusplus |
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26 | extern "C" { |
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27 | #endif |
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28 | |
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29 | /* Constants */ |
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30 | |
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31 | #define RAM_START 0x00005000 |
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32 | #define RAM_END 0x00400000 |
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33 | |
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34 | /* MVME 147 Peripheral controller chip |
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35 | see MVME147/D1, 3.4 */ |
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36 | |
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37 | struct pcc_map { |
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38 | /* 32 bit registers */ |
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39 | uint32_t dma_table_address; /* 0xfffe1000 */ |
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40 | uint32_t dma_data_address; /* 0xfffe1004 */ |
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41 | uint32_t dma_bytecount; /* 0xfffe1008 */ |
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42 | uint32_t dma_data_holding; /* 0xfffe100c */ |
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43 | |
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44 | /* 16 bit registers */ |
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45 | uint16_t timer1_preload; /* 0xfffe1010 */ |
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46 | uint16_t timer1_count; /* 0xfffe1012 */ |
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47 | uint16_t timer2_preload; /* 0xfffe1014 */ |
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48 | uint16_t timer2_count; /* 0xfffe1016 */ |
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49 | |
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50 | /* 8 bit registers */ |
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51 | uint8_t timer1_int_control; /* 0xfffe1018 */ |
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52 | uint8_t timer1_control; /* 0xfffe1019 */ |
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53 | uint8_t timer2_int_control; /* 0xfffe101a */ |
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54 | uint8_t timer2_control; /* 0xfffe101b */ |
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55 | |
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56 | uint8_t acfail_int_control; /* 0xfffe101c */ |
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57 | uint8_t watchdog_control; /* 0xfffe101d */ |
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58 | |
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59 | uint8_t printer_int_control; /* 0xfffe101e */ |
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60 | uint8_t printer_control; /* 0xfffe102f */ |
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61 | |
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62 | uint8_t dma_int_control; /* 0xfffe1020 */ |
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63 | uint8_t dma_control; /* 0xfffe1021 */ |
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64 | uint8_t bus_error_int_control; /* 0xfffe1022 */ |
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65 | uint8_t dma_status; /* 0xfffe1023 */ |
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66 | uint8_t abort_int_control; /* 0xfffe1024 */ |
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67 | uint8_t table_address_function_code; /* 0xfffe1025 */ |
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68 | uint8_t serial_port_int_control; /* 0xfffe1026 */ |
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69 | uint8_t general_purpose_control; /* 0xfffe1027 */ |
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70 | uint8_t lan_int_control; /* 0xfffe1028 */ |
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71 | uint8_t general_purpose_status; /* 0xfffe1029 */ |
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72 | uint8_t scsi_port_int_control; /* 0xfffe102a */ |
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73 | uint8_t slave_base_address; /* 0xfffe102b */ |
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74 | uint8_t software_int_1_control; /* 0xfffe102c */ |
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75 | uint8_t int_base_vector; /* 0xfffe102d */ |
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76 | uint8_t software_int_2_control; /* 0xfffe102e */ |
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77 | uint8_t revision_level; /* 0xfffe102f */ |
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78 | }; |
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79 | |
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80 | #define pcc ((volatile struct pcc_map * const) 0xfffe1000) |
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81 | |
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82 | #define z8530 0xfffe3001 |
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83 | |
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84 | /* interrupt vectors - see MVME146/D1 4.14 */ |
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85 | #define PCC_BASE_VECTOR 0x40 /* First user int */ |
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86 | #define SCC_VECTOR PCC_BASE_VECTOR+3 |
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87 | #define TIMER_1_VECTOR PCC_BASE_VECTOR+8 |
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88 | #define TIMER_2_VECTOR PCC_BASE_VECTOR+9 |
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89 | #define SOFT_1_VECTOR PCC_BASE_VECTOR+10 |
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90 | #define SOFT_2_VECTOR PCC_BASE_VECTOR+11 |
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91 | |
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92 | #define USE_CHANNEL_A 1 /* 1 = use channel A for console */ |
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93 | #define USE_CHANNEL_B 0 /* 1 = use channel B for console */ |
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94 | |
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95 | #if (USE_CHANNEL_A == 1) |
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96 | #define CONSOLE_CONTROL 0xfffe3002 |
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97 | #define CONSOLE_DATA 0xfffe3003 |
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98 | #elif (USE_CHANNEL_B == 1) |
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99 | #define CONSOLE_CONTROL 0xfffe3000 |
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100 | #define CONSOLE_DATA 0xfffe3001 |
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101 | #endif |
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102 | |
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103 | extern rtems_isr_entry M68Kvec[]; /* vector table address */ |
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104 | |
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105 | /* functions */ |
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106 | |
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107 | rtems_isr_entry set_vector( |
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108 | rtems_isr_entry handler, |
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109 | rtems_vector_number vector, |
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110 | int type |
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111 | ); |
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112 | |
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113 | #ifdef __cplusplus |
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114 | } |
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115 | #endif |
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116 | |
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117 | #endif |
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