[ac7d5ef0] | 1 | /* Timer_init() |
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| 2 | * |
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| 3 | * This routine initializes the Z8036 timer on the MVME136 board. |
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| 4 | * |
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| 5 | * Input parameters: NONE |
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| 6 | * |
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| 7 | * Output parameters: NONE |
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| 8 | * |
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| 9 | * NOTE: This routine will not work if the optimizer is enabled |
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| 10 | * for some compilers. The multiple writes to the Z8036 |
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| 11 | * may be optimized away. |
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| 12 | * |
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| 13 | * It is important that the timer start/stop overhead be |
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| 14 | * determined when porting or modifying this code. |
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| 15 | * |
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[03f2154e] | 16 | * COPYRIGHT (c) 1989-1997. |
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[ac7d5ef0] | 17 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 18 | * Copyright assigned to U.S. Government, 1994. |
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[ac7d5ef0] | 19 | * |
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[98e4ebf5] | 20 | * The license and distribution terms for this file may be |
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| 21 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 22 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 23 | * |
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| 24 | * $Id$ |
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| 25 | */ |
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| 26 | |
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| 27 | |
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| 28 | #include <bsp.h> |
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[81d96577] | 29 | #include <zilog/z8036.h> |
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[ac7d5ef0] | 30 | |
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| 31 | #define TIMER 0xfffb0000 /* address of Z8036 on MVME136 */ |
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| 32 | |
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| 33 | int Ttimer_val; |
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| 34 | rtems_boolean Timer_driver_Find_average_overhead; |
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| 35 | |
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| 36 | rtems_isr timerisr(); |
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| 37 | |
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| 38 | void Timer_initialize() |
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| 39 | { |
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| 40 | (void) set_vector( timerisr, 66, 0 ); /* install ISR */ |
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| 41 | |
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| 42 | Ttimer_val = 0; /* clear timer ISR count */ |
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| 43 | Z8x36_WRITE( TIMER, MASTER_INTR, 0x01 ); /* reset */ |
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| 44 | Z8x36_WRITE( TIMER, MASTER_INTR, 0x00 ); /* clear reset */ |
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| 45 | Z8x36_WRITE( TIMER, MASTER_INTR, 0xe2 ); /* disable lower chain, no vec */ |
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| 46 | /* set right justified addr */ |
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| 47 | /* and master int enable */ |
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| 48 | Z8x36_WRITE( TIMER, CT1_MODE_SPEC, 0x80 ); /* T1 continuous, and */ |
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| 49 | /* cycle/pulse output */ |
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| 50 | |
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| 51 | *((rtems_unsigned16 *)0xfffb0016) = 0x0000; /* write countdown value */ |
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| 52 | /* |
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| 53 | Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x00 ); |
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| 54 | Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0x00 ); |
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| 55 | */ |
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| 56 | Z8x36_WRITE( TIMER, MASTER_CFG, 0xc4 ); /* enable timer1 */ |
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| 57 | |
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| 58 | Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xc6 ); /* set INTR enable (IE), */ |
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| 59 | /* trigger command */ |
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| 60 | /* (TCB) and gate */ |
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| 61 | /* command (GCB) bits */ |
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| 62 | *((rtems_unsigned8 *)0xfffb0038) &= 0xfd; /* enable timer INTR on */ |
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| 63 | /* VME controller */ |
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| 64 | } |
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| 65 | |
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| 66 | #define AVG_OVERHEAD 6 /* It typically takes 3.0 microseconds */ |
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| 67 | /* (6 countdowns) to start/stop the timer. */ |
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| 68 | #define LEAST_VALID 10 /* Don't trust a value lower than this */ |
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| 69 | |
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| 70 | int Read_timer() |
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| 71 | { |
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| 72 | /* |
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| 73 | rtems_unsigned8 msb, lsb; |
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| 74 | */ |
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| 75 | rtems_unsigned32 remaining, total; |
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| 76 | |
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| 77 | Z8x36_WRITE( TIMER, CT1_CMD_STATUS, 0xce ); /* read the counter value */ |
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| 78 | remaining = 0xffff - *((rtems_unsigned16 *) 0xfffb0010); |
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| 79 | /* |
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| 80 | Z8x36_READ( TIMER, CT1_CUR_CNT_MSB, msb ); |
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| 81 | Z8x36_READ( TIMER, CT1_CUR_CNT_LSB, lsb ); |
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| 82 | |
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| 83 | remaining = 0xffff - ((msb << 8) + lsb); |
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| 84 | */ |
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| 85 | total = (Ttimer_val * 0x10000) + remaining; |
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| 86 | |
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| 87 | if ( Timer_driver_Find_average_overhead == 1 ) |
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| 88 | return total; /* in one-half microsecond units */ |
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| 89 | |
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| 90 | else { |
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| 91 | if ( total < LEAST_VALID ) |
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| 92 | return 0; /* below timer resolution */ |
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| 93 | return (total-AVG_OVERHEAD) >> 1; |
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| 94 | } |
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| 95 | } |
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| 96 | |
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| 97 | rtems_status_code Empty_function( void ) |
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| 98 | { |
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| 99 | return RTEMS_SUCCESSFUL; |
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| 100 | } |
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| 101 | |
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| 102 | void Set_find_average_overhead( |
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| 103 | rtems_boolean find_flag |
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| 104 | ) |
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| 105 | { |
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| 106 | Timer_driver_Find_average_overhead = find_flag; |
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| 107 | } |
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