source: rtems/c/src/lib/libbsp/m68k/mvme136/include/bsp.h @ ac7d5ef0

4.104.114.84.95
Last change on this file since ac7d5ef0 was ac7d5ef0, checked in by Joel Sherrill <joel.sherrill@…>, on May 11, 1995 at 5:39:37 PM

Initial revision

  • Property mode set to 100644
File size: 4.2 KB
Line 
1/*  bsp.h
2 *
3 *  This include file contains all MVME136 board IO definitions.
4 *
5 *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
6 *  On-Line Applications Research Corporation (OAR).
7 *  All rights assigned to U.S. Government, 1994.
8 *
9 *  This material may be reproduced by or for the U.S. Government pursuant
10 *  to the copyright license under the clause at DFARS 252.227-7013.  This
11 *  notice must appear in all copies of this file and its derivatives.
12 *
13 *  $Id$
14 */
15
16#ifndef __MVME136_h
17#define __MVME136_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems.h>
24#include <iosupp.h>
25
26/*
27 *  Define the time limits for RTEMS Test Suite test durations.
28 *  Long test and short test duration limits are provided.  These
29 *  values are in seconds and need to be converted to ticks for the
30 *  application.
31 *
32 */
33
34#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
35#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
36
37/*
38 *  Define the interrupt mechanism for Time Test 27
39 *
40 *  NOTE: Use the MPCSR vector for the MVME136
41 */
42
43#define MUST_WAIT_FOR_INTERRUPT 0
44
45#define Install_tm27_vector( handler ) set_vector( (handler), 75, 1 )
46
47#define Cause_tm27_intr()  (*(volatile rtems_unsigned8 *)0xfffb006b) = 0x80
48
49#define Clear_tm27_intr()  (*(volatile rtems_unsigned8 *)0xfffb006b) = 0x00
50
51#define Lower_tm27_intr()
52
53/*
54 *  Simple spin delay in microsecond units for device drivers.
55 *  This is very dependent on the clock speed of the target.
56 */
57
58#define delay( microseconds ) \
59  { register rtems_unsigned32 _delay=(microseconds); \
60    register rtems_unsigned32 _tmp=123; \
61    asm volatile( "0: \
62                     nbcd      %0 ; \
63                     nbcd      %0 ; \
64                     dbf       %1,0b" \
65                  : "=d" (_tmp), "=d" (_delay) \
66                  : "0"  (_tmp), "1"  (_delay) ); \
67  }
68
69/* Constants */
70
71#define RAM_START 0
72#define RAM_END   0x100000
73
74#define M681ADDR      0xfffb0040         /* address of the M68681 chip */
75#define RXRDYB        0x01               /* status reg recv ready mask */
76#define TXRDYB        0x04               /* status reg trans ready mask */
77#define PARITYERR     0x20               /* status reg parity error mask */
78#define FRAMEERR      0x40               /* status reg frame error mask */
79
80
81#define FOREVER       1                  /* infinite loop */
82
83/* Structures */
84
85struct r_m681_info {
86  char fill1[ 5 ];                       /* channel A regs ( not used ) */
87  char isr;                              /* interrupt status reg */
88  char fill2[ 2 ];                       /* counter regs (not used) */
89  char mr1mr2b;                          /* MR1B and MR2B regs */
90  char srb;                              /* status reg channel B */
91  char fill3;                            /* do not access */
92  char rbb;                              /* receive buffer channel B */
93  char ivr;                              /* interrupt vector register */
94};
95
96struct w_m681_info {
97  char fill1[ 4 ];                       /* channel A regs (not used) */
98  char acr;                              /* auxillary control reg */
99  char imr;                              /* interrupt mask reg */
100  char fill2[ 2 ];                       /* counter regs (not used) */
101  char mr1mr2b;                          /* MR1B and MR2B regs */
102  char csrb;                             /* clock select reg */
103  char crb;                              /* command reg */
104  char tbb;                              /* transmit buffer channel B */
105  char ivr;                              /* interrupt vector register */
106};
107
108#ifdef M136_INIT
109#undef EXTERN
110#define EXTERN
111#else
112#undef EXTERN
113#define EXTERN extern
114#endif
115
116/* miscellaneous stuff assumed to exist */
117
118extern rtems_configuration_table BSP_Configuration;
119
120/* M68681 DUART chip register variables */
121
122EXTERN volatile struct r_m681_info *_Read_m681;  /* M68681 read registers */
123EXTERN volatile struct w_m681_info *_Write_m681; /* M68681 write registers */
124
125extern m68k_isr     M68Kvec[];   /* vector table address */
126
127/* functions */
128
129void bsp_cleanup( void );
130
131m68k_isr set_vector(
132  rtems_isr_entry     handler,
133  rtems_vector_number vector,
134  int                 type
135);
136
137#ifdef __cplusplus
138}
139#endif
140
141#endif
142/* end of include file */
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