[ac7d5ef0] | 1 | /* bsp.h |
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| 2 | * |
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| 3 | * This include file contains all MVME136 board IO definitions. |
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| 4 | * |
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[60b791ad] | 5 | * COPYRIGHT (c) 1989-1998. |
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[ac7d5ef0] | 6 | * On-Line Applications Research Corporation (OAR). |
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[03f2154e] | 7 | * Copyright assigned to U.S. Government, 1994. |
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[ac7d5ef0] | 8 | * |
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[98e4ebf5] | 9 | * The license and distribution terms for this file may be |
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| 10 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 11 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 12 | * |
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| 13 | * $Id$ |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef __MVME136_h |
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| 17 | #define __MVME136_h |
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| 18 | |
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| 19 | #ifdef __cplusplus |
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| 20 | extern "C" { |
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| 21 | #endif |
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| 22 | |
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| 23 | #include <rtems.h> |
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[3a4ae6c] | 24 | #include <clockdrv.h> |
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| 25 | #include <console.h> |
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[ac7d5ef0] | 26 | #include <iosupp.h> |
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| 27 | |
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| 28 | /* |
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| 29 | * Define the time limits for RTEMS Test Suite test durations. |
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| 30 | * Long test and short test duration limits are provided. These |
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| 31 | * values are in seconds and need to be converted to ticks for the |
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| 32 | * application. |
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| 33 | * |
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| 34 | */ |
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| 35 | |
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| 36 | #define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ |
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| 37 | #define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ |
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| 38 | |
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| 39 | /* |
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| 40 | * Define the interrupt mechanism for Time Test 27 |
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| 41 | * |
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| 42 | * NOTE: Use the MPCSR vector for the MVME136 |
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| 43 | */ |
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| 44 | |
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| 45 | #define MUST_WAIT_FOR_INTERRUPT 0 |
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| 46 | |
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| 47 | #define Install_tm27_vector( handler ) set_vector( (handler), 75, 1 ) |
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| 48 | |
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| 49 | #define Cause_tm27_intr() (*(volatile rtems_unsigned8 *)0xfffb006b) = 0x80 |
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| 50 | |
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| 51 | #define Clear_tm27_intr() (*(volatile rtems_unsigned8 *)0xfffb006b) = 0x00 |
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| 52 | |
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| 53 | #define Lower_tm27_intr() |
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| 54 | |
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| 55 | /* |
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| 56 | * Simple spin delay in microsecond units for device drivers. |
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| 57 | * This is very dependent on the clock speed of the target. |
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| 58 | */ |
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| 59 | |
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| 60 | #define delay( microseconds ) \ |
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| 61 | { register rtems_unsigned32 _delay=(microseconds); \ |
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| 62 | register rtems_unsigned32 _tmp=123; \ |
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| 63 | asm volatile( "0: \ |
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| 64 | nbcd %0 ; \ |
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| 65 | nbcd %0 ; \ |
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| 66 | dbf %1,0b" \ |
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| 67 | : "=d" (_tmp), "=d" (_delay) \ |
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| 68 | : "0" (_tmp), "1" (_delay) ); \ |
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| 69 | } |
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| 70 | |
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| 71 | /* Constants */ |
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| 72 | |
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| 73 | #define RAM_START 0 |
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| 74 | #define RAM_END 0x100000 |
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| 75 | |
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| 76 | #define M681ADDR 0xfffb0040 /* address of the M68681 chip */ |
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| 77 | #define RXRDYB 0x01 /* status reg recv ready mask */ |
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| 78 | #define TXRDYB 0x04 /* status reg trans ready mask */ |
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| 79 | #define PARITYERR 0x20 /* status reg parity error mask */ |
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| 80 | #define FRAMEERR 0x40 /* status reg frame error mask */ |
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| 81 | |
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| 82 | |
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| 83 | #define FOREVER 1 /* infinite loop */ |
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| 84 | |
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| 85 | /* Structures */ |
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| 86 | |
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| 87 | struct r_m681_info { |
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| 88 | char fill1[ 5 ]; /* channel A regs ( not used ) */ |
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| 89 | char isr; /* interrupt status reg */ |
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| 90 | char fill2[ 2 ]; /* counter regs (not used) */ |
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| 91 | char mr1mr2b; /* MR1B and MR2B regs */ |
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| 92 | char srb; /* status reg channel B */ |
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| 93 | char fill3; /* do not access */ |
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| 94 | char rbb; /* receive buffer channel B */ |
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| 95 | char ivr; /* interrupt vector register */ |
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| 96 | }; |
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| 97 | |
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| 98 | struct w_m681_info { |
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| 99 | char fill1[ 4 ]; /* channel A regs (not used) */ |
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| 100 | char acr; /* auxillary control reg */ |
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| 101 | char imr; /* interrupt mask reg */ |
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| 102 | char fill2[ 2 ]; /* counter regs (not used) */ |
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| 103 | char mr1mr2b; /* MR1B and MR2B regs */ |
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| 104 | char csrb; /* clock select reg */ |
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| 105 | char crb; /* command reg */ |
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| 106 | char tbb; /* transmit buffer channel B */ |
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| 107 | char ivr; /* interrupt vector register */ |
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| 108 | }; |
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| 109 | |
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| 110 | #ifdef M136_INIT |
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| 111 | #undef EXTERN |
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| 112 | #define EXTERN |
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| 113 | #else |
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| 114 | #undef EXTERN |
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| 115 | #define EXTERN extern |
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| 116 | #endif |
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| 117 | |
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| 118 | /* miscellaneous stuff assumed to exist */ |
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| 119 | |
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| 120 | extern rtems_configuration_table BSP_Configuration; |
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| 121 | |
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| 122 | /* M68681 DUART chip register variables */ |
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| 123 | |
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| 124 | EXTERN volatile struct r_m681_info *_Read_m681; /* M68681 read registers */ |
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| 125 | EXTERN volatile struct w_m681_info *_Write_m681; /* M68681 write registers */ |
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| 126 | |
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[497428a2] | 127 | extern m68k_isr_entry M68Kvec[]; /* vector table address */ |
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[ac7d5ef0] | 128 | |
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[3a4ae6c] | 129 | /* |
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| 130 | * Device Driver Table Entries |
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| 131 | */ |
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| 132 | |
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| 133 | /* |
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| 134 | * NOTE: Use the standard Console driver entry |
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| 135 | */ |
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| 136 | |
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| 137 | /* |
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| 138 | * NOTE: Use the standard Clock driver entry |
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| 139 | */ |
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| 140 | |
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[ac7d5ef0] | 141 | /* functions */ |
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| 142 | |
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| 143 | void bsp_cleanup( void ); |
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| 144 | |
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[497428a2] | 145 | m68k_isr_entry set_vector( |
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[ac7d5ef0] | 146 | rtems_isr_entry handler, |
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| 147 | rtems_vector_number vector, |
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| 148 | int type |
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| 149 | ); |
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| 150 | |
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| 151 | #ifdef __cplusplus |
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| 152 | } |
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| 153 | #endif |
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| 154 | |
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| 155 | #endif |
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| 156 | /* end of include file */ |
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