1 | /* Clock_init() |
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2 | * |
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3 | * This routine initializes the Z80386 1 on the MVME136 board. |
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4 | * The tick frequency is 1 millisecond. |
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5 | * |
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6 | * Input parameters: NONE |
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7 | * |
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8 | * Output parameters: NONE |
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9 | * |
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10 | * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * All rights assigned to U.S. Government, 1994. |
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13 | * |
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14 | * This material may be reproduced by or for the U.S. Government pursuant |
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15 | * to the copyright license under the clause at DFARS 252.227-7013. This |
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16 | * notice must appear in all copies of this file and its derivatives. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include <stdlib.h> |
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22 | |
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23 | #include <rtems.h> |
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24 | #include <bsp.h> |
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25 | #include <clockdrv.h> |
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26 | #include <z8036.h> |
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27 | |
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28 | #define MICRVAL 0xe2 /* disable lower chain, no vec */ |
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29 | /* set right justified addr */ |
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30 | /* and master int enable */ |
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31 | #define MCCRVAL 0xc4 /* enable T1 and port B */ |
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32 | /* timers independent */ |
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33 | #define MS_COUNT 0x07d0 /* T1's countdown constant (1 ms) */ |
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34 | #define T1MSRVAL 0x80 /* T1 cont. cycle/pulse output */ |
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35 | #define T1CSRVAL 0xc6 /* enable interrupt, allow and */ |
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36 | /* and trigger countdown */ |
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37 | |
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38 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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39 | volatile rtems_unsigned32 Clock_driver_ticks; |
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40 | /* ticks since initialization */ |
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41 | rtems_isr_entry Old_ticker; |
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42 | |
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43 | rtems_device_driver Clock_initialize( |
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44 | rtems_device_major_number major, |
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45 | rtems_device_minor_number minor, |
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46 | void *pargp, |
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47 | rtems_id tid, |
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48 | rtems_unsigned32 *rval |
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49 | ) |
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50 | { |
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51 | Install_clock( Clock_isr ); |
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52 | } |
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53 | |
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54 | void ReInstall_clock( |
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55 | rtems_isr_entry clock_isr |
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56 | ) |
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57 | { |
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58 | rtems_unsigned32 isrlevel; |
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59 | |
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60 | rtems_interrupt_disable( isrlevel ); |
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61 | (void) set_vector( clock_isr, 66, 1 ); |
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62 | rtems_interrupt_enable( isrlevel ); |
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63 | } |
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64 | |
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65 | void Install_clock( |
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66 | rtems_isr_entry clock_isr |
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67 | ) |
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68 | { |
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69 | volatile struct z8036_map *timer; |
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70 | |
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71 | Clock_driver_ticks = 0; |
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72 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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73 | |
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74 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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75 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, 66, 1 ); |
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76 | timer = (struct z8036_map *) 0xfffb0000; |
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77 | timer->MASTER_INTR = MICRVAL; |
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78 | timer->CT1_MODE_SPEC = T1MSRVAL; |
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79 | |
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80 | *((rtems_unsigned16 *)0xfffb0016) = MS_COUNT; /* write countdown value */ |
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81 | /* |
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82 | timer->CT1_TIME_CONST_MSB = (MS_COUNT >> 8); |
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83 | timer->CT1_TIME_CONST_LSB = (MS_COUNT & 0xff); |
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84 | */ |
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85 | timer->MASTER_CFG = MCCRVAL; |
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86 | timer->CT1_CMD_STATUS = T1CSRVAL; |
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87 | |
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88 | /* |
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89 | * Enable interrupt via VME interrupt mask register |
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90 | */ |
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91 | (*(rtems_unsigned8 *)0xfffb0038) &= 0xfd; |
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92 | |
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93 | |
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94 | atexit( Clock_exit ); |
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95 | } |
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96 | |
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97 | } |
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98 | |
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99 | void Clock_exit( void ) |
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100 | { |
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101 | volatile struct z8036_map *timer; |
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102 | |
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103 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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104 | timer = (struct z8036_map *) 0xfffb0000; |
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105 | timer->MASTER_INTR = 0x62; |
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106 | timer->CT1_MODE_SPEC = 0x00; |
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107 | timer->MASTER_CFG = 0xf4; |
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108 | timer->CT1_CMD_STATUS = 0x00; |
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109 | /* do not restore old vector */ |
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110 | } |
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111 | } |
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