[ac7d5ef0] | 1 | /* Clock_init() |
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| 2 | * |
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| 3 | * This routine initializes the Z80386 1 on the MVME136 board. |
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| 4 | * The tick frequency is 1 millisecond. |
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| 5 | * |
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| 6 | * Input parameters: NONE |
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| 7 | * |
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| 8 | * Output parameters: NONE |
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| 9 | * |
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[08311cc3] | 10 | * COPYRIGHT (c) 1989-1999. |
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[ac7d5ef0] | 11 | * On-Line Applications Research Corporation (OAR). |
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| 12 | * |
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[98e4ebf5] | 13 | * The license and distribution terms for this file may be |
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| 14 | * found in the file LICENSE in this distribution or at |
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[03f2154e] | 15 | * http://www.OARcorp.com/rtems/license.html. |
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[ac7d5ef0] | 16 | * |
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| 17 | * $Id$ |
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| 18 | */ |
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| 19 | |
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| 20 | #include <stdlib.h> |
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| 21 | |
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| 22 | #include <bsp.h> |
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[3a4ae6c] | 23 | #include <rtems/libio.h> |
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[81d96577] | 24 | #include <zilog/z8036.h> |
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[ac7d5ef0] | 25 | |
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| 26 | #define MICRVAL 0xe2 /* disable lower chain, no vec */ |
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| 27 | /* set right justified addr */ |
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| 28 | /* and master int enable */ |
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| 29 | #define MCCRVAL 0xc4 /* enable T1 and port B */ |
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| 30 | /* timers independent */ |
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| 31 | #define MS_COUNT 0x07d0 /* T1's countdown constant (1 ms) */ |
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| 32 | #define T1MSRVAL 0x80 /* T1 cont. cycle/pulse output */ |
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| 33 | #define T1CSRVAL 0xc6 /* enable interrupt, allow and */ |
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| 34 | /* and trigger countdown */ |
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| 35 | |
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[3a4ae6c] | 36 | #define TIMER 0xfffb0000 |
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| 37 | #define RELOAD 0x24 /* clr IP & IUS,allow countdown */ |
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| 38 | |
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| 39 | #define CLOCK_VECTOR 66 |
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| 40 | |
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[ac7d5ef0] | 41 | rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ |
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[3a4ae6c] | 42 | |
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| 43 | volatile rtems_unsigned32 Clock_driver_ticks; /* ticks since initialization */ |
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| 44 | |
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[ac7d5ef0] | 45 | rtems_isr_entry Old_ticker; |
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| 46 | |
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[3a4ae6c] | 47 | void Clock_exit( void ); |
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[ac7d5ef0] | 48 | |
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[3a4ae6c] | 49 | /* |
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| 50 | * These are set by clock driver during its init |
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| 51 | */ |
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| 52 | |
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| 53 | rtems_device_major_number rtems_clock_major = ~0; |
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| 54 | rtems_device_minor_number rtems_clock_minor; |
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| 55 | |
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| 56 | /* |
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| 57 | * ISR Handler |
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| 58 | */ |
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| 59 | |
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| 60 | rtems_isr Clock_isr( |
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| 61 | rtems_vector_number vector |
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[ac7d5ef0] | 62 | ) |
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| 63 | { |
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[3a4ae6c] | 64 | Clock_driver_ticks += 1; |
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| 65 | ((volatile struct z8036_map *) TIMER)->CT1_CMD_STATUS = RELOAD; |
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[ac7d5ef0] | 66 | |
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[3a4ae6c] | 67 | if ( Clock_isrs == 1 ) { |
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| 68 | rtems_clock_tick(); |
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| 69 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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| 70 | } |
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| 71 | else |
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| 72 | Clock_isrs -= 1; |
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[ac7d5ef0] | 73 | } |
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| 74 | |
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| 75 | void Install_clock( |
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| 76 | rtems_isr_entry clock_isr |
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| 77 | ) |
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| 78 | { |
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| 79 | volatile struct z8036_map *timer; |
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| 80 | |
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| 81 | Clock_driver_ticks = 0; |
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| 82 | Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; |
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| 83 | |
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| 84 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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[3a4ae6c] | 85 | Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); |
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[ac7d5ef0] | 86 | timer = (struct z8036_map *) 0xfffb0000; |
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| 87 | timer->MASTER_INTR = MICRVAL; |
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| 88 | timer->CT1_MODE_SPEC = T1MSRVAL; |
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| 89 | |
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[3a4ae6c] | 90 | *((rtems_unsigned16 *)0xfffb0016) = MS_COUNT; /* write countdown value */ |
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| 91 | |
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| 92 | /* |
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| 93 | * timer->CT1_TIME_CONST_MSB = (MS_COUNT >> 8); |
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| 94 | * timer->CT1_TIME_CONST_LSB = (MS_COUNT & 0xff); |
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| 95 | */ |
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| 96 | |
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[ac7d5ef0] | 97 | timer->MASTER_CFG = MCCRVAL; |
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| 98 | timer->CT1_CMD_STATUS = T1CSRVAL; |
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| 99 | |
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[3a4ae6c] | 100 | /* |
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| 101 | * Enable interrupt via VME interrupt mask register |
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| 102 | */ |
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[ac7d5ef0] | 103 | (*(rtems_unsigned8 *)0xfffb0038) &= 0xfd; |
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| 104 | |
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| 105 | atexit( Clock_exit ); |
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| 106 | } |
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| 107 | |
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| 108 | } |
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| 109 | |
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| 110 | void Clock_exit( void ) |
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| 111 | { |
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| 112 | volatile struct z8036_map *timer; |
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| 113 | |
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| 114 | if ( BSP_Configuration.ticks_per_timeslice ) { |
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| 115 | timer = (struct z8036_map *) 0xfffb0000; |
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| 116 | timer->MASTER_INTR = 0x62; |
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| 117 | timer->CT1_MODE_SPEC = 0x00; |
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| 118 | timer->MASTER_CFG = 0xf4; |
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| 119 | timer->CT1_CMD_STATUS = 0x00; |
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| 120 | /* do not restore old vector */ |
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| 121 | } |
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| 122 | } |
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[3a4ae6c] | 123 | |
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| 124 | rtems_device_driver Clock_initialize( |
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| 125 | rtems_device_major_number major, |
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| 126 | rtems_device_minor_number minor, |
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| 127 | void *pargp |
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| 128 | ) |
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| 129 | { |
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| 130 | Install_clock( Clock_isr ); |
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| 131 | |
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| 132 | /* |
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| 133 | * make major/minor avail to others such as shared memory driver |
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| 134 | */ |
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| 135 | |
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| 136 | rtems_clock_major = major; |
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| 137 | rtems_clock_minor = minor; |
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| 138 | |
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| 139 | return RTEMS_SUCCESSFUL; |
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| 140 | } |
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| 141 | |
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| 142 | rtems_device_driver Clock_control( |
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| 143 | rtems_device_major_number major, |
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| 144 | rtems_device_minor_number minor, |
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| 145 | void *pargp |
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| 146 | ) |
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| 147 | { |
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[9700578] | 148 | rtems_unsigned32 isrlevel; |
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[3a4ae6c] | 149 | rtems_libio_ioctl_args_t *args = pargp; |
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| 150 | |
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| 151 | if (args == 0) |
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| 152 | goto done; |
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| 153 | |
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| 154 | /* |
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| 155 | * This is hokey, but until we get a defined interface |
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| 156 | * to do this, it will just be this simple... |
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| 157 | */ |
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| 158 | |
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| 159 | if (args->command == rtems_build_name('I', 'S', 'R', ' ')) |
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| 160 | { |
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| 161 | Clock_isr(CLOCK_VECTOR); |
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| 162 | } |
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| 163 | else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) |
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| 164 | { |
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[9700578] | 165 | rtems_interrupt_disable( isrlevel ); |
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| 166 | (void) set_vector( args->buffer, CLOCK_VECTOR, 1 ); |
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| 167 | rtems_interrupt_enable( isrlevel ); |
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[3a4ae6c] | 168 | } |
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| 169 | |
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| 170 | done: |
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| 171 | return RTEMS_SUCCESSFUL; |
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| 172 | } |
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